From: hades Date: Thu, 10 May 2001 18:29:24 +0000 (+0000) Subject: Change in shower read out for SRAM switch only, ZERO_SUPPRESSION set by X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d223f57097a090fe33c351168e7d1cf855519b5a;p=daqdata.git Change in shower read out for SRAM switch only, ZERO_SUPPRESSION set by slow control ... MP --- diff --git a/hadaq/hwship.c b/hadaq/hwship.c index 2db1f9c..167f758 100644 --- a/hadaq/hwship.c +++ b/hadaq/hwship.c @@ -1,4 +1,4 @@ -static char *rcsId = "$Header: /misc/hadesprojects/daq/cvsroot/eventbuilder/hadaq/Attic/hwship.c,v 6.15 2001-05-10 13:04:25 hades Exp $"; +static char *rcsId = "$Header: /misc/hadesprojects/daq/cvsroot/eventbuilder/hadaq/Attic/hwship.c,v 6.16 2001-05-10 18:29:24 hades Exp $"; #include #include @@ -12,20 +12,17 @@ static char *rcsId = "$Header: /misc/hadesprojects/daq/cvsroot/eventbuilder/hada #include "ipc_basis.h" #include "hwship.h" -/* set this to 8 for zero supp on, 0 for off */ -#define ZEROSUP 8 - static int bankRequested(HwShip *my) { UInt2 val; - val = LVme_tstBitL(my->lvme, LVL2_STAT_READ, 6); + val = LVme_tstBitL(my->lvme, LVL2_ACCESS_VMEREG, 6); return val; } static int bankConfirmed(HwShip *my) { UInt2 val; - val = LVme_tstBitL(my->lvme, LVL2_STAT_READ, 8); + val = LVme_tstBitL(my->lvme, LVL2_ACCESS_VMEREG, 7); return val; } @@ -55,6 +52,9 @@ int conHwShip(HwShip * my, const char *name, const Param *param) msglog(LOG_ERR, "HwShip on %p not found\n", cardBase); return -1; } + /* Select VME-accessible register of LVL2-controller */ + LVme_setW(my->lvme, LVL2_SEL_VMEREG, LVL2_SELMEM_VMEREG); + my->trigNr = 0; my->currAddr = 0xffffffff; /* behind end of memory */ @@ -72,8 +72,8 @@ void HwShip_requestBuffer(HwShip *my) { #ifndef NDEBUG msglog(LOG_DEBUG, "wait for data\n"); #endif - while ((LVme_getL(my->lvme, LVL2_STAT_READ) >> 16 & 0xffff) <= 2) { -#if 0 + while ((LVme_getL(my->lvme, LVL2_ACCESS_VMEREG) >> 16 & 0xffff) <= 2) { +#if 1 struct timespec tS, *t = &tS; t->tv_sec = 0; t->tv_nsec = 020000000; @@ -81,11 +81,10 @@ void HwShip_requestBuffer(HwShip *my) { #endif } #ifndef NDEBUG - msglog(LOG_DEBUG, - "%d evts available\n", LVme_getL(my->lvme, LVL2_STAT_READ) >> 9 & 0x7f); + msglog(LOG_DEBUG, "data available\n"); #endif i = bankRequested(my) == 1 ? 0 : 1; - LVme_setW(my->lvme, LVL2_STAT_WRITE, (i << 1) | ZEROSUP); + LVme_setL(my->lvme, LVL2_ACCESS_VMEREG, i); my->currAddr = LVL2_OFFSET + 0x4; } diff --git a/hadaq/hwshow.c b/hadaq/hwshow.c index fb80b93..1fc3ebc 100644 --- a/hadaq/hwshow.c +++ b/hadaq/hwshow.c @@ -1,4 +1,4 @@ -static char *rcsId = "$Header: /misc/hadesprojects/daq/cvsroot/eventbuilder/hadaq/Attic/hwshow.c,v 6.17 2001-04-12 12:28:05 hades Exp $"; +static char *rcsId = "$Header: /misc/hadesprojects/daq/cvsroot/eventbuilder/hadaq/Attic/hwshow.c,v 6.18 2001-05-10 18:29:24 hades Exp $"; #define _POSIX_C_SOURCE 199309L @@ -88,7 +88,7 @@ void Hardware_waitForTrigger(Hardware *my, void *subEvt) for (i = 0; i < NSHIPS; i++) { while (HwShip_isBusy(my->ship[i])) { -#if 0 +#if 1 /* * This sleep prevents a tight loop which stops work on real * time systems if the priority of readout is not lowered. diff --git a/hadaq/ipc_basis.h b/hadaq/ipc_basis.h index 987fe12..be45c59 100644 --- a/hadaq/ipc_basis.h +++ b/hadaq/ipc_basis.h @@ -12,6 +12,7 @@ */ #if !defined(IPC_BASIS) +#include #define IPC_1_BASIS 0xc00000 #define IPC_2_BASIS 0xc00000 #define IPC_ASPACE 0x00100000 @@ -21,6 +22,9 @@ #define RC3_ACCESS_OFF 0x04022 #define RC3_ACCESS_ON 0x04020 +#define RC3_VME_REG_B 0x0401a +#define RC3_VME_REG_A 0x04018 +#define RC3_LM_BADDRREG 0x04016 #define RC3_ERRREG_B 0x04014 #define RC3_ERRREG_A 0x04012 #define RC3_BYSREG_B 0x04010 @@ -35,6 +39,16 @@ #define ADDON_ACCESS_OFF 0x02012 #define ADDON_ACCESS_ON 0x02010 +#define ADDON_SELECT_DEV 0x0213c +#define ADDON_SUBEVT_ID_2 0x02126 +#define ADDON_SUBEVT_ID_1 0x02124 +#define ADDON_THRESHOLD_2 0x0211c +#define ADDON_THRESHOLD_1 0x0211a +#define ADDON_STATUS_2 0x02118 +#define ADDON_STATUS_1 0x02116 +#define ADDON_FIFO_LD_STR 0x02114 +#define ADDON_FIFO_LD_DISAB 0x02112 +#define ADDON_FIFO_LD_ENAB 0x02110 #define ADDON_FIFO_RESET 0x02108 #define ADDON_SHOWER_MODE 0x02106 #define ADDON_TEST_MODE 0x02104 @@ -43,9 +57,8 @@ #define LVL2_ACCESS_OFF 0x0101e #define LVL2_ACCESS_ON 0x0101c -#define LVL2_SUBID_WRITE 0x0100e -#define LVL2_STAT_READ 0x0100c -#define LVL2_STAT_WRITE 0x0100a +#define LVL2_ACCESS_VMEREG 0x0100c +#define LVL2_SEL_VMEREG 0x0100a #define LVL2_VME_RCLK 0x01008 #define LVL2_SHOWER_MODE 0x01006 #define LVL2_TEST_MODE 0x01004 @@ -90,6 +103,7 @@ #define ID_CTR_ACCESS_ON 0x00600 #define ID_CTR_ACCESS_OFF 0x00200 +#define ID_CTR_SW_TO_ADDON 0x000e0 #define ID_CTR_SHOWER_MODE 0x000c0 #define ID_CTR_TEST_MODE 0x000a0 #define ID_CTR_CONF_MODE 0x00080 @@ -174,13 +188,14 @@ These codes/flags are just used by the controlling C-software #define SEL_SRAM_B 0x2 #define SEL_LVL2_PIPE 0x0 #define SEL_LVL2_BUFFER 0x1 +#define SUBEVT_BUILDER_ID 0x7575 -/* Layers, Rows, Columns per Shower Detector segment */ -/* -#define D_LAYS 3 -#define D_ROWS 32 -#define D_COLS 32 -*/ +/* VME accessible LVL2_Registers */ +#define LVL2_LVL2MODE_VMEREG 0x1 +#define LVL2_SUBID_VMEREG 0x2 +#define LVL2_SELMEM_VMEREG 0x3 +#define LVL2_STATUS_VMEREG 0x3 +#define LVL2_REVID_VMEREG 0x5 /* Layers, Rows, Columns per Image Processing Card */ #define IPC_LAYS 3 @@ -194,6 +209,54 @@ These codes/flags are just used by the controlling C-software #define NUM_RBS 2 /* Number of RBs in current test 1 or 2 */ #define NUM_RB_FIFOS 2 /* Number of fifos per RB */ #define NUM_ROWS_RB_FIFO 8 /* Number of detector colmuns per RB fifo */ + +#define MAX_LINE_CHARS 50 + +void IPC_Conf_Display(LVme *lvme, unsigned long ul_dummy); +void IPC_Write_Display(LVme *lvme, int char_pos, char character); +void IPC_Reset_Display(LVme *lvme); +int IPC_Status_FPGA(LVme *lvme, int mode, int dev_chain); +void IPC_Set_OpMode(LVme *lvme, int i_choice); +void IPC_Set_Lvl1_Depth(LVme *lvme, int i_thres); +void IPC_Fifo_Reset(LVme *lvme, int i_mode); +void IPC_Write_SubID(LVme *lvme, unsigned long ul_daten); +void IPC_Set_Lvl2_MemBank(LVme *lvme, int i_l2ab); +void IPC_Write_LMAddr(LVme *lvme, unsigned short us_lmbaddr, + int i_mode); +void IPC_Set_BsyErr_Mask(LVme *lvme, int i_bsymsk, int i_errmsk, + int i_mode); +void IPC_Set_Lvl2_Mode(LVme *lvme, unsigned long us_daten); +void IPC_Set_PedMode(LVme *lvme, unsigned short us_pedes, + int i_mode); +void IPC_Clear_Lvl2(LVme *lvme, int i_mode); +void IPC_Set_Shower_Threshold(LVme *lvme, int i_device, + int i_shower_threshold, int i_mode); +void IPC_Get_Shower_Threshold(LVme *lvme, int i_device, + unsigned i_shower_threshold, + int i_mode); +void IPC_Set_Addon_Status(LVme *lvme, int i_device, + int i_addon_status, int i_mode); +void IPC_Get_Addon_Status(LVme *lvme, int i_device, + int i_addon_status, int i_mode); +void IPC_Set_Addon_SubID(LVme *lvme, int i_device, + int i_subevt_id, int i_mode); +void IPC_Get_Addon_SubID(LVme *lvme, int i_device, + int i_subevt_id, int i_mode); +void IPC_Conf_Lut1234(LVme *lvme, const char *filename, int i_calmode, + int i_sector, int i_rbhigh, int i_mode); +int IPC_Lut1234_Access(LVme *lvme, int i_layer, int i_row, + int i_column, int i_ucal_pad, int i_cal_pad, + int i_mode); +void IPC_Conf_Lut5(LVme *lvme, const char *filename, int ipc_sector, + int ipc_rbhigh, int i_mode); +void IPC_Conf_FPGA(LVme *lvme, const char *filename, int dev_chain, + int mode); +int IPC_Status_FPGA(LVme *lvme, int dev_chain, int mode); +void IPC_Init_FPGA(LVme *lvme, int mode, int dev_chain); +void IPC_Read_Status_Regs(LVme *lvme); +int IPC_GetPedestals(const char *pFileName, int iSector, int iRBHigh, + unsigned char pedestals[][][]); +void IPC_create_lut1234_daten(); #endif @@ -211,3 +274,5 @@ These codes/flags are just used by the controlling C-software + +