From: hadaq Date: Sat, 17 Mar 2012 16:45:43 +0000 (+0000) Subject: preparation for beam apr 2012 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d2458c4ab277df85f723a85ab048bb8255ed096d;p=ctsaddon.git preparation for beam apr 2012 --- diff --git a/cts_components.vhd b/cts_components.vhd index 4d2d2a0..0c6d380 100644 --- a/cts_components.vhd +++ b/cts_components.vhd @@ -56,10 +56,11 @@ package cts_components is FAST_MDCA_TIMING_IN : in std_logic_vector(3 downto 0); FAST_MDCB_TIMING_IN : in std_logic_vector(3 downto 0); MULTIPLEXER_IN : in std_logic_vector(7 downto 0); - LVDS_TIMING_OUT : out std_logic_vector(11 downto 0); + LVDS_TIMING_OUT : out std_logic_vector(12 downto 0); PECL_TIMING_OUT : out std_logic_vector(2 downto 0); START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0); - TRIG_CNTRL_IN : in std_logic_vector(7 downto 0) + TRIG_CNTRL_IN : in std_logic_vector(7 downto 0); + TRIG_STAT_OUT : out std_logic_vector(7 downto 0) ); end component; @@ -328,7 +329,8 @@ component cts_readout DEBUG_REGISTER_00 : out std_logic_vector(31 downto 0); DEBUG_REGISTER_01 : out std_logic_vector(31 downto 0); DEBUG_REGISTER_02 : out std_logic_vector(31 downto 0); - DATA_VERSION : in std_logic_vector(7 downto 0)); + DATA_VERSION : in std_logic_vector(7 downto 0); + BEAM_INHIBIT_IN : in std_logic); end component; component etrax_reg diff --git a/cts_fpga1.lpf b/cts_fpga1.lpf index f2c0ea8..ff3201d 100644 --- a/cts_fpga1.lpf +++ b/cts_fpga1.lpf @@ -29,6 +29,12 @@ FREQUENCY PORT CLK_200_IN 200.000000 MHz; #IOBUF PORT "ADDON_RESET" IO_TYPE=LVTTL33 PULLMODE=UP ; #IOBUF PORT "RESET_FPGA_1" IO_TYPE=LVTTL33 PULLMODE=UP ; +################################################################# +# DLL for edge clokcs +################################################################# + +LOCATE COMP "the_ddr2_buses/MAKE_DDR_CONNECTIONS_0_DLL_EDGE_INJECTION_COMPENSATE" SITE "DLL_URCC"; + ################################################################# # To TRB diff --git a/cts_fpga1.prj b/cts_fpga1.prj index 8ee580d..c6a49e9 100644 --- a/cts_fpga1.prj +++ b/cts_fpga1.prj @@ -79,8 +79,13 @@ add_file -vhdl -lib work "cts_simple_data_transport.vhd" #ddr2_busses components add_file -vhdl -lib work "dll_edge.vhd" add_file -vhdl -lib work "ddr2_16inputs.vhd" + add_file -vhdl -lib work "fifo12bit_synch.vhd" add_file -vhdl -lib work "fifo16bit_synch.vhd" + add_file -vhdl -lib work "fifo48bit_synch.vhd" + add_file -vhdl -lib work "fifo52bit_synch.vhd" + add_file -vhdl -lib work "fifo64bit_synch.vhd" add_file -vhdl -lib work "ddr2_12out_clkdiv.vhd" + add_file -vhdl -lib work "ddr2_13out_clkdiv.vhd" add_file -vhdl -lib work "ddr2_3out_clkdiv.vhd" #cts_trigger_logic.vhd add_file -vhdl -lib work "cts_one_clock.vhd" @@ -179,7 +184,7 @@ set_option -part_companion "" set_option -top_module "cts_fpga1" #map options -set_option -frequency 220 +set_option -frequency 200 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -retiming 0 diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd index d830b9b..a05ff4f 100644 --- a/cts_fpga1.vhd +++ b/cts_fpga1.vhd @@ -368,6 +368,7 @@ architecture cts_fpga1_arch of cts_fpga1 is signal multiplexer_to_ddr : std_logic_vector(7 downto 0); begin + ------------------------------------------------------------------------------- -- Emergency stop is RS1 ------------------------------------------------------------------------------- @@ -474,7 +475,10 @@ begin --------------------------------------------------------------------------- -- FFC <= (others => 'Z'); DIS1 <= (others => 'Z'); - DIS2 <= (others => 'Z'); +-- DIS2(0) <= clk_400;--<= (others => 'Z'); +-- DIS2(1) <= clk_200;--<= (others => 'Z'); +-- DIS2(2) <= dll_200_lock; + RS1 <= (others => 'Z'); RS2 <= (others => 'Z'); @@ -551,9 +555,12 @@ begin MULTIPLEXER_IN => multiplexer_to_ddr, LVDS_TIMING_OUT(9 downto 0) => LVDS_OUT(9 downto 0), LVDS_TIMING_OUT(11 downto 10) => LVDS_OUT(14 downto 13), + LVDS_TIMING_OUT(12 downto 12) => RICH_TIMING_OUT, PECL_TIMING_OUT => PECL_OUT, START_VETO_STRUCTURE_OUT => start_veto_beam_structure_buf, - TRIG_CNTRL_IN => rw_register_i(27)(7 downto 0)); + TRIG_CNTRL_IN => rw_register_i(26)(7 downto 0), + TRIG_STAT_OUT => r_register_i(2)(31 downto 24) + ); THE_CTS_TRIGGER_LOGIC: cts_trigger_logic generic map ( @@ -783,7 +790,8 @@ begin DEBUG_REGISTER_00 => r_register_i(4), DEBUG_REGISTER_01 => r_register_i(5), DEBUG_REGISTER_02 => r_register_i(6), - DATA_VERSION => data_version_readout); + DATA_VERSION => data_version_readout, + BEAM_INHIBIT_IN => beam_inhibit_buf); -- fee_trg_release <= lvl1_finished; -- lvl2_finished @@ -963,7 +971,7 @@ begin START_TIME_OFFSET_IN => rw_register_i(6),--(others => '0'), START_TIME_SAMPLE_IN => rw_register_i(8),--x"0000000A", START_BEAM_IN => LVDS_IN, - BEAM_INHIBIT_LENGTH_IN => rw_register_i(26), + BEAM_INHIBIT_LENGTH_IN => rw_register_i(25), BEAM_INHIBIT_OUT => beam_inhibit_buf,--open, BEAM_STRUCTURE_SIGNAL_IN => beam_structure_out_buf, BEAM_START_VETO_STRUCKTURE_IN(1 downto 0) => beam_structure_out_buf, diff --git a/cts_fpga1_compile.pl b/cts_fpga1_compile.pl index 9ff2a73..7c10151 100755 --- a/cts_fpga1_compile.pl +++ b/cts_fpga1_compile.pl @@ -112,7 +112,7 @@ execute($c); my $tpmap = $TOPNAME . "_map" ; -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; execute($c); diff --git a/cts_fpga1_test.vhd b/cts_fpga1_test.vhd index c487585..e02f8b9 100644 --- a/cts_fpga1_test.vhd +++ b/cts_fpga1_test.vhd @@ -265,8 +265,8 @@ begin port map ( clock => CLK_200_IN, en_clk => '1', - signal_in => hit_cntr(conv_integer (rw_register_i(i/4) ( (((i mod 4)+1)*8-1) downto (i mod 4)*8))), - -- signal_in => hit_cntr(4), +-- signal_in => hit_cntr(conv_integer (rw_register_i(i/4) ( (((i mod 4)+1)*8-1) downto (i mod 4)*8))), + signal_in => hit_cntr(4), pulse => start_pulses(i)); start_pulses_in_array(i)(0) <= start_pulses(i); @@ -307,8 +307,8 @@ begin port map ( clock => CLK_200_IN, en_clk => '1', - signal_in => hit_cntr(conv_integer(rw_register_i(25)(5 downto 0))), - -- signal_in => hit_cntr(8), + -- signal_in => hit_cntr(conv_integer(rw_register_i(25)(5 downto 0))), + signal_in => hit_cntr(8), pulse => beam_inhibit_pulse); BEAM_INHIBIT_SET_WIDTH: cts_fpga1_test_set_width diff --git a/cts_fpga2_reg_interface.vhd b/cts_fpga2_reg_interface.vhd index 31c9c79..6e75a30 100644 --- a/cts_fpga2_reg_interface.vhd +++ b/cts_fpga2_reg_interface.vhd @@ -168,7 +168,8 @@ begin -- unknown_addr <= '0'; -- elsif saved_mode = '0' and saved_address(15 downto 8) = x"A0" and saved_address(7 downto 0) > x"c0" and saved_address(7 downto 0) < 191 + RW_REGISTERS_NUMBER then -- unknown_addr <= '0'; - elsif (saved_address(15 downto 12) = x"A") or (saved_address(15 downto 12) = x"B") then +-- elsif (saved_address(15 downto 12) = x"A") or (saved_address(15 downto 12) = x"B") or (saved_address(15 downto 12) = x"C") or (saved_address(15 downto 8) = x"D") then + elsif saved_address < x"D3C9" and saved_address > x"9FFF" then --D3C8=0xA100+d26*500 unknown_addr <= '0'; else unknown_addr <= '1'; diff --git a/cts_readout.vhd b/cts_readout.vhd index f24ac2a..65c8236 100644 --- a/cts_readout.vhd +++ b/cts_readout.vhd @@ -34,7 +34,8 @@ entity cts_readout is DEBUG_REGISTER_01 : out std_logic_vector(31 downto 0); DEBUG_REGISTER_02 : out std_logic_vector(31 downto 0); --ctrl - DATA_VERSION : in std_logic_vector(7 downto 0) + DATA_VERSION : in std_logic_vector(7 downto 0); + BEAM_INHIBIT_IN : in std_logic ); end cts_readout; @@ -79,6 +80,7 @@ architecture cts_readout of cts_readout is type LVL2_FSM is (IDLE, WAIT_FOR_BUSY_END, READOUT_HEADER_MARKER_1, READOUT_HEADER_MARKER_2, READOUT_HEADER_MARKER_3, SEND_HEADERS_AND_DATA, READOUT_DATA_MARKER_1, READOUT_DATA_MARKER_2, READOUT_DATA_MARKER_3, SEND_DATA); signal LVL2_FSM_CURRENT, LVL2_FSM_NEXT : LVL2_FSM; + signal saved_lvl1_trigger_type : std_logic_vector(3 downto 0); --data buffer signal data_din, data_din_fsm, data_dout : std_logic_vector(33 downto 0); signal data_wr_en, data_wr_en_fsm, data_rd_en, data_rd_en_fsm, data_empty, data_full : std_logic; @@ -160,6 +162,19 @@ begin LVL1_BUSY_OUT <= lvl1_busy_i; SEND_DATA_TOKEN_OUT <= lvl1_data_token_i; + + SVAE_TRIGG_TYPE_PROC : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_lvl1_trigger_type <= (others => '0'); + elsif LVL1_TRBNET_TRIGGER_IN = '1' then + saved_lvl1_trigger_type <= LVL1_CODE_IN; + else + saved_lvl1_trigger_type <= saved_lvl1_trigger_type; + end if; + end if; + end process SVAE_TRIGG_TYPE_PROC; LVL1_FSM_CLOCK : process (CLK, RESET) begin @@ -229,7 +244,8 @@ begin when SAVE_HEADER_1 => lvl1_debug_fsm <= x"3"; hd_wr_en_fsm <= '1'; - hd_din_fsm <= "01" & x"0" & LVL1_CODE_IN & LVL1_TAG_IN(7 downto 0) & words_in_event; +-- hd_din_fsm <= "01" & "000" & BEAM_INHIBIT_IN & LVL1_CODE_IN & LVL1_TAG_IN(7 downto 0) & words_in_event; + hd_din_fsm <= "01" & "000" & BEAM_INHIBIT_IN & saved_lvl1_trigger_type & LVL1_TAG_IN(7 downto 0) & words_in_event; LVL1_FSM_NEXT <= SAVE_HEADER_2; when SAVE_HEADER_2 => diff --git a/cts_simulation_tb.mpf b/cts_simulation_tb.mpf index a1aab4a..79004bf 100644 --- a/cts_simulation_tb.mpf +++ b/cts_simulation_tb.mpf @@ -583,7 +583,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 10 ns +RunLength = 330 us ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -1547,285 +1547,295 @@ libhm = $MODEL_TECH/libhm.sl Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 139 +Project_Files_Count = 144 Project_File_0 = /home/marek/trbnet/basics/ram.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 59 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 58 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_1 = /home/marek/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1228404858 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 75 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1228404858 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 74 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_2 = /home/marek/trbv2/up_down_counter.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249045055 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 117 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249045055 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 116 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_3 = /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_4 = /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 40 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 39 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_5 = /home/marek/trbnet/basics/ram_16x8_dp.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 60 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 59 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_6 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277134650 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 81 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277134650 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 80 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_7 = /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_8 = /home/marek/trbnet/trb_net_priority_arbiter.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 95 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 94 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_9 = /home/marek/trbnet/special/spi_master.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 113 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 112 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_10 = /home/marek/ctsaddon/simulation/ram_register.vhd Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_11 = /home/marek/trbnet/lattice/ecp2m/trb_net_clock_generator.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 74 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 73 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_12 = /home/marek/trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249570868 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 68 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_13 = /home/marek/trbnet/trb_net_sbuf6.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 98 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_14 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325773805 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_15 = /home/marek/trbnet/special/handler_trigger_and_data.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296638933 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 111 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_16 = /home/marek/trbnet/trb_net16_term.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1237891031 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 55 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_17 = /home/marek/trbnet/trb_net_dummy_fifo.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 93 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_18 = /home/marek/trbnet/trb_net_sbuf.vhd -Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 97 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_19 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 89 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_20 = /home/marek/trbnet/lattice/ecp2m/dll_in100_out100.vhd -Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292267 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 67 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_21 = /home/marek/ctsaddon/simulation/cts_fpga1_to_fpga2.vhd -Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 33 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_22 = /home/marek/trbnet/trb_net16_endpoint_hades_full_handler.vhd -Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 101 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_23 = /home/marek/ctsaddon/simulation/pll_in200_out40.vhd -Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_24 = /home/marek/ctsaddon/simulation/ddr2_16inputs.vhd -Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_25 = /home/marek/ctsaddon/simulation/cts_width_rom.vhd -Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_26 = /home/marek/trbnet/special/handler_lvl1.vhd -Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014417 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 110 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_27 = /home/marek/trbnet/trb_net16_sbuf.vhd -Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295625509 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 108 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_28 = /home/marek/trbv2/f_divider.vhd -Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1259846036 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 116 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_29 = /home/marek/ctsaddon/simulation/scm_fifo_16bit_to_32bit.vhd -Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_30 = /home/marek/trbnet/trb_net16_obuf_nodata.vhd -Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248956644 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 54 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_31 = /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd -Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 37 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_32 = /home/marek/ctsaddon/simulation/cts_fpga2.vhd -Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 124 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_33 = /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd -Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_34 = /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd -Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321880898 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 132 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_35 = /home/marek/trbnet/special/spi_databus_memory.vhd -Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1268245488 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 112 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_36 = /home/marek/trbnet/special/spi_slim.vhd -Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875807 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 130 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_37 = /home/marek/trbnet/trb_net16_term_buf.vhd -Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_38 = /home/marek/trbnet/basics/pulse_stretch.vhd -Project_File_P_38 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277977616 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 128 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_39 = /home/marek/trbnet/trb_net16_iobuf.vhd -Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 104 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_40 = /home/marek/trbnet/trb_net16_regIO.vhd -Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295344067 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 106 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_41 = /home/marek/trbnet/trb_net16_ibuf.vhd -Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 102 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_42 = /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd -Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 118 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_43 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd -Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 79 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_44 = /home/marek/ctsaddon/simulation/cts_beam_structure.vhd -Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325766507 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 136 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_45 = /home/marek/trbnet/trb_net16_ipudata.vhd -Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 53 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_46 = /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd -Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 38 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_47 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd -Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 134 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_48 = /home/marek/trbnet/trb_net_CRC.vhd -Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 92 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_49 = /home/marek/trbnet/trb_net16_io_multiplexer.vhd -Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 103 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_50 = /home/marek/ctsaddon/simulation/cts_delay_large.vhd -Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_51 = /home/marek/ctsaddon/simulation/cts_polarity_check.vhd -Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 39 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_52 = /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd -Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_53 = /home/marek/ctsaddon/simulation/delay_fifo.vhd -Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_54 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd -Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 72 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_55 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd -Project_File_P_55 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_56 = /home/marek/trbnet/trb_net16_api_base.vhd -Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 99 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_57 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd -Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 78 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_58 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd -Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 41 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_59 = /home/marek/ctsaddon/simulation/cts_readout.vhd -Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_60 = /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd -Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875836 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 131 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_61 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd -Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 76 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_62 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd -Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_63 = /home/marek/trbnet/trb_net_onewire_listener.vhd -Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 127 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_64 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd -Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_65 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd -Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 123 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_66 = /home/marek/ctsaddon/simulation/cts_components.vhd -Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_67 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd -Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_68 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd -Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 42 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_69 = /home/marek/trbnet/trb_net_pattern_gen.vhd -Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 94 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_70 = /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd -Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_71 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd -Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_72 = /home/marek/ctsaddon/simulation/fifo_1bit_to_32bit.vhd -Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 43 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_73 = /home/marek/trbnet/special/trb_net_reset_handler.vhd -Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 66 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_74 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd -Project_File_P_74 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 84 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_75 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd -Project_File_P_75 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 44 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_76 = /home/marek/trbnet/trb_net_onewire.vhd -Project_File_P_76 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872769 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 126 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_77 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd -Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 71 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_78 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd -Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_79 = /home/marek/trbnet/basics/ram_dp.vhd -Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 62 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_80 = /home/marek/trbv2/etrax_write_read_tb.vhd -Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321461742 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 119 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_81 = /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd -Project_File_P_81 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_82 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd -Project_File_P_82 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 45 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_83 = /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd -Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_84 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd -Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 107 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_85 = /home/marek/ctsaddon/cts_fpga1_test.vhd -Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325688824 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_86 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd -Project_File_P_86 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760377 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 85 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_87 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd -Project_File_P_87 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_88 = /home/marek/trbnet/trb_net_sbuf5.vhd -Project_File_P_88 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 49 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_89 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd -Project_File_P_89 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 69 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_90 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd -Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 122 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_91 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd -Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_92 = /home/marek/ctsaddon/simulation/version.vhd -Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_93 = /home/marek/trbnet/special/handler_ipu.vhd -Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304089906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 109 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_94 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd -Project_File_P_94 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 88 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_95 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd -Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267800223 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 115 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_96 = /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd -Project_File_P_96 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 46 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_97 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd -Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278661530 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 70 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_98 = /home/marek/ctsaddon/simulation/cts_downscale.vhd -Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_99 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd -Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_100 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd -Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_101 = /home/marek/trbnet/trb_net_priority_encoder.vhd -Project_File_P_101 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 96 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_102 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd -Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 87 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_103 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd -Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_104 = /home/marek/trbnet/trb_net16_obuf.vhd -Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302529528 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 105 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_105 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd -Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_106 = /home/marek/trbnet/trb_net16_term_ibuf.vhd -Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_107 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd -Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689502 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 138 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_108 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd -Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 82 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_109 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd -Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 77 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_110 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd -Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 34 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_111 = /home/marek/ctsaddon/simulation/etrax_reg_mem.vhd -Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_112 = /home/marek/trbnet/basics/ram_16x16_dp.vhd -Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291756328 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 61 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_113 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd -Project_File_P_113 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 135 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_114 = /home/marek/ctsaddon/simulation/dll_edge.vhd -Project_File_P_114 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_115 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd -Project_File_P_115 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 90 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_116 = /home/marek/ctsaddon/simulation/multiplicity.vhd -Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_117 = /home/marek/trbnet/basics/signal_sync.vhd -Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 65 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_118 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd -Project_File_P_118 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_119 = /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd -Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_120 = /home/marek/trbnet/basics/ram_dp_rw.vhd -Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 63 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_121 = /home/marek/ctsaddon/simulation/trb_net_components.vhd -Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 91 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_122 = /home/marek/trbnet/trb_net16_trigger.vhd -Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 58 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_123 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd -Project_File_P_123 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 73 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_124 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd -Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600671 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 121 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_125 = /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd -Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 120 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_126 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd -Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_127 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd -Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 100 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_128 = /home/marek/ctsaddon/simulation/cts_delay.vhd -Project_File_P_128 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_129 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd -Project_File_P_129 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 80 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_130 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd -Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1271868444 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 114 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_131 = /home/marek/trbnet/special/handler_data.vhd -Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304328663 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 129 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_132 = /home/marek/trbnet/trb_net_std.vhd -Project_File_P_132 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 50 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_133 = /home/marek/trbnet/basics/rom_16x8.vhd -Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 64 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_134 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd -Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 86 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_135 = /home/marek/ctsaddon/simulation/cts_set_width.vhd -Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 133 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_136 = /home/marek/trbnet/trb_net16_addresses.vhd -Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_137 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd -Project_File_P_137 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 47 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_138 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd -Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 83 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249570868 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 67 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_13 = /home/marek/ctsaddon/fifo12bit_synch.vhd +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329309772 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 141 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_14 = /home/marek/trbnet/trb_net_sbuf6.vhd +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 97 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_15 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331894152 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_16 = /home/marek/ctsaddon/simulation/delay.vhd +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331907215 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 138 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_17 = /home/marek/trbnet/special/handler_trigger_and_data.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296638933 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 110 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_18 = /home/marek/trbnet/trb_net16_term.vhd +Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1237891031 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 54 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_19 = /home/marek/trbnet/trb_net_dummy_fifo.vhd +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 92 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_20 = /home/marek/trbnet/trb_net_sbuf.vhd +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 96 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_21 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd +Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 88 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_22 = /home/marek/trbnet/lattice/ecp2m/dll_in100_out100.vhd +Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292267 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 66 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_23 = /home/marek/ctsaddon/simulation/cts_fpga1_to_fpga2.vhd +Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_24 = /home/marek/ctsaddon/fifo52bit_synch.vhd +Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503624 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 142 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_25 = /home/marek/trbnet/trb_net16_endpoint_hades_full_handler.vhd +Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 100 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_26 = /home/marek/ctsaddon/simulation/pll_in200_out40.vhd +Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_27 = /home/marek/ctsaddon/simulation/ddr2_16inputs.vhd +Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_28 = /home/marek/ctsaddon/simulation/cts_width_rom.vhd +Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_29 = /home/marek/trbnet/special/handler_lvl1.vhd +Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014417 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 109 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_30 = /home/marek/trbnet/trb_net16_sbuf.vhd +Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295625509 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 107 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_31 = /home/marek/trbv2/f_divider.vhd +Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1259846036 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 115 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_32 = /home/marek/ctsaddon/simulation/scm_fifo_16bit_to_32bit.vhd +Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_33 = /home/marek/trbnet/trb_net16_obuf_nodata.vhd +Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248956644 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 53 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_34 = /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd +Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_35 = /home/marek/ctsaddon/simulation/cts_fpga2.vhd +Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 123 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_36 = /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd +Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_37 = /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd +Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321880898 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 131 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_38 = /home/marek/trbnet/special/spi_databus_memory.vhd +Project_File_P_38 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1268245488 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 111 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_39 = /home/marek/trbnet/special/spi_slim.vhd +Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875807 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 129 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_40 = /home/marek/trbnet/trb_net16_term_buf.vhd +Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 55 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_41 = /home/marek/trbnet/basics/pulse_stretch.vhd +Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277977616 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 127 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_42 = /home/marek/trbnet/trb_net16_iobuf.vhd +Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 103 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_43 = /home/marek/trbnet/trb_net16_regIO.vhd +Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295344067 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 105 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_44 = /home/marek/trbnet/trb_net16_ibuf.vhd +Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 101 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_45 = /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd +Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 117 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_46 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd +Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 78 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_47 = /home/marek/ctsaddon/simulation/cts_beam_structure.vhd +Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325766507 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 134 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_48 = /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd +Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 37 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_49 = /home/marek/trbnet/trb_net16_ipudata.vhd +Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_50 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd +Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 133 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_51 = /home/marek/trbnet/trb_net_CRC.vhd +Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 91 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_52 = /home/marek/trbnet/trb_net16_io_multiplexer.vhd +Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 102 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_53 = /home/marek/ctsaddon/simulation/cts_delay_large.vhd +Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_54 = /home/marek/ctsaddon/simulation/cts_polarity_check.vhd +Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 38 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_55 = /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd +Project_File_P_55 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_56 = /home/marek/ctsaddon/simulation/delay_fifo.vhd +Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_57 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd +Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 71 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_58 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd +Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_59 = /home/marek/trbnet/trb_net16_api_base.vhd +Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 98 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_60 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd +Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 77 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_61 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd +Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 40 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_62 = /home/marek/ctsaddon/simulation/cts_readout.vhd +Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331894152 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_63 = /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd +Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875836 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 130 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_64 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd +Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 75 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_65 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd +Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_66 = /home/marek/trbnet/trb_net_onewire_listener.vhd +Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 126 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_67 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd +Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_68 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd +Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 122 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_69 = /home/marek/ctsaddon/simulation/cts_components.vhd +Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_70 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd +Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_71 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd +Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 41 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_72 = /home/marek/trbnet/trb_net_pattern_gen.vhd +Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 93 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_73 = /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd +Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_74 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd +Project_File_P_74 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 34 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_75 = /home/marek/ctsaddon/simulation/fifo_1bit_to_32bit.vhd +Project_File_P_75 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 42 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_76 = /home/marek/trbnet/special/trb_net_reset_handler.vhd +Project_File_P_76 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 65 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_77 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd +Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 83 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_78 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd +Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 43 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_79 = /home/marek/trbnet/trb_net_onewire.vhd +Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872769 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_80 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd +Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 70 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_81 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd +Project_File_P_81 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_82 = /home/marek/trbnet/basics/ram_dp.vhd +Project_File_P_82 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 61 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_83 = /home/marek/trbv2/etrax_write_read_tb.vhd +Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321461742 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 118 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_84 = /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd +Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331894152 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_85 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd +Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 44 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_86 = /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd +Project_File_P_86 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_87 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd +Project_File_P_87 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 106 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_88 = /home/marek/ctsaddon/cts_fpga1_test.vhd +Project_File_P_88 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672862 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 136 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_89 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd +Project_File_P_89 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760377 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 84 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_90 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd +Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_91 = /home/marek/trbnet/trb_net_sbuf5.vhd +Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_92 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd +Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 68 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_93 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd +Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 121 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_94 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd +Project_File_P_94 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_95 = /home/marek/ctsaddon/simulation/version.vhd +Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331921178 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_96 = /home/marek/trbnet/special/handler_ipu.vhd +Project_File_P_96 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304089906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 108 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_97 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd +Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 87 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_98 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd +Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267800223 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 114 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_99 = /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd +Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 45 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_100 = /home/marek/ctsaddon/ddr2_13out_clkdiv.vhd +Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503926 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 140 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_101 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd +Project_File_P_101 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278661530 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 69 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_102 = /home/marek/ctsaddon/simulation/cts_downscale.vhd +Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_103 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd +Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 47 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_104 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd +Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_105 = /home/marek/trbnet/trb_net_priority_encoder.vhd +Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 95 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_106 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd +Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 86 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_107 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd +Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 124 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_108 = /home/marek/trbnet/trb_net16_obuf.vhd +Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302529528 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 104 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_109 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd +Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_110 = /home/marek/trbnet/trb_net16_term_ibuf.vhd +Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_111 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd +Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689502 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 135 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_112 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd +Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 81 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_113 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd +Project_File_P_113 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 76 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_114 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd +Project_File_P_114 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 33 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_115 = /home/marek/ctsaddon/simulation/etrax_reg_mem.vhd +Project_File_P_115 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_116 = /home/marek/trbnet/basics/ram_16x16_dp.vhd +Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291756328 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 60 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_117 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd +Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_118 = /home/marek/ctsaddon/simulation/dll_edge.vhd +Project_File_P_118 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_119 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd +Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 89 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_120 = /home/marek/ctsaddon/simulation/multiplicity.vhd +Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331919062 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 143 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_121 = /home/marek/trbnet/basics/signal_sync.vhd +Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 64 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_122 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd +Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923063 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_123 = /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd +Project_File_P_123 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_124 = /home/marek/trbnet/basics/ram_dp_rw.vhd +Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 62 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_125 = /home/marek/ctsaddon/simulation/trb_net_components.vhd +Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 90 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_126 = /home/marek/trbnet/trb_net16_trigger.vhd +Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_127 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd +Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 72 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_128 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd +Project_File_P_128 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600671 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 120 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_129 = /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd +Project_File_P_129 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 119 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_130 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd +Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_131 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd +Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 99 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_132 = /home/marek/ctsaddon/simulation/cts_delay.vhd +Project_File_P_132 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_133 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd +Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 79 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_134 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd +Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1271868444 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 113 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_135 = /home/marek/trbnet/special/handler_data.vhd +Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304328663 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 128 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_136 = /home/marek/trbnet/trb_net_std.vhd +Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 49 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_137 = /home/marek/trbnet/basics/rom_16x8.vhd +Project_File_P_137 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 63 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_138 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd +Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 85 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_139 = /home/marek/ctsaddon/simulation/cts_set_width.vhd +Project_File_P_139 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 132 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_140 = /home/marek/trbnet/trb_net16_addresses.vhd +Project_File_P_140 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 50 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_141 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd +Project_File_P_141 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 46 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_142 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd +Project_File_P_142 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 82 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_143 = /home/marek/ctsaddon/cts_polarity_check.vhd +Project_File_P_143 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 139 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/cts_trigger_logic.vhd b/cts_trigger_logic.vhd index e22e023..e7494b8 100755 --- a/cts_trigger_logic.vhd +++ b/cts_trigger_logic.vhd @@ -167,8 +167,7 @@ architecture cts_trigger_logic of cts_trigger_logic is LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0); LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0); DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_0 : out std_logic_vector(31 downto 0); - DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 : out std_logic_vector(31 downto 0); - DDR_LVL1_TRIGGER_BUFFER_CTRL_IN_0 : in std_logic_vector(11 downto 0) + DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 : out std_logic_vector(31 downto 0) ); end component; @@ -259,7 +258,8 @@ architecture cts_trigger_logic of cts_trigger_logic is RESET : in std_logic; CLK : in std_logic; SIGNAL_IN : in std_logic_vector(5 downto 0); - SIGNAL_OUT : out std_logic_vector(8 downto 0) + SIGNAL_OUT : out std_logic_vector(8 downto 0); + SAMPLE_DELAY_IN : in std_logic_vector(3 downto 0) ); end component; @@ -470,6 +470,7 @@ architecture cts_trigger_logic of cts_trigger_logic is signal tof_multiplicity : std_logic_vector(7 downto 0); signal tof_multiplicity_all : std_logic; signal multiplicity_out : std_logic_vector(8 downto 0); + signal mult_array_signal_delay, mult_array_signal_delay_conv : std_logic_vector(7 downto 0); signal tof_mdc_trigger : std_logic; signal multiplexer_address_a, multiplexer_address_b,multiplexer_address_c, multiplexer_address_d : integer range 0 to 128 :=0; signal multiplexer_sync_array_a,multiplexer_sync_array_b,multiplexer_sync_array_c,multiplexer_sync_array_d : std_logic_vector(7 downto 0); @@ -574,6 +575,7 @@ architecture cts_trigger_logic of cts_trigger_logic is signal trigg_last_time, trigg_last_time_saved : std_logic_vector(31 downto 0); signal trigg_anticoinc_time, trigg_anticoinc_time_saved : std_logic_vector(31 downto 0); signal trigg_anticoinc : std_logic; + signal reset_special_scalers : std_logic; begin -- TRIGGER_IN @@ -972,7 +974,8 @@ begin RESET => RESET, CLK => CLK, SIGNAL_IN => multiplicity_in_array, --TOF or RPC - SIGNAL_OUT => multiplicity_out_for_delay + SIGNAL_OUT => multiplicity_out_for_delay, + SAMPLE_DELAY_IN => TRIGGER_LOGIC_CTRL_IN_1(3 downto 0) ); multiplicity_out <= multiplicity_out_for_delay; @@ -981,38 +984,60 @@ begin if rising_edge(CLK) then tof_rpc_or <= pti_set_width_out_array(16) or pti_set_width_out_array(17) or pti_set_width_out_array(18) or pti_set_width_out_array(19) or pti_set_width_out_array(20) or pti_set_width_out_array(21) or pti_set_width_out_array(22) or pti_set_width_out_array(23) or pti_set_width_out_array(24) or pti_set_width_out_array(25) or pti_set_width_out_array(26) or pti_set_width_out_array(27); - tof_rpc_sync <= tof_rpc_or; + -- tof_rpc_sync <= tof_rpc_or; end if; end process TOF_RPC_MAKE_OR_ALL; - MAKE_TOF_RPC_FASTEST_SIGNAL : process (CLK, RESET) +-- MAKE_TOF_RPC_FASTEST_SIGNAL : process (CLK, RESET) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' then +-- tof_rpc_fast <= x"0"; +-- elsif tof_rpc_sync = x"0" and tof_rpc_or /= x"0" then +-- tof_rpc_fast <= tof_rpc_or; +-- else +-- tof_rpc_fast <= x"0"; +-- end if; +-- end if; +-- end process MAKE_TOF_RPC_FASTEST_SIGNAL; + + MULT_CTS_FASTEST_SIGNAL: cts_one_clock + generic map ( + VECTOR_WIDTH => VECTOR_WIDTH + ) + port map ( + RESET => RESET, + CLK => CLK, + ENABLE_IN => '1', + ONE_CLOCK_VECTOR_IN => tof_rpc_or, + ONE_CLOCK_VECTOR_OUT => multiplicity_out_array); + mult_array_signal_delay <= x"0" & TRIGGER_LOGIC_CTRL_IN_1(3 downto 0); + + SET_DELAY_FOR_MULT_ARRAY : process (CLK, RESET) begin if rising_edge(CLK) then if RESET = '1' then - tof_rpc_fast <= x"0"; - elsif tof_rpc_sync = x"0" and tof_rpc_or /= x"0" then - tof_rpc_fast <= tof_rpc_or; + mult_array_signal_delay_conv <= x"01"; else - tof_rpc_fast <= tof_rpc_fast; + mult_array_signal_delay_conv <= mult_array_signal_delay + 5; end if; end if; - end process MAKE_TOF_RPC_FASTEST_SIGNAL; + end process SET_DELAY_FOR_MULT_ARRAY; --- MULT_CTS_FASTEST_SIGNAL: cts_one_clock --- generic map ( --- VECTOR_WIDTH => VECTOR_WIDTH --- ) --- port map ( --- RESET => RESET, --- CLK => CLK, --- ENABLE_IN => '1', --- ONE_CLOCK_VECTOR_IN => tof_rpc_fast, --- ONE_CLOCK_VECTOR_OUT => multiplicity_out_array); - --- cts_align_signals_1: cts_align_signals + MULT_ARRAY_DELAY: cts_delay_large + generic map ( + VECTOR_WIDTH => 4) + port map ( + RESET => RESET, + CLK => CLK, + DELAY_IN => mult_array_signal_delay_conv, + DELAY_VECTOR_IN => multiplicity_out_array, + DELAY_VECTOR_OUT => multiplicity_out_array_delayed); + +-- CTS_ALIGN_TOFRPCARRAY_MULTDECISION: cts_align_signals -- generic map ( --- DELAY => 3, +-- DELAY => 4, -- VECTOR_WIDTH => VECTOR_WIDTH) -- port map ( -- CLK => CLK, @@ -1026,7 +1051,7 @@ begin if RESET = '1' then individual_multiplicity_out_array(i) <= (others => '0'); elsif multiplicity_out(i) = '1' then - individual_multiplicity_out_array(i) <= tof_rpc_fast;--multiplicity_out_array; + individual_multiplicity_out_array(i) <= multiplicity_out_array_delayed; --tof_rpc_fast;--multiplicity_out_array; else individual_multiplicity_out_array(i) <= (others => '0'); end if; @@ -1427,7 +1452,7 @@ begin FAST_UPDATE_UP_SIGNAL_FOR_OUT_SCALERS : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if RESET = '1' or TRIGGER_LOGIC_CTRL_IN_2(27 downto 0) > 0 then scalers_out_up(i) <= '0'; else scalers_out_up(i) <= ( pti_and_gts_out_saved(i) and scalers_out_save_pulse and (not(internal_trigger)) ); @@ -1559,9 +1584,8 @@ begin LVL2_TRIGGER_TAG_OUT => LVL2_TRIGGER_TAG_OUT, LVL2_RND_NUMBER_OUT => LVL2_RND_NUMBER_OUT, DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_0 => TRIGGER_LOGIC_DEBUG_OUT_0, - DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 => TRIGGER_LOGIC_DEBUG_OUT_1, - DDR_LVL1_TRIGGER_BUFFER_CTRL_IN_0 => TRIGGER_LOGIC_CTRL_IN_1(11 downto 0) - ); + DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 => TRIGGER_LOGIC_DEBUG_OUT_1 + ); TRIGGER_LOGIC_DEBUG_OUT_2(3 downto 0) <= lvl1_trigger_debug; TRIGGER_LOGIC_DEBUG_OUT_2(4) <= beam_inhibit_in_i; @@ -1574,6 +1598,16 @@ begin -- special scalers ------------------------------------------------------------------------------ + RESET_SP_SCALERS : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or lvl1_trigger_pulse = '1' then + reset_special_scalers <= '1'; + else + reset_special_scalers <= '0'; + end if; + end if; + end process RESET_SP_SCALERS; --realtive time to the start of the beam COUNT_SAVE_RELATIVE_TIME : process (CLK, RESET) @@ -1592,7 +1626,7 @@ begin if rising_edge(CLK) then if RESET = '1' then trigg_relative_time_saved <= (others => '0'); - elsif lvl1_trigger_out_fast = '1' then + elsif lvl1_trigger_pulse = '1' then trigg_relative_time_saved <= trigg_relative_time; else trigg_relative_time_saved <= trigg_relative_time_saved; @@ -1602,11 +1636,12 @@ begin scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+1) <= trigg_relative_time_saved; --time since the last trigger - + + COUNT_SAVE_LAST_TIME : process (CLK, RESET) begin if rising_edge(CLK) then - if RESET = '1' or lvl1_trigger_out_fast = '1' then + if reset_special_scalers = '1' then trigg_last_time <= (others => '0'); else trigg_last_time <= trigg_last_time + 1; @@ -1619,7 +1654,7 @@ begin if rising_edge(CLK) then if RESET = '1' then trigg_last_time_saved <= (others => '0'); - elsif phys_trigger_out = '1' or cal_trigger_out = '1' then + elsif lvl1_trigger_pulse = '1' then trigg_last_time_saved <= trigg_last_time; else trigg_last_time_saved <= trigg_last_time_saved; @@ -1628,7 +1663,7 @@ begin end process SAVE_LAST_TIME; scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+2) <= trigg_last_time_saved; ---time since the anticoincidence +--time since the last anticoincidence signal ANTICOINC_SIGNAL : process (CLK, RESET) begin if rising_edge(CLK) then @@ -1645,7 +1680,7 @@ begin COUNT_SAVE_ANTICOINC_TIME : process (CLK, RESET) begin if rising_edge(CLK) then - if RESET = '1' or trigg_anticoinc = '1' then + if RESET = '1' or trigg_anticoinc = '1' or reset_special_scalers = '1' then trigg_anticoinc_time <= (others => '0'); else trigg_anticoinc_time <= trigg_anticoinc_time + 1; @@ -1658,7 +1693,7 @@ begin if rising_edge(CLK) then if RESET = '1' then trigg_anticoinc_time_saved <= (others => '0'); - elsif start_veto_anticoincidence_array > 0 then + elsif lvl1_trigger_pulse = '1' then trigg_anticoinc_time_saved <= trigg_anticoinc_time; else trigg_anticoinc_time_saved <= trigg_anticoinc_time_saved; @@ -1708,7 +1743,7 @@ begin SET_ALL_DDR_BITS: for i in 0 to 3 generate - multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+3)(i) <=lvl1_trigger_out_fast; + multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+3)(i) <=lvl1_trigger_out_fast; multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+4)(i) <= out_inhibit; multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+5)(i) <= phys_trigger_out_local_busy; multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+6)(i) <= beam_inhibit_in_i; diff --git a/ddr2_busses.vhd b/ddr2_busses.vhd index a416803..3b4d4fc 100644 --- a/ddr2_busses.vhd +++ b/ddr2_busses.vhd @@ -3,8 +3,8 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library work; -use work.all; +--library work; +--use work.all; use ieee.std_logic_arith.all; entity ddr2_busses is @@ -21,10 +21,11 @@ entity ddr2_busses is FAST_MDCA_TIMING_IN : in std_logic_vector(3 downto 0); FAST_MDCB_TIMING_IN : in std_logic_vector(3 downto 0); MULTIPLEXER_IN : in std_logic_vector(7 downto 0); - LVDS_TIMING_OUT : out std_logic_vector(11 downto 0); + LVDS_TIMING_OUT : out std_logic_vector(12 downto 0); PECL_TIMING_OUT : out std_logic_vector(2 downto 0); START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0); - TRIG_CNTRL_IN : in std_logic_vector(7 downto 0) + TRIG_CNTRL_IN : in std_logic_vector(7 downto 0); + TRIG_STAT_OUT : out std_logic_vector(7 downto 0) ); end ddr2_busses; @@ -85,6 +86,39 @@ architecture ddr2_busses of ddr2_busses is AlmostFull : out std_logic); end component; + component fifo12bit_synch + port ( + Data : in std_logic_vector(11 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(11 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic); + end component; + + component fifo52bit_synch + port ( + Data : in std_logic_vector(51 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(51 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic); + end component; + + component dll_edge port ( clk : in std_logic; @@ -94,14 +128,14 @@ architecture ddr2_busses of ddr2_busses is lock : out std_logic); end component; - component ddr2_12out_clkdiv + component ddr2_13out_clkdiv port ( - Data : in std_logic_vector(47 downto 0); + Data : in std_logic_vector(51 downto 0); EClk : in std_logic; Rst : in std_logic; SClk : out std_logic; - Q : out std_logic_vector(11 downto 0); - Update : out std_logic_vector(11 downto 0)); + Q : out std_logic_vector(12 downto 0); + Update : out std_logic_vector(12 downto 0)); end component; component ddr2_3out_clkdiv @@ -127,21 +161,25 @@ architecture ddr2_busses of ddr2_busses is end component; attribute DCSMODE:string; attribute DCSMODE of DCS_A: label is "POS" ; --no_sim-- - attribute DCSMODE of DCS_B: label is "POS" ; --no_sim-- +-- attribute DCSMODE of DCS_B: label is "POS" ; --no_sim-- --ddr in signal ddr_outvector : std_logic_vector(64*4-1 downto 0); + signal ddr_outvector_corr : std_logic_vector(64*4-1 downto 0); + signal ddr_div_clk : std_logic_vector(15 downto 0); signal ddr_div_clk_op : std_logic_vector(15 downto 0); signal ddr_edge_clk : std_logic_vector(15 downto 0); signal output_from_fifo_sunch_a : std_logic_vector(64*4-1 downto 0); + signal dll_lock : std_logic_vector(7 downto 0); --ddr out - signal ddr_in_vector_a : std_logic_vector(16*3-1 downto 0); - signal ddr_out_vector_a : std_logic_vector(16*3-1 downto 0); - - - signal ddr_in_vector_b : std_logic_vector(15 downto 0); - signal ddr_out_vector_b : std_logic_vector(15 downto 0); + signal ddr_in_vector_a : std_logic_vector(52-1 downto 0); + signal ddr_in_vector_a_corr : std_logic_vector(52-1 downto 0); + signal ddr_out_vector_a : std_logic_vector(52-1 downto 0); + signal ddr_out_vector_a_corr : std_logic_vector(52-1 downto 0); + + signal ddr_in_vector_b : std_logic_vector(11 downto 0); + signal ddr_out_vector_b : std_logic_vector(11 downto 0); signal ddr_div_out_clk : std_logic_vector(1 downto 0); signal fast_trigger_tmp : std_logic_vector(47 downto 0); @@ -163,7 +201,8 @@ begin ----------------------------------------------------------------------------- -- in DDR ----------------------------------------------------------------------------- - + TRIG_STAT_OUT <= dll_lock; + MAKE_DDR_CONNECTIONS: for i in 0 to 3 generate DLL_EDGE_INJECTION_COMPENSATE: dll_edge port map ( @@ -171,7 +210,7 @@ begin aluhold => '0', clkop => ddr_div_clk_op(i), clkos => ddr_edge_clk(i), - lock => open); + lock => dll_lock(i)); DDR2_16INPUTS_INST: ddr2_16inputs port map ( @@ -183,23 +222,32 @@ begin Update => open); end generate MAKE_DDR_CONNECTIONS; + + DDR_SYNCH: for i in 0 to 15 generate FIFO16BIT_SYNCH_A: fifo16bit_synch port map ( - Data => ddr_outvector((16*(i+1))-1 downto i*16), + Data => ddr_outvector( (16*(i+1))-1 downto i*16 ), WrClock => ddr_div_clk(i/4), RdClock => CLK, - WrEn => '1', + WrEn => dll_lock(i/4), RdEn => '1', Reset => RESET, RPReset => RESET, - Q => output_from_fifo_sunch_a((16*(i+1))-1 downto i*16), + Q => ddr_outvector_corr((16*(i+1))-1 downto i*16),--output_from_fifo_sunch_a((16*(i+1))-1 downto i*16), Empty => open, Full => open, AlmostEmpty => open, AlmostFull => open); - end generate DDR_SYNCH; + + ALL_CON_CORR: for y in 0 to 3 generate + MAKE_CORR_ORDER: for i in 0 to 15 generate + output_from_fifo_sunch_a((y*64)+(i+1)*4-1 downto (y*64)+(i*4)) <= ddr_outvector_corr(i+48+(y*64)) & ddr_outvector_corr(i+32+(y*64)) & ddr_outvector_corr(i+16+(y*64)) & ddr_outvector_corr(i+(y*64)); + end generate MAKE_CORR_ORDER; + end generate ALL_CON_CORR; + + --TRIG_OUT arrangment -- 7:0 START -- 15:8 Veto @@ -215,37 +263,43 @@ begin if rising_edge(CLK) then case TRIG_CNTRL_IN(7 downto 6) is when b"00" => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); when b"01" => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(12*4-1 downto 4*4); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(12*4-1 downto 4*4); when b"10" => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(16*4-1 downto 8*4); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(16*4-1 downto 8*4); when others => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); end case; end if; end process SELECT_START_SIGNALS_FOR_TRIGGER; --first 32 inputs are used for the START - first 16 for trggering and --histograming next 16 for histograming only - - TRIG_OUT(16*4-1 downto 8*4) <= output_from_fifo_sunch_a(40*4-1 downto 32*4); --veto - TRIG_OUT(22*4-1 downto 16*4) <= output_from_fifo_sunch_a(54*4-1 downto 48*4); --TOF - TRIG_OUT(26*4-1 downto 22*4) <= output_from_fifo_sunch_a(60*4-1 downto 56*4); --RPC - TRIG_OUT(28*4-1 downto 26*4) <= output_from_fifo_sunch_a(63*4-1 downto 61*4); --RPC - TRIG_OUT(36*4-1 downto 28*4) <= output_from_fifo_sunch_a(48*4-1 downto 40*4); --PT + + MAKE_POLAR_AND_SYNCH : process (CLK, RESET) + begin + if rising_edge(CLK) then + TRIG_OUT(36*4-1 downto 28*4) <= output_from_fifo_sunch_a(40*4-1 downto 32*4); --PT + TRIG_OUT(22*4-1 downto 16*4) <= output_from_fifo_sunch_a(54*4-1 downto 48*4); --TOF + TRIG_OUT(26*4-1 downto 22*4) <= output_from_fifo_sunch_a(60*4-1 downto 56*4); --RPC + TRIG_OUT(28*4-1 downto 26*4) <= output_from_fifo_sunch_a(63*4-1 downto 61*4); --RPC + TRIG_OUT(16*4-1 downto 8*4) <= output_from_fifo_sunch_a(48*4-1 downto 40*4); --VETO + end if; + end process MAKE_POLAR_AND_SYNCH; --veto and PT connector number 3 --TOF and RPC connector number 4 ----------------------------------------------------------------------------- -- beam structure (pulses on rising edge made in the beam structure component) ----------------------------------------------------------------------------- - SET_START_VETO_STRUCT_SIGNALS: for i in 0 to 63 generate + SET_START_VETO_STRUCT_SIGNALS: for i in 0 to 39 generate SET_HISTOGRAM_SIGNALS_PROC : process (CLK, RESET) begin if rising_edge(CLK) then if RESET = '1' then start_veto_beam_struct_signals(i) <= '0'; - elsif output_from_fifo_sunch_a((i+1)*4-1 downto i*4) > 0 then + elsif output_from_fifo_sunch_a((i+1)*4-1 downto i*4) /= x"f" then +--inverted start and veto inputs start_veto_beam_struct_signals(i) <= '1'; else start_veto_beam_struct_signals(i) <= '0'; @@ -296,7 +350,7 @@ begin ----------------------------------------------------------------------------- ddr_in_vector_a <= - FAST_LVDS_TIMING_IN & FAST_LVDS_TIMING_IN & + FAST_LVDS_TIMING_IN & FAST_LVDS_TIMING_IN & FAST_LVDS_TIMING_IN & MULTIPLEXER_IN & FAST_MDCB_TIMING_IN & FAST_MDCB_TIMING_IN & FAST_MDCA_TIMING_IN & FAST_MDCA_TIMING_IN & FAST_MDCA_TIMING_IN & @@ -309,6 +363,16 @@ begin -- clkop => open, -- clkos => ddr_edge_clk(4), -- lock => open); + + +-- DLL_EDGE_INJECTION_COMPENSATE_PECL: dll_edge +-- port map ( +-- clk => EDGE_CLK, +-- aluhold => '0', +-- clkop => open, +-- clkos => ddr_edge_clk(4), +-- lock => open); + DCS_A: DCS --no_sim-- -- synthesis translate_off --no_sim-- generic map ( --no_sim-- @@ -320,26 +384,49 @@ begin CLK1 => '0', --no_sim-- DCSOUT => ddr_edge_clk(4) ); --no_sim-- + + MAKE_CORR_OUT_ORDER_A: for i in 0 to 3 generate + ddr_in_vector_a_corr((i+1)*13-1 downto i*13) <= ddr_in_vector_a(i+48) & + ddr_in_vector_a(i+44) & ddr_in_vector_a(i+40) & ddr_in_vector_a(i+36) & ddr_in_vector_a(i+32) & + ddr_in_vector_a(i+28) & ddr_in_vector_a(i+24) & ddr_in_vector_a(i+20) & ddr_in_vector_a(i+16) & + ddr_in_vector_a(i+12) & ddr_in_vector_a(i+ 8) & ddr_in_vector_a(i+ 4) & ddr_in_vector_a(i ); + end generate MAKE_CORR_OUT_ORDER_A; ---sim-- ddr_edge_clk(4) <= EDGE_CLK; - REWRITE_DDR_DATA_OUT: for i in 0 to 2 generate - FIFO16BIT_SYNCH_OUT_A: fifo16bit_synch + FIFO16BIT_SYNCH_OUT_A: fifo52bit_synch port map ( - Data => ddr_in_vector_a((i+1)*16-1 downto i*16), + Data => ddr_in_vector_a_corr, WrClock => CLK, RdClock => ddr_div_out_clk(0), - WrEn => '1', + WrEn => dll_lock(0), RdEn => '1', Reset => RESET, RPReset => RESET, - Q => ddr_out_vector_a((i+1)*16-1 downto i*16), + Q => ddr_out_vector_a, Empty => open, Full => open, AlmostEmpty => open, AlmostFull => open); - end generate REWRITE_DDR_DATA_OUT; + + +--sim-- ddr_edge_clk(4) <= EDGE_CLK; +-- REWRITE_DDR_DATA_OUT: for i in 0 to 2 generate +-- FIFO16BIT_SYNCH_OUT_A: fifo16bit_synch +-- port map ( +-- Data => ddr_in_vector_a((i+1)*16-1 downto i*16), +-- WrClock => CLK, +-- RdClock => ddr_div_out_clk(0), +-- WrEn => '1', +-- RdEn => '1', +-- Reset => RESET, +-- RPReset => RESET, +-- Q => ddr_out_vector_a((i+1)*16-1 downto i*16), +-- Empty => open, +-- Full => open, +-- AlmostEmpty => open, +-- AlmostFull => open); +-- end generate REWRITE_DDR_DATA_OUT; - DDR2_12OUT_CLKDIV_INST: ddr2_12out_clkdiv + DDR2_12OUT_CLKDIV_INST: ddr2_13out_clkdiv port map ( Data => ddr_out_vector_a, EClk => ddr_edge_clk(4), @@ -355,27 +442,29 @@ begin -- clkop => open, -- clkos => ddr_edge_clk(5), -- lock => open); - DCS_B : DCS --no_sim-- --- synthesis translate_off --no_sim-- - generic map ( --no_sim-- - DCSMODE => "POS") --no_sim-- --- synthesis translate_on --no_sim-- - port map ( --no_sim-- - SEL => '0', --no_sim-- - CLK0 => EDGE_CLK, --no_sim-- - CLK1 => '0', --no_sim-- - DCSOUT => ddr_edge_clk(5) ); --no_sim-- +-- DCS_B : DCS --no_sim-- +---- synthesis translate_off --no_sim-- +-- generic map ( --no_sim-- +-- DCSMODE => "POS") --no_sim-- +---- synthesis translate_on --no_sim-- +-- port map ( --no_sim-- +-- SEL => '0', --no_sim-- +-- CLK0 => EDGE_CLK, --no_sim-- +-- CLK1 => '0', --no_sim-- +-- DCSOUT => ddr_edge_clk(5) ); --no_sim-- --sim-- ddr_edge_clk(5) <= EDGE_CLK; - ddr_in_vector_b <= x"0" & FAST_PECL_TIMING_IN & FAST_PECL_TIMING_IN & FAST_PECL_TIMING_IN; --pecl out bank 2 - - FIFO16BIT_SYNCH_OUT_B: fifo16bit_synch + ddr_in_vector_b <= FAST_PECL_TIMING_IN(3) & FAST_PECL_TIMING_IN(3) & FAST_PECL_TIMING_IN(3) & + FAST_PECL_TIMING_IN(2) & FAST_PECL_TIMING_IN(2) & FAST_PECL_TIMING_IN(2) & + FAST_PECL_TIMING_IN(1) & FAST_PECL_TIMING_IN(1) & FAST_PECL_TIMING_IN(1) & + FAST_PECL_TIMING_IN(0) & FAST_PECL_TIMING_IN(0) & FAST_PECL_TIMING_IN(0); + FIFO16BIT_SYNCH_OUT_B: fifo12bit_synch port map ( Data => ddr_in_vector_b, WrClock => CLK, RdClock => ddr_div_clk(0), - WrEn => '1', + WrEn => dll_lock(0), RdEn => '1', Reset => RESET, RPReset => RESET, @@ -387,7 +476,7 @@ begin DDR2_3OUT_CLKDIV_INST: ddr2_3out_clkdiv port map ( - Data => ddr_out_vector_b(11 downto 0), + Data => ddr_out_vector_b, EClk => ddr_edge_clk(0), Rst => RESET, SClk => ddr_div_out_clk(1), diff --git a/ddr_lvl1_trigger.vhd b/ddr_lvl1_trigger.vhd index 92efba0..adc67ef 100644 --- a/ddr_lvl1_trigger.vhd +++ b/ddr_lvl1_trigger.vhd @@ -47,8 +47,7 @@ entity ddr_lvl1_trigger is LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0); DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_0 : out std_logic_vector(31 downto 0); - DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 : out std_logic_vector(31 downto 0); - DDR_LVL1_TRIGGER_BUFFER_CTRL_IN_0 : in std_logic_vector(11 downto 0) + DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 : out std_logic_vector(31 downto 0) ); end ddr_lvl1_trigger; @@ -551,7 +550,7 @@ begin FAST_TRIGGER_OUT_LVDS <= fast_trigger_sync(0); - FAST_TRIGGER_OUT_PECL <= fast_trigger_sync(1); + FAST_TRIGGER_OUT_PECL <= fast_trigger_sync(0); MDCA_TRIGGER_OUT <= mdca_trigger; MDCB_TRIGGER_OUT <= mdcb_trigger; diff --git a/dll_in400_out200.vhd b/dll_in400_out200.vhd index 6a45c8e..f005f3e 100644 --- a/dll_in400_out200.vhd +++ b/dll_in400_out200.vhd @@ -1,14 +1,14 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 3.5 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n dll_in400_out200 -lang vhdl -synth synplify -bus_exp 7 -bb -arch slayer -type dll -dll_type cid -fin 400 -clkos_div 2 -fb_mode 0 -e +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n dll_in400_out200 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type dll -dll_type cid -fin 400 -clkos_div 2 -fb_mode 1 -e --- Tue Nov 1 11:30:03 2011 +-- Mon Feb 13 22:26:37 2012 library IEEE; use IEEE.std_logic_1164.all; -- synopsys translate_off -library SC; -use SC.COMPONENTS.all; +library SCM; +use SCM.COMPONENTS.all; -- synopsys translate_on entity dll_in400_out200 is @@ -29,9 +29,9 @@ architecture Structure of dll_in400_out200 is -- internal signal declarations signal scuba_vlo: std_logic; - signal clkos_t: std_logic; signal scuba_vhi: std_logic; signal clkop_t: std_logic; + signal clkos_t: std_logic; signal clk_t: std_logic; attribute module_type : string; @@ -87,7 +87,7 @@ architecture Structure of dll_in400_out200 is attribute ALU_INIT_CNTVAL of dll_in400_out200_0_0 : label is "0"; attribute ALU_UNLOCK_CNT of dll_in400_out200_0_0 : label is "3"; attribute ALU_LOCK_CNT of dll_in400_out200_0_0 : label is "3"; - attribute CLKI_DIV of dll_in400_out200_0_0 : label is "1"; + attribute CLKI_DIV of dll_in400_out200_0_0 : label is "2"; attribute CLKOS_DIV of dll_in400_out200_0_0 : label is "2"; attribute CLKOS_FPHASE of dll_in400_out200_0_0 : label is "0"; attribute CLKOS_PHASE of dll_in400_out200_0_0 : label is "90"; @@ -110,7 +110,7 @@ begin , CLKOS_DIV=> 2, CLKOS_FPHASE=> 0 -- synopsys translate_on ) - port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>scuba_vhi, + port map (CLKI=>clk_t, CLKFB=>clkos_t, RSTN=>scuba_vhi, ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, @@ -126,12 +126,12 @@ begin end Structure; -- synopsys translate_off -library SC; +library SCM; configuration Structure_CON of dll_in400_out200 is for Structure - for all:VHI use entity SC.VHI(V); end for; - for all:VLO use entity SC.VLO(V); end for; - for all:CIDDLLA use entity SC.CIDDLLA(V); end for; + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:CIDDLLA use entity SCM.CIDDLLA(V); end for; end for; end Structure_CON; diff --git a/multiplicity.vhd b/multiplicity.vhd index 4a8eeab..0e91003 100644 --- a/multiplicity.vhd +++ b/multiplicity.vhd @@ -14,8 +14,9 @@ entity multiplicity is RESET : in std_logic; CLK : in std_logic; SIGNAL_IN : in std_logic_vector(5 downto 0); - SIGNAL_OUT : out std_logic_vector(8 downto 0) - ); + SIGNAL_OUT : out std_logic_vector(8 downto 0); + SAMPLE_DELAY_IN : in std_logic_vector(3 downto 0) + ); end multiplicity; architecture multiplicity of multiplicity is @@ -26,11 +27,24 @@ architecture multiplicity of multiplicity is signal_in : in std_logic; pulse : out std_logic); end component; + + component cts_delay_large + generic ( + VECTOR_WIDTH : integer range 1 to 32); + port ( + RESET : in std_logic; + CLK : in std_logic; + DELAY_IN : in std_logic_vector(7 downto 0); + DELAY_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0); + DELAY_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0)); + end component; + signal signal_out_i : std_logic_vector(8 downto 0); signal signal_out_buf_sync : std_logic_vector(8 downto 0); signal signal_out_buf : std_logic_vector(8 downto 0); - signal sample_mult_signal : std_logic; + signal sample_mult_signal, sample_mult_signal_pulse : std_logic_vector(0 downto 0); signal mult_signal_en : std_logic; + signal sample_delay_value : std_logic_vector(7 downto 0); begin --there is assumption that the input signals are aligned with proper delay and --width settings - in that case signals from the same event should be within 20 @@ -47,21 +61,33 @@ begin end if; end if; end process ENABLE_MULT_SIGNAL; - + MULT_SAMPLE_PULSE : edge_to_pulse port map ( clock => CLK, en_clk => '1', signal_in => mult_signal_en, - pulse => sample_mult_signal --20 ns after input has + pulse => sample_mult_signal_pulse(0) --20 ns after input has --changed(mult.is settled after 20ns) ); + + sample_delay_value <= x"0" & SAMPLE_DELAY_IN; + MULT_ARRAY_DELAY: cts_delay_large + generic map ( + VECTOR_WIDTH => 1) + port map ( + RESET => RESET, + CLK => CLK, + DELAY_IN => sample_delay_value, + DELAY_VECTOR_IN => sample_mult_signal_pulse, + DELAY_VECTOR_OUT => sample_mult_signal); + MAKE_FINAL_MULT : process (CLK, RESET) begin if rising_edge(CLK) then if RESET = '1' then signal_out_i <= (others => '0'); - elsif sample_mult_signal = '1' then --after 20 ns the mult. signal is sampled + elsif sample_mult_signal(0) = '1' then --after 20 ns the mult. signal is sampled signal_out_i <= signal_out_buf_sync; else signal_out_i <= (others => '0'); diff --git a/pll_in200_out400.vhd b/pll_in200_out400.vhd index d626538..b5100ee 100644 --- a/pll_in200_out400.vhd +++ b/pll_in200_out400.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 5.2 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n pll_in200_out400 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 200 -mfreq 400 -nfreq 100 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n pll_in200_out400 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 200 -mfreq 400 -nfreq 100 -clkos_fdel 0 -fb 0 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e --- Wed Nov 9 10:40:07 2011 +-- Tue Feb 14 14:17:30 2012 library IEEE; use IEEE.std_logic_1164.all; @@ -30,6 +30,7 @@ architecture Structure of pll_in200_out400 is signal scuba_vlo: std_logic; signal scuba_vhi: std_logic; signal clkos_t: std_logic; + signal fb: std_logic; signal clkop_t: std_logic; signal clk_t: std_logic; @@ -145,9 +146,9 @@ begin SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, - SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t, - RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, - CLKINTFB=>open, SMIRDATA=>open); + SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>fb, RSTN=>scuba_vhi, + CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, CLKINTFB=>fb, + SMIRDATA=>open); clkos <= clkos_t; clkop <= clkop_t; diff --git a/version.vhd b/version.vhd index 0bfb352..6b295d6 100644 --- a/version.vhd +++ b/version.vhd @@ -8,6 +8,6 @@ use ieee.numeric_std.all; package version is - constant VERSION_NUMBER_TIME : integer := 1326799917; + constant VERSION_NUMBER_TIME : integer := 1332000868; end package version;