From: Tobias Weber <webert@kph.uni-mainz.de>
Date: Sat, 21 Mar 2015 14:44:44 +0000 (+0100)
Subject: delay the hitbus signal for time walk measurement.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d286c4edcc0d8eb719f733fad89c40835485d7f7;p=trb3.git

delay the hitbus signal for time walk measurement.
---

diff --git a/mupix/sources/TimeWalk.vhd b/mupix/sources/TimeWalk.vhd
index a8256cd..750cc49 100644
--- a/mupix/sources/TimeWalk.vhd
+++ b/mupix/sources/TimeWalk.vhd
@@ -6,6 +6,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.numeric_std.all;
 
+
 entity TimeWalk is
   port (
     clk                  : in  std_logic;
@@ -22,24 +23,45 @@ architecture TimeWalk_Arch of TimeWalk is
 
   signal latencycounter            : unsigned(15 downto 0)        := (others => '0');
   signal hitbuscounter             : unsigned(15 downto 0)        := (others => '0');
+  signal hitbus_delayed            : std_logic := '0';
   signal hitbus_edge               : std_logic_vector(1 downto 0) := (others => '0');
   signal szintillator_trigger_edge : std_logic_vector(1 downto 0) := (others => '0');
-  signal hitbusBuffer : std_logic := '0';
-  signal szintilatorTriggerBuffer : std_logic := '0';
+  signal szintillator_trigger_buffer : std_logic := '0';
   type TimeWalk_fsm_type is (idle, waitforhitbus, measurehitbus, measurement_done);
   signal timewalk_fsm              : TimeWalk_fsm_type            := idle;
 
+  component SignalDelay is
+    generic (
+      Width : integer range 1 to 32;
+      Delay : integer range 2 to 8);
+    port (
+      clk_in   : in  std_logic;
+      write_en_in : in std_logic;
+      delay_in : in  std_logic_vector(Delay - 1 downto 0);
+      sig_in   : in  std_logic_vector(Width - 1 downto 0);
+      sig_out  : out std_logic_vector(Width - 1 downto 0));
+  end component SignalDelay;
   
 begin  -- architecture TimeWalk_Arch
 
+  SignalDelay_1: entity work.SignalDelay
+    generic map (
+      Width => 1,
+      Delay => 12)
+    port map (
+      clk_in   => clk,
+      write_en_in => '1',
+      delay_in => std_logic_vector(to_unsigned(16,12)),
+      sig_in(0)   => hitbus,
+      sig_out(0)  => hitbus_delayed);
+  
   -- purpose: synchronize signals and edge detection
   signal_synchro: process (clk) is
   begin  -- process clk
     if rising_edge(clk) then
-      hitbusBuffer <= hitbus;
-      szintilatorTriggerBuffer <= szintillator_trigger;
-      hitbus_edge               <= hitbus_edge(0) & hitbusBuffer;
-      szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintilatorTriggerBuffer;  
+      hitbus_edge               <= hitbus_edge(0) & hitbus_delayed;
+      szintillator_trigger_buffer <= szintillator_trigger;
+      szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintillator_trigger_buffer;  
     end if;
   end process signal_synchro;
 
@@ -54,7 +76,7 @@ begin  -- architecture TimeWalk_Arch
         hitbuscounter  <= (others => '0');
         if szintillator_trigger_edge = "01" then
           timewalk_fsm   <= waitforhitbus;
-          latencycounter <= latencycounter + 1;
+          latencycounter <= to_unsigned(1,16);
         end if;
         when waitforhitbus =>
         latencycounter <= latencycounter + 1;
@@ -62,7 +84,7 @@ begin  -- architecture TimeWalk_Arch
           timewalk_fsm <= idle;
         elsif hitbus_edge = "01" then
           timewalk_fsm  <= measurehitbus;
-          hitbuscounter <= hitbuscounter + 1;
+          hitbuscounter <= to_unsigned(1,16);
         else
           timewalk_fsm <= waitforhitbus;
         end if;
diff --git a/mupix/sources/TimeWalkWithFiFo.vhd b/mupix/sources/TimeWalkWithFiFo.vhd
index b06bcd9..59bcaac 100644
--- a/mupix/sources/TimeWalkWithFiFo.vhd
+++ b/mupix/sources/TimeWalkWithFiFo.vhd
@@ -32,7 +32,7 @@ end entity TimeWalkWithFiFo;
 architecture TimeWalk_arch of TimeWalkWithFiFo is
 
   constant bitsBeforeWriteCounter : integer := 2;
-  signal hitbus_timeout            : std_logic_vector(31 downto 0)        := (others => '0');
+  signal hitbus_timeout            : std_logic_vector(31 downto 0)        := x"00000024";
 
   signal resetcounters : std_logic := '0';
   signal hitbusEdgeCounter : unsigned(31 downto 0) := (others => '0');
diff --git a/mupix/sources/mupix_components.vhd b/mupix/sources/mupix_components.vhd
index 8a429e0..7eebcbe 100644
--- a/mupix/sources/mupix_components.vhd
+++ b/mupix/sources/mupix_components.vhd
@@ -334,5 +334,6 @@ package mupix_components is
       measurementFinished  : out std_logic;
       measurementData      : out std_logic_vector(31 downto 0));
   end component TimeWalk;
+
   
 end mupix_components;
diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj
index 71067e9..f82fd15 100644
--- a/mupix/trb3_periph.prj
+++ b/mupix/trb3_periph.prj
@@ -159,4 +159,5 @@ add_file -vhdl -lib "work" "cores/fifo_32x2k.vhd"
 add_file -vhdl -lib "work" "sources/ResetHandler.vhd"
 add_file -vhdl -lib "work" "cores/fifo_4k32_async.vhd"
 add_file -vhdl -lib "work" "sources/TimeWalk.vhd"
-add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd"
\ No newline at end of file
+add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd"
+add_file -vhdl -lib "work" "sources/SignalDelay.vhd"
\ No newline at end of file