From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Wed, 11 Feb 2015 09:37:26 +0000 (+0100)
Subject: Synplify: Set clock timing for ADC to 163MHz, enable retiming and pipelining
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d2b64a1d660b8349045f83c7408cd626cbba6ebb;p=trb3.git

Synplify: Set clock timing for ADC to 163MHz, enable retiming and pipelining
---

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index cf186b5..2997f12 100644
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -19,8 +19,8 @@ set_option -resource_sharing true
 set_option -frequency 200
 set_option -fanout_limit 100
 set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
+set_option -retiming 1
+set_option -pipe 1
 #set_option -force_gsr 
 set_option -force_gsr false
 set_option -fixgatedclocks false #3
diff --git a/ADC/trb3_periph_adc.sdc b/ADC/trb3_periph_adc.sdc
index 0909361..9ffbb0f 100644
--- a/ADC/trb3_periph_adc.sdc
+++ b/ADC/trb3_periph_adc.sdc
@@ -13,8 +13,8 @@
 define_clock   {CLK_PCLK_RIGHT} -name {CLK_PCLK_RIGHT}  -freq 200 -clockgroup default_clkgroup_0
 define_clock   {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1}  -freq 100 -clockgroup default_clkgroup_1
 define_clock   {TRIGGER_LEFT} -name {TRIGGER_LEFT}  -freq 10 -clockgroup default_clkgroup_2
-define_clock   {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk}  -freq 100 -clockgroup default_clkgroup_3
-define_clock   {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk}  -freq 100 -clockgroup default_clkgroup_4
+define_clock   {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk}  -freq 163 -clockgroup default_clkgroup_3
+define_clock   {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk}  -freq 163 -clockgroup default_clkgroup_4
 define_clock   {n:THE_MAIN_PLL.CLKOP} -name {n:THE_MAIN_PLL.CLKOP}  -freq 100 -clockgroup default_clkgroup_5
 define_clock   {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1}  -freq 100 -clockgroup default_clkgroup_6
 define_clock   {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1}  -freq 100 -clockgroup default_clkgroup_7