From: Thomas Gessler Date: Wed, 5 Aug 2020 14:57:43 +0000 (+0200) Subject: XCKU media interfaces: simplify and clean up X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d2d02ddc9fa864f536a4e2403be34bcb4fd24f0c;p=trbnet.git XCKU media interfaces: simplify and clean up --- diff --git a/media_interfaces/med_xcku_sfp_sync.vhd b/media_interfaces/med_xcku_sfp_sync.vhd index b23bbbe..ec1aecc 100644 --- a/media_interfaces/med_xcku_sfp_sync.vhd +++ b/media_interfaces/med_xcku_sfp_sync.vhd @@ -1,275 +1,165 @@ ---Media interface for Xilinx Kintex UltraScale - - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.all; +library ieee; +use ieee.std_logic_1164.all; library work; use work.trb_net_std.all; -use work.config.all; use work.trb_net_components.all; use work.med_sync_define.all; entity med_xcku_sfp_sync is - generic( - SERDES_NUM : integer range 0 to 3 := 0; - IS_SYNC_SLAVE : integer := c_YES --select slave mode + generic ( + IS_SYNC_SLAVE : integer := c_NO ); - port( - CLK_REF_FULL : in std_logic; -- 200 MHz reference clock - CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - TX_USRCLK : out std_logic; - FREECLK : in std_logic; - --Internal Connection TX - MEDIA_MED2INT : out MED2INT; - MEDIA_INT2MED : in INT2MED; - - --Sync operation - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; - TX_DLM : in std_logic := '0'; - TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; - - --SFP Connection - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable - SD_REFCLK : in std_logic; - SD_RX_N : in std_logic; - SD_RX_P : in std_logic; - SD_TX_N : out std_logic; - SD_TX_P : out std_logic; - --Control Interface - BUS_RX : in CTRLBUS_RX; - BUS_TX : out CTRLBUS_TX; - - -- Status and control port - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') - ); -end entity; - - -architecture med_xcku_sfp_sync_arch of med_xcku_sfp_sync is + port ( + SYSCLK : in std_logic; + CLK_200 : in std_logic; + GTREFCLK : in std_logic; - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of med_xcku_sfp_sync_arch : architecture is "media_interface_group"; - attribute syn_sharing : string; - attribute syn_sharing of med_xcku_sfp_sync_arch : architecture is "off"; - attribute syn_hier : string; - attribute syn_hier of med_xcku_sfp_sync_arch : architecture is "hard"; + RESET : in std_logic; + CLEAR : in std_logic; --- signal clk_200_i : std_logic; -signal clk_200_ref : std_logic; -signal clk_rx_full : std_logic; -signal clk_tx_full : std_logic; + RXN : in std_logic; + RXP : in std_logic; + TXN : out std_logic; + TXP : out std_logic; -signal tx_data : std_logic_vector(7 downto 0); -signal tx_k : std_logic; -signal rx_data : std_logic_vector(7 downto 0); -signal rx_k : std_logic; -signal rx_error : std_logic; + MEDIA_MED2INT : out MED2INT; + MEDIA_INT2MED : in INT2MED; -signal rst_n : std_logic; -signal rx_serdes_rst : std_logic; -signal tx_serdes_rst : std_logic; -signal tx_pcs_rst : std_logic; -signal rx_pcs_rst : std_logic; -signal rst_qd : std_logic; -signal serdes_rst_qd : std_logic; + RX_DLM : out std_logic := '0'; + RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; + TX_DLM : in std_logic := '0'; + TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; -signal rx_los_low : std_logic; -signal lsm_status : std_logic; -signal rx_cdr_lol : std_logic; -signal tx_pll_lol : std_logic; + SD_LOS_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; -signal sci_ch_i : std_logic_vector(4 downto 0); -signal sci_addr_i : std_logic_vector(5 downto 0); -signal sci_data_in_i : std_logic_vector(7 downto 0); -signal sci_data_out_i : std_logic_vector(7 downto 0); -signal sci_read_i : std_logic; -signal sci_write_i : std_logic; + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; -signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; -signal wa_position_sel : std_logic_vector(3 downto 0); - -signal stat_rx_control_i : std_logic_vector(31 downto 0); -signal stat_tx_control_i : std_logic_vector(31 downto 0); -signal debug_rx_control_i : std_logic_vector(31 downto 0); -signal debug_tx_control_i : std_logic_vector(31 downto 0); -signal stat_fsm_reset_i : std_logic_vector(31 downto 0); -signal debug_med_sync_control_i : std_logic_vector(31 downto 0); - -signal stat_med : std_logic_vector(31 downto 0); - -signal reset_rx_pll_dp : std_logic := '0'; -signal reset_all : std_logic := '0'; -signal reset_clk_freerun : std_logic := '0'; -signal reset_tx_pll_dp : std_logic := '0'; -signal reset_tx_dp : std_logic := '0'; -signal reset_rx_dp : std_logic := '0'; -signal reset_rx_cdr : std_logic; -signal reset_tx_done : std_logic; -signal reset_rx_done : std_logic; -signal gtrefClk : std_logic; - -signal gtpowergood_i : std_logic; -signal tx_ready_i : std_logic; -signal rx_ready_i : std_logic; -signal tx_active_i : std_logic; -signal rx_active_i : std_logic; -signal rx_cdr_stable_i : std_logic; + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; -signal init_done_i : std_logic; +architecture med_xcku_sfp_sync_arch of med_xcku_sfp_sync is + signal usrclk_full : std_logic; + signal usrclk_half : std_logic; + + signal txdata : std_logic_vector(7 downto 0); + signal txcharisk : std_logic; + signal txchardispmode : std_logic; + signal rxdata : std_logic_vector(7 downto 0); + signal rxcharisk : std_logic; + signal rxnotintable : std_logic; + + signal rxpmareset : std_logic; + signal txpcsreset : std_logic; + signal rxpcsreset : std_logic; + signal quad_rst : std_logic; + signal reset_all : std_logic; + + signal rx_los : std_logic; + signal rx_cdr_lol : std_logic; + signal tx_lol : std_logic; + + signal reset_tx_done : std_logic; + signal rxpmaresetdone : std_logic; + signal txpmaresetdone : std_logic; + + signal debug_rx_control_i : std_logic_vector(31 downto 0); + signal debug_tx_control_i : std_logic_vector(31 downto 0); begin + SD_TXDIS_OUT <= '0'; + + reset_all <= quad_rst; + + THE_SERDES : entity work.gth_xcku_x0y8_top + port map ( + CLK_100 => SYSCLK, + GTREFCLK => GTREFCLK, + USRCLK_FULL => usrclk_full, + USRCLK_HALF => usrclk_half, + RESET_ALL => reset_all, + RXPMARESET => rxpmareset, + RXPCSRESET => rxpcsreset, + TXPMARESET => '0', + TXPCSRESET => txpcsreset, + USRCLK_LOCKED => open, + INIT_DONE => open, + RXRESETDONE => open, + TXRESETDONE => open, + RXPMARESETDONE => rxpmaresetdone, + TXPMARESETDONE => txpmaresetdone, + RXBYTEISALIGNED => open, + RXN => RXN, + RXP => RXP, + TXN => TXN, + TXP => TXP, + TXDATA => txdata, + TXCHARISK => txcharisk, + TXCHARDISPMODE => txchardispmode, + TXCHARDISPVAL => '0', + RXDATA => rxdata, + RXCHARISK => rxcharisk, + RXCHARISCOMMA => open, + RXNOTINTABLE => rxnotintable, + RXDISPERR => open + ); -clk_200_ref <= CLK_REF_FULL; - -SD_TXDIS_OUT <= not rx_ready_i when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready --- SD_TXDIS_OUT <= RESET; - --- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate --- clk_200_i <= clk_rx_full; --- end generate; --- --- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate --- clk_200_i <= clk_200_internal; --- end generate; - - -------------------------------------------------- --- Serdes -------------------------------------------------- -gen_pcs0 : if SERDES_NUM = 0 generate - -THE_GTH_8b10b : entity work.gth_xcku_x0y8_top - port map( - clk_100 => SYSCLK, - clk_200 => CLK_INTERNAL_FULL, - reset_all => RESET, - mgtrefclk0_x0y3_int => SD_REFCLK, - FREECLK => FREECLK, - - ch0_gthrxn_in => SD_RX_N, - ch0_gthrxp_in => SD_RX_P, - ch0_gthtxn_out => SD_TX_N, - ch0_gthtxp_out => SD_TX_P, - - tx_clk => clk_tx_full, - tx_data => tx_data, - tx_k => tx_k, - - rx_clk => clk_rx_full, - rx_data => rx_data, --clk with 200MHz osci - rx_k => rx_k, - - rx_cdr_stable => rx_cdr_stable_i, - tx_pll_reset => '0',--reset_tx_pll_and_datapath_i, - rx_pll_reset => '0',--reset_rx_pll_and_datapath_i, - - tx_ready => tx_ready_i, - rx_ready => rx_ready_i, - - tx_active => tx_active_i, - rx_active => rx_active_i, - gtpowergood => gtpowergood_i, - - init_done => init_done_i, - TX_USRCLK => TX_USRCLK - ); + tx_lol <= not txpmaresetdone; + rx_cdr_lol <= not rxpmaresetdone; -end generate; - tx_serdes_rst <= '0'; --SD_LOS_IN; --no function - serdes_rst_qd <= '0'; --included in rst_qd - wa_position_sel <= x"0"; --- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0 --- else wa_position(15 downto 12) when SERDES_NUM = 3; - -THE_MED_CONTROL : entity work.med_sync_control - generic map( - IS_SYNC_SLAVE => IS_SYNC_SLAVE, - IS_TX_RESET => 1 + THE_MED_CONTROL : entity work.med_sync_control + generic map( + IS_SYNC_SLAVE => IS_SYNC_SLAVE, + IS_TX_RESET => 1 ) - port map( - CLK_SYS => SYSCLK, - CLK_RXI => clk_rx_full, --clk_rx_full, - CLK_RXHALF => '0', - CLK_TXI => clk_tx_full, --clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 - CLK_REF => CLK_INTERNAL_FULL, - RESET => RESET, - CLEAR => CLEAR, - - INIT_DONE => init_done_i, - - TX_ACTIVE => tx_active_i, - RX_ACTIVE => rx_active_i, - - RX_SERDES_RST => open, - TX_SERDES_RST => open, - - MEDIA_MED2INT => MEDIA_MED2INT, - MEDIA_INT2MED => MEDIA_INT2MED, - - TX_DATA => tx_data, - TX_K => tx_k, - RX_DATA => rx_data, - RX_K => rx_k, - - TX_DLM_WORD => TX_DLM_WORD, - TX_DLM => TX_DLM, - RX_DLM_WORD => RX_DLM_WORD, - RX_DLM => RX_DLM, - - SERDES_RX_READY_IN => rx_ready_i, - SERDES_TX_READY_IN => tx_ready_i, - - STAT_TX_CONTROL => stat_tx_control_i, - STAT_RX_CONTROL => stat_rx_control_i, - DEBUG_TX_CONTROL => debug_tx_control_i, - DEBUG_RX_CONTROL => debug_rx_control_i, - STAT_RESET => stat_fsm_reset_i, - DEBUG_OUT => debug_med_sync_control_i + port map( + CLK_SYS => SYSCLK, + CLK_RXI => usrclk_full, + CLK_RXHALF => usrclk_half, + CLK_TXI => usrclk_full, + CLK_REF => CLK_200, + RESET => RESET, + CLEAR => CLEAR, + SFP_LOS => SD_LOS_IN, + TX_LOL => tx_lol, + RX_CDR_LOL => rx_cdr_lol, + RX_LOS => SD_LOS_IN, + WA_POSITION => (others => '0'), + RX_SERDES_RST => rxpmareset, + RX_PCS_RST => rxpcsreset, + QUAD_RST => quad_rst, + TX_PCS_RST => txpcsreset, + MEDIA_MED2INT => MEDIA_MED2INT, + MEDIA_INT2MED => MEDIA_INT2MED, + TX_DATA => txdata, + TX_K => txcharisk, + TX_CD => txchardispmode, + RX_DATA => rxdata, + RX_K => rxcharisk, + TX_DLM_WORD => TX_DLM_WORD, + TX_DLM => TX_DLM, + RX_DLM_WORD => RX_DLM_WORD, + RX_DLM => RX_DLM, + STAT_TX_CONTROL => open, + STAT_RX_CONTROL => open, + DEBUG_TX_CONTROL => debug_tx_control_i, + DEBUG_RX_CONTROL => debug_rx_control_i, + STAT_RESET => open ); -THE_BUS : process begin - wait until rising_edge(SYSCLK); - BUS_TX.unknown <= BUS_RX.read or BUS_RX.write; - BUS_TX.ack <= '0'; -end process; + THE_BUS: + process is + begin + wait until rising_edge(SYSCLK); + BUS_TX.unknown <= BUS_RX.read or BUS_RX.write; + BUS_TX.ack <= '0'; + end process; --- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); --- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); --- STAT_DEBUG(7) <= '0'; --- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); --- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); --- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); - STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0); - STAT_DEBUG(7 downto 4) <= rx_los_low & lsm_status & rx_cdr_lol & tx_pll_lol; --- STAT_DEBUG(9) <= CLK_REF_FULL; --- STAT_DEBUG(10) <= clk_rx_full; --- STAT_DEBUG(11) <= clk_tx_full; - - -stat_med(0) <= rst_qd; -stat_med(1) <= rx_pcs_rst; -stat_med(2) <= tx_pcs_rst; -stat_med(3) <= rx_serdes_rst; -stat_med(4) <= tx_pll_lol; -stat_med(5) <= rx_cdr_lol; -stat_med(6) <= rx_los_low; -stat_med(7) <= rx_ready_i; -stat_med(8) <= tx_ready_i; -stat_med(9) <= lsm_status; -stat_med(31 downto 10) <= (others => '0'); - - + STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); + STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); end architecture; - diff --git a/media_interfaces/med_xcku_sfp_sync_4.vhd b/media_interfaces/med_xcku_sfp_sync_4.vhd index 4098b89..cdffa9f 100644 --- a/media_interfaces/med_xcku_sfp_sync_4.vhd +++ b/media_interfaces/med_xcku_sfp_sync_4.vhd @@ -1,259 +1,176 @@ ---Media interface for Xilinx Kintex UltraScale - - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.all; +library ieee; +use ieee.std_logic_1164.all; library work; use work.trb_net_std.all; -use work.config.all; use work.trb_net_components.all; use work.med_sync_define.all; entity med_xcku_sfp_sync_4 is - generic( - IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); --select slave mode - IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES) + generic ( + IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); + IS_USED : int_array_t(0 to 3) := (c_YES, c_YES, c_YES, c_YES) ); - port( - CLK_REF_FULL : in std_logic; -- 200 MHz reference clock - CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - TX_USRCLK : out std_logic; - FREECLK : in std_logic; - --Internal Connection TX - MEDIA_MED2INT : out med2int_array_t(0 to 3); - MEDIA_INT2MED : in int2med_array_t(0 to 3); - - --Sync operation - RX_DLM : out std_logic_vector(3 downto 0) := x"0"; - RX_DLM_WORD : out std_logic_vector(4*8-1 downto 0) := (others => '0'); - TX_DLM : in std_logic_vector(3 downto 0) := x"0"; - TX_DLM_WORD : in std_logic_vector(4*8-1 downto 0) := (others => '0'); - - --SFP Connection - SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable - SD_REFCLK : in std_logic; - SD_RX_N : in std_logic_vector(3 downto 0); - SD_RX_P : in std_logic_vector(3 downto 0); - SD_TX_N : out std_logic_vector(3 downto 0); - SD_TX_P : out std_logic_vector(3 downto 0); - --Control Interface - BUS_RX : in CTRLBUS_RX; - BUS_TX : out CTRLBUS_TX; - - -- Status and control port - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') - ); -end entity; - - -architecture med_xcku_sfp_sync_4_arch of med_xcku_sfp_sync_4 is - - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of med_xcku_sfp_sync_4_arch : architecture is "media_interface_group"; - attribute syn_sharing : string; - attribute syn_sharing of med_xcku_sfp_sync_4_arch : architecture is "off"; - attribute syn_hier : string; - attribute syn_hier of med_xcku_sfp_sync_4_arch : architecture is "hard"; - --- signal clk_200_i : std_logic; -signal clk_200_ref : std_logic; -signal clk_rx_full : std_logic; -signal clk_tx_full : std_logic; + port ( + SYSCLK : in std_logic; + CLK_200 : in std_logic; + GTREFCLK : in std_logic; -signal tx_data : std_logic_vector(4*8-1 downto 0); -signal tx_k : std_logic_vector(3 downto 0); -signal rx_data : std_logic_vector(4*8-1 downto 0); -signal rx_k : std_logic_vector(3 downto 0); -signal rx_error : std_logic_vector(3 downto 0); + RESET : in std_logic; + CLEAR : in std_logic; -signal rst_n : std_logic; -signal rx_serdes_rst : std_logic_vector(3 downto 0); -signal tx_serdes_rst : std_logic_vector(3 downto 0); -signal tx_pcs_rst : std_logic_vector(3 downto 0); -signal rx_pcs_rst : std_logic_vector(3 downto 0); -signal rst_qd : std_logic_vector(3 downto 0); -signal serdes_rst_qd : std_logic_vector(3 downto 0); + RXN : in std_logic_vector(3 downto 0); + RXP : in std_logic_vector(3 downto 0); + TXN : out std_logic_vector(3 downto 0); + TXP : out std_logic_vector(3 downto 0); -signal rx_los_low : std_logic_vector(3 downto 0); -signal lsm_status : std_logic_vector(3 downto 0); -signal rx_cdr_lol : std_logic_vector(3 downto 0); -signal tx_pll_lol : std_logic; + MEDIA_MED2INT : out med2int_array_t(0 to 3); + MEDIA_INT2MED : in int2med_array_t(0 to 3); -signal sci_ch_i : std_logic_vector(4 downto 0); -signal sci_addr_i : std_logic_vector(5 downto 0); -signal sci_data_in_i : std_logic_vector(7 downto 0); -signal sci_data_out_i : std_logic_vector(7 downto 0); -signal sci_read_i : std_logic; -signal sci_write_i : std_logic; + RX_DLM : out std_logic_vector(3 downto 0) := x"0"; + RX_DLM_WORD : out std_logic_vector(31 downto 0) := (others => '0'); + TX_DLM : in std_logic_vector(3 downto 0) := x"0"; + TX_DLM_WORD : in std_logic_vector(31 downto 0) := (others => '0'); -signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; -signal wa_position_sel : std_logic_vector(3 downto 0); + SD_LOS_IN : in std_logic_vector(3 downto 0); + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -signal stat_rx_control_i : std_logic_vector(4*32-1 downto 0); -signal stat_tx_control_i : std_logic_vector(4*32-1 downto 0); -signal debug_rx_control_i : std_logic_vector(4*32-1 downto 0); -signal debug_tx_control_i : std_logic_vector(4*32-1 downto 0); -signal stat_fsm_reset_i : std_logic_vector(4*32-1 downto 0); -signal debug_med_sync_control_i : std_logic_vector(31 downto 0); + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; -signal stat_med : std_logic_vector(127 downto 0); - -signal gtpowergood_i : std_logic_vector(3 downto 0); -signal tx_ready_i : std_logic; -signal rx_ready_i : std_logic; -signal tx_active_i : std_logic; -signal rx_active_i : std_logic; -signal rx_cdr_stable_i : std_logic; + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; -signal init_done_i : std_logic; +architecture med_xcku_sfp_sync_4_arch of med_xcku_sfp_sync_4 is + signal usrclk_full : std_logic; + signal usrclk_half : std_logic; + + signal txdata : std_logic_vector(31 downto 0); + signal txcharisk : std_logic_vector(3 downto 0); + signal txchardispmode : std_logic_vector(3 downto 0); + signal rxdata : std_logic_vector(31 downto 0); + signal rxcharisk : std_logic_vector(3 downto 0); + signal rxnotintable : std_logic_vector(3 downto 0); + + signal rxpmareset : std_logic_vector(3 downto 0); + signal txpcsreset : std_logic_vector(3 downto 0); + signal rxpcsreset : std_logic_vector(3 downto 0); + signal quad_rst : std_logic_vector(3 downto 0); + signal reset_all : std_logic; + + signal rx_los : std_logic_vector(3 downto 0); + signal rx_cdr_lol : std_logic_vector(3 downto 0); + signal tx_lol : std_logic; + + signal reset_tx_done : std_logic; + signal rxpmaresetdone : std_logic_vector(3 downto 0); + signal txpmaresetdone : std_logic_vector(3 downto 0); + + signal debug_rx_control_i : std_logic_vector(127 downto 0); + signal debug_tx_control_i : std_logic_vector(127 downto 0); begin + SD_TXDIS_OUT <= (others =>'0'); + + reset_all <= quad_rst(0) or quad_rst(1) or quad_rst(2) or quad_rst(3); + + THE_SERDES : entity work.gth_xcku_quad_x0y2_top + port map ( + CLK_100 => SYSCLK, + GTREFCLK => GTREFCLK, + USRCLK_FULL => usrclk_full, + USRCLK_HALF => usrclk_half, + RESET_ALL => reset_all, + RXPMARESET => rxpmareset, + RXPCSRESET => rxpcsreset, + TXPMARESET => "0000", + TXPCSRESET => txpcsreset, + USRCLK_LOCKED => open, + INIT_DONE => open, + RXRESETDONE => open, + TXRESETDONE => open, + RXPMARESETDONE => rxpmaresetdone, + TXPMARESETDONE => txpmaresetdone, + RXBYTEISALIGNED => open, + RXN => RXN, + RXP => RXP, + TXN => TXN, + TXP => TXP, + TXDATA => txdata, + TXCHARISK => txcharisk, + TXCHARDISPMODE => txchardispmode, + TXCHARDISPVAL => "0000", + RXDATA => rxdata, + RXCHARISK => rxcharisk, + RXCHARISCOMMA => open, + RXNOTINTABLE => rxnotintable, + RXDISPERR => open + ); -clk_200_ref <= CLK_REF_FULL; - -SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready --- SD_TXDIS_OUT <= (others => RESET); -------------------------------------------------- --- Serdes -------------------------------------------------- -THE_GTH_8b10b : entity work.gth_xcku_quad_x0y2_top - port map( - clk_100 => SYSCLK, - clk_200 => CLK_INTERNAL_FULL, - reset_all => RESET, - mgtrefclk0_x0y3_int => SD_REFCLK, - FREECLK => FREECLK, - - ch0_gthrxn_in => SD_RX_N, - ch0_gthrxp_in => SD_RX_P, - ch0_gthtxn_out => SD_TX_N, - ch0_gthtxp_out => SD_TX_P, - - tx_clk => clk_tx_full, - tx_data => tx_data, - tx_k => tx_k, - - rx_clk => clk_rx_full, - rx_data => rx_data, --clk with 200MHz osci - rx_k => rx_k, - - rx_cdr_stable => rx_cdr_stable_i, - tx_pll_reset => '0',--reset_tx_pll_and_datapath_i, - rx_pll_reset => '0',--reset_rx_pll_and_datapath_i, - - tx_ready => tx_ready_i, - rx_ready => rx_ready_i, - - tx_active => tx_active_i, - rx_active => rx_active_i, - gtpowergood => gtpowergood_i, - - init_done => init_done_i, - TX_USRCLK => TX_USRCLK - ); - - tx_serdes_rst <= "0000"; --SD_LOS_IN; --no function - serdes_rst_qd <= "0000"; --included in rst_qd - wa_position_sel <= x"0"; --- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0 --- else wa_position(15 downto 12) when SERDES_NUM = 3; - -gen_control : for i in 0 to 3 generate - gen_used_control : if IS_USED(i) = c_YES generate - THE_MED_CONTROL : entity work.med_sync_control - generic map( - IS_SYNC_SLAVE => IS_SYNC_SLAVE(i), - IS_TX_RESET => 1 - ) - port map( - CLK_SYS => SYSCLK, - CLK_RXI => clk_rx_full, --clk_rx_full, - CLK_RXHALF => '0', - CLK_TXI => clk_tx_full, --clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 - CLK_REF => CLK_INTERNAL_FULL, - RESET => RESET, - CLEAR => CLEAR, - - INIT_DONE => init_done_i, - - TX_ACTIVE => tx_active_i, - RX_ACTIVE => rx_active_i, - - RX_SERDES_RST => open, - TX_SERDES_RST => open, - - MEDIA_MED2INT => MEDIA_MED2INT(i), - MEDIA_INT2MED => MEDIA_INT2MED(i), - - TX_DATA => tx_data(i*8+7 downto i*8), - TX_K => tx_k(i), - RX_DATA => rx_data(i*8+7 downto i*8), - RX_K => rx_k(i), - - TX_DLM_WORD => TX_DLM_WORD(i*8+7 downto i*8), - TX_DLM => TX_DLM(i), - RX_DLM_WORD => RX_DLM_WORD(i*8+7 downto i*8), - RX_DLM => RX_DLM(i), - - SERDES_RX_READY_IN => rx_ready_i, - SERDES_TX_READY_IN => tx_ready_i, - - STAT_TX_CONTROL => stat_tx_control_i(i*32+31 downto i*32), - STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32), - DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32), - DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32), - STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32), - DEBUG_OUT => debug_med_sync_control_i - ); - end generate; - - gen_not_used : if IS_USED(i) = c_NO generate - MEDIA_MED2INT(i).dataready <= '0'; - MEDIA_MED2INT(i).tx_read <= '1'; - MEDIA_MED2INT(i).stat_op <= x"0007"; - end generate; - --- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); --- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); --- STAT_DEBUG(7) <= '0'; --- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); --- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); --- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); --- -- -- STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0); --- -- -- STAT_DEBUG(7 downto 4) <= rx_los_low(0) & lsm_status(0) & rx_cdr_lol(0) & tx_pll_lol; --- STAT_DEBUG(9) <= CLK_REF_FULL; --- STAT_DEBUG(10) <= clk_rx_full; --- STAT_DEBUG(11) <= clk_tx_full; - - - stat_med(i*32+0) <= rst_qd(i); - stat_med(i*32+1) <= rx_pcs_rst(i); - stat_med(i*32+2) <= tx_pcs_rst(i); - stat_med(i*32+3) <= rx_serdes_rst(i); - stat_med(i*32+4) <= tx_pll_lol; - stat_med(i*32+5) <= rx_cdr_lol(i); - stat_med(i*32+6) <= rx_los_low(i); - stat_med(i*32+7) <= rx_ready_i; - stat_med(i*32+8) <= tx_ready_i; - stat_med(i*32+9) <= lsm_status(i); - stat_med(i*32+31 downto i*32+10) <= (others => '0'); -end generate; - -THE_BUS : process begin - wait until rising_edge(SYSCLK); - BUS_TX.unknown <= BUS_RX.read or BUS_RX.write; - BUS_TX.ack <= '0'; -end process; - + tx_lol <= not txpmaresetdone(0); + rx_cdr_lol <= not rxpmaresetdone; + + + gen_control : for i in 0 to 3 generate + gen_used_control : if IS_USED(i) = c_YES generate + THE_MED_CONTROL : entity work.med_sync_control + generic map( + IS_SYNC_SLAVE => IS_SYNC_SLAVE(i), + IS_TX_RESET => 1 + ) + port map( + CLK_SYS => SYSCLK, + CLK_RXI => usrclk_full, + CLK_RXHALF => usrclk_half, + CLK_TXI => usrclk_full, + CLK_REF => CLK_200, + RESET => RESET, + CLEAR => CLEAR, + SFP_LOS => SD_LOS_IN(i), + TX_LOL => tx_lol, + RX_CDR_LOL => rx_cdr_lol(i), + RX_LOS => SD_LOS_IN(i), + WA_POSITION => (others => '0'), + RX_SERDES_RST => rxpmareset(i), + RX_PCS_RST => rxpcsreset(i), + QUAD_RST => quad_rst(i), + TX_PCS_RST => txpcsreset(i), + MEDIA_MED2INT => MEDIA_MED2INT(i), + MEDIA_INT2MED => MEDIA_INT2MED(i), + TX_DATA => txdata(8 * i + 7 downto 8 * i), + TX_K => txcharisk(i), + TX_CD => txchardispmode(i), + RX_DATA => rxdata(8 * i + 7 downto 8 * i), + RX_K => rxcharisk(i), + TX_DLM_WORD => TX_DLM_WORD(8 * i + 7 downto 8 * i), + TX_DLM => TX_DLM(i), + RX_DLM_WORD => RX_DLM_WORD(8 * i + 7 downto 8 * i), + RX_DLM => RX_DLM(i), + STAT_TX_CONTROL => open, + STAT_RX_CONTROL => open, + DEBUG_TX_CONTROL => debug_tx_control_i(32 * i + 31 downto 32 * i), + DEBUG_RX_CONTROL => debug_rx_control_i(32 * i + 31 downto 32 * i), + STAT_RESET => open + ); + end generate; + + gen_not_used : if IS_USED(i) = c_NO generate + MEDIA_MED2INT(i).dataready <= '0'; + MEDIA_MED2INT(i).tx_read <= '1'; + MEDIA_MED2INT(i).stat_op <= x"0007"; + end generate; + end generate; + + THE_BUS: + process is + begin + wait until rising_edge(SYSCLK); + BUS_TX.unknown <= BUS_RX.read or BUS_RX.write; + BUS_TX.ack <= '0'; + end process; + + STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); + STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); end architecture; - diff --git a/media_interfaces/sync/xcku/med_sync_control.vhd b/media_interfaces/sync/xcku/med_sync_control.vhd deleted file mode 100644 index 369e852..0000000 --- a/media_interfaces/sync/xcku/med_sync_control.vhd +++ /dev/null @@ -1,267 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.med_sync_define.all; - -entity med_sync_control is - generic( - IS_SYNC_SLAVE : integer := 1; - IS_TX_RESET : integer := 1 - ); - port( - CLK_SYS : in std_logic; - CLK_RXI : in std_logic; - CLK_RXHALF : in std_logic; - CLK_TXI : in std_logic; - CLK_REF : in std_logic; - RESET : in std_logic; - CLEAR : in std_logic; - - INIT_DONE : in std_logic; - - TX_ACTIVE : in std_logic; - RX_ACTIVE : in std_logic; - - RX_SERDES_RST : out std_logic; - TX_SERDES_RST : out std_logic; - - MEDIA_MED2INT : out MED2INT; - MEDIA_INT2MED : in INT2MED; - - TX_DATA : out std_logic_vector(7 downto 0); - TX_K : out std_logic; - TX_CD : out std_logic; - RX_DATA : in std_logic_vector(7 downto 0); - RX_K : in std_logic; - - TX_DLM_WORD : in std_logic_vector(7 downto 0); - TX_DLM : in std_logic; - RX_DLM_WORD : out std_logic_vector(7 downto 0); - RX_DLM : out std_logic; - - SERDES_RX_READY_IN : in std_logic := '1'; - SERDES_TX_READY_IN : in std_logic := '1'; - - STAT_TX_CONTROL : out std_logic_vector(31 downto 0); - STAT_RX_CONTROL : out std_logic_vector(31 downto 0); - DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); - DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); - STAT_RESET : out std_logic_vector(31 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); -end entity; - - -architecture med_sync_control_arch of med_sync_control is - -signal rx_fsm_state : std_logic_vector(3 downto 0); -signal tx_fsm_state : std_logic_vector(3 downto 0); -signal wa_position_rx : std_logic_vector(3 downto 0); -signal start_timer : unsigned(21 downto 0) := (others => '0'); - -signal request_retr_i : std_logic; -signal start_retr_i : std_logic; -signal request_retr_position_i : std_logic_vector(7 downto 0); -signal start_retr_position_i : std_logic_vector(7 downto 0); -signal rx_dlm_i : std_logic; - -signal led_ok : std_logic; -signal led_dlm, last_led_dlm : std_logic; -signal led_rx, last_led_rx : std_logic; -signal led_tx, last_led_tx : std_logic; -signal timer : unsigned(20 downto 0); -signal sd_los_i : std_logic; - -signal rx_allow : std_logic; -signal tx_allow : std_logic; -signal got_link_ready_i : std_logic; -signal make_link_reset_i : std_logic; -signal send_link_reset_i : std_logic; -signal make_link_reset_real_i : std_logic := '0'; -signal make_link_reset_sys_i : std_logic := '0'; -signal send_link_reset_real_i : std_logic := '0'; -signal send_link_reset_sys_i : std_logic := '0'; - -signal reset_i, rst_n, rst_n_tx : std_logic; -signal media_med2int_i : MED2INT; -signal finished_reset_rx, finished_reset_rx_q : std_logic; -signal finished_reset_tx, finished_reset_tx_q : std_logic; -signal TX_DATA_i : std_logic_vector(7 downto 0); -signal TX_K_i : std_logic; - -attribute MARK_DEBUG : string; -attribute MARK_DEBUG of CLK_SYS : signal is "TRUE"; -attribute MARK_DEBUG of media_med2int_i : signal is "TRUE"; -attribute MARK_DEBUG of MEDIA_INT2MED : signal is "TRUE"; -attribute MARK_DEBUG of RX_DATA : signal is "TRUE"; -attribute KEEP : string; -attribute KEEP of CLK_SYS : signal is "TRUE"; -attribute KEEP of media_med2int_i : signal is "TRUE"; -attribute KEEP of MEDIA_INT2MED : signal is "TRUE"; -attribute KEEP of RX_DATA : signal is "TRUE"; - -begin - -media_med2int_i.clk_half <= CLK_RXHALF; -media_med2int_i.clk_full <= CLK_RXI; - -TX_DATA <= TX_DATA_i; -TX_K <= TX_K_i; - - --- -finished_reset_tx <= INIT_DONE; -finished_reset_rx <= INIT_DONE; -reset_i <= RESET; - -------------------------------------------------- --- TX Data -------------------------------------------------- -THE_TX : tx_control - port map( - CLK_200 => CLK_REF, - CLK_100 => CLK_SYS, - RESET_IN => reset_i, - - TX_DATA_IN => MEDIA_INT2MED.data, - TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num, - TX_WRITE_IN => MEDIA_INT2MED.dataready, - TX_READ_OUT => media_med2int_i.tx_read, - - TX_DATA_OUT => TX_DATA_i, - TX_K_OUT => TX_K_i, - TX_CD_OUT => TX_CD, - - REQUEST_RETRANSMIT_IN => request_retr_i, --TODO - REQUEST_POSITION_IN => request_retr_position_i, --TODO - - START_RETRANSMIT_IN => start_retr_i, --TODO - START_POSITION_IN => start_retr_position_i, --TODO - - SEND_DLM => TX_DLM, - SEND_DLM_WORD => TX_DLM_WORD, - - SEND_LINK_RESET_IN => MEDIA_INT2MED.ctrl_op(15), - TX_ALLOW_IN => TX_ACTIVE, - RX_ALLOW_IN => RX_ACTIVE, - - DEBUG_OUT => DEBUG_TX_CONTROL, - STAT_REG_OUT => STAT_TX_CONTROL - ); - - -------------------------------------------------- --- RX Data -------------------------------------------------- -THE_RX_CONTROL : rx_control - port map( - CLK_200 => CLK_REF, --200MHz intern; used in fifo of 8b10b - CLK_100 => CLK_SYS, - RESET_IN => reset_i, - - RX_DATA_OUT => media_med2int_i.data, - RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, - RX_WRITE_OUT => media_med2int_i.dataready, --- RX_READ_IN => '1', - - RX_DATA_IN => RX_DATA, - RX_K_IN => RX_K, - - REQUEST_RETRANSMIT_OUT => request_retr_i, - REQUEST_POSITION_OUT => request_retr_position_i, - - START_RETRANSMIT_OUT => start_retr_i, - START_POSITION_OUT => start_retr_position_i, - - --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM - RX_DLM => rx_dlm_i, - RX_DLM_WORD => RX_DLM_WORD, - - SEND_LINK_RESET_OUT => send_link_reset_i, - MAKE_RESET_OUT => make_link_reset_sys_i, - RX_ALLOW_IN => RX_ACTIVE, - RX_RESET_FINISHED => finished_reset_rx, - GOT_LINK_READY => got_link_ready_i, - - DEBUG_OUT => DEBUG_RX_CONTROL, - STAT_REG_OUT => STAT_RX_CONTROL - ); - -RX_DLM <= rx_dlm_i; -MEDIA_MED2INT <= media_med2int_i; - -------------------------------------------------- --- Generate LED signals -------------------------------------------------- -led_ok <= TX_ACTIVE and RX_ACTIVE when rising_edge(CLK_SYS); -led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); --- led_tx <= '1' when DEBUG_TX_CONTROL(13 downto 10) = x"c" else '0'; -- -led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_i) and not timer(20) when rising_edge(CLK_SYS); -led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(CLK_SYS); --- led_dlm <= '1' when DEBUG_RX_CONTROL(3 downto 0) = x"f" else '0'; - -ROC_TIMER : process begin - wait until rising_edge(CLK_SYS); - timer <= timer + 1 ; - if timer(20) = '1' then - timer <= (others => '0'); - last_led_rx <= led_rx ; - last_led_tx <= led_tx; - last_led_dlm <= led_dlm; - end if; -end process; - -------------------------------------------------- --- Status signals -------------------------------------------------- - -STAT_RESET(3 downto 0) <= rx_fsm_state; -STAT_RESET(7 downto 4) <= tx_fsm_state; -STAT_RESET(8) <= TX_ACTIVE; -STAT_RESET(9) <= RX_ACTIVE; -STAT_RESET(15 downto 10) <= (others => '0'); -STAT_RESET(16) <= '0'; -STAT_RESET(17) <= '0'; -STAT_RESET(18) <= '0';--QUAD_RST; --RX_PCS_RST; -STAT_RESET(19) <= '0';--TX_PCS_RST; -STAT_RESET(20) <= '0'; -STAT_RESET(21) <= rst_n; -STAT_RESET(22) <= rst_n_tx; -STAT_RESET(30 downto 23) <= (others => '0'); -STAT_RESET(31) <= start_timer(start_timer'left); - - -gen_link_reset : if IS_SYNC_SLAVE = 1 generate - link_reset_send : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS, - D_IN(0) => send_link_reset_i, - D_OUT(0) => send_link_reset_sys_i); -end generate; - -make_link_reset_real_i <= make_link_reset_sys_i or sd_los_i when IS_SYNC_SLAVE = 1 - else '0'; -send_link_reset_real_i <= send_link_reset_sys_i when IS_SYNC_SLAVE = 1 - else '0'; - -sd_los_i <= '0';--SFP_LOS when rising_edge(CLK_SYS); - -media_med2int_i.stat_op(15) <= send_link_reset_real_i when rising_edge(CLK_SYS); -media_med2int_i.stat_op(14) <= '0'; -media_med2int_i.stat_op(13) <= make_link_reset_real_i when rising_edge(CLK_SYS); --make trbnet reset -media_med2int_i.stat_op(12) <= led_dlm when rising_edge(CLK_SYS); -- or last_led_dlm; -media_med2int_i.stat_op(11) <= led_tx; -- or last_led_tx; -media_med2int_i.stat_op(10) <= led_rx or last_led_rx; -media_med2int_i.stat_op(9) <= TX_ACTIVE; --led_ok -media_med2int_i.stat_op(8 downto 5) <= (others => '0'); -media_med2int_i.stat_op(4) <= RX_ACTIVE; -media_med2int_i.stat_op(3 downto 0) <= x"0" when RX_ACTIVE = '1' and TX_ACTIVE = '1' else x"7"; - -DEBUG_OUT(0) <= TX_ACTIVE; -DEBUG_OUT(1) <= RX_ACTIVE; -DEBUG_OUT(2) <= sd_los_i; -DEBUG_OUT(3) <= '0'; --DEBUG_RX_CONTROL(4); - -end architecture; diff --git a/media_interfaces/sync/xcku/rx_control.vhd b/media_interfaces/sync/xcku/rx_control.vhd deleted file mode 100644 index 94e0b90..0000000 --- a/media_interfaces/sync/xcku/rx_control.vhd +++ /dev/null @@ -1,437 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.med_sync_define.all; - -entity rx_control is - generic( - IDLE_WORD_CKECK_LENGTH : unsigned(9 downto 0) := b"00_0110_0100"; --100 - RESET_WORD_CKECK_LENGTH : unsigned(9 downto 0) := b"00_0010_0000"; --32 - IS_SIMULATION : std_logic := '0' - ); - port( - CLK_200 : in std_logic; - CLK_100 : in std_logic; - RESET_IN : in std_logic; - ---clk_sys signals - RX_DATA_OUT : out std_logic_vector(15 downto 0); - RX_PACKET_NUMBER_OUT : out std_logic_vector(2 downto 0); - RX_WRITE_OUT : out std_logic; - --- clk_rx signals - RX_DATA_IN : in std_logic_vector( 7 downto 0); - RX_K_IN : in std_logic; - - REQUEST_RETRANSMIT_OUT : out std_logic := '0'; - REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); - - START_RETRANSMIT_OUT : out std_logic := '0'; - START_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); - - --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector( 7 downto 0) := (others => '0'); - ---other signals - SEND_LINK_RESET_OUT : out std_logic := '0'; --clk_rx - MAKE_RESET_OUT : out std_logic := '0'; --clk_rx - RX_ALLOW_IN : in std_logic := '0'; --clk_sys - RX_RESET_FINISHED : in std_logic := '0'; --clk_rx - GOT_LINK_READY : out std_logic := '0'; --clk_rx - - DEBUG_OUT : out std_logic_vector(31 downto 0); - STAT_REG_OUT : out std_logic_vector(31 downto 0) - ); -end entity; - - -architecture rx_control_arch of rx_control is - -signal reset_i : std_logic; -type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR); -signal rx_state : rx_state_t; -signal rx_state_bits : std_logic_vector(3 downto 0); -signal rx_packet_num : std_logic_vector(2 downto 0); -signal buf_rx_write_out : std_logic := '0'; - -signal rx_data : std_logic_vector(17 downto 0); -signal ct_fifo_write : std_logic := '0'; -signal ct_fifo_read : std_logic := '0'; -signal ct_fifo_reset : std_logic := '0'; -signal ct_fifo_data_out : std_logic_vector(17 downto 0); -signal ct_fifo_empty : std_logic; -signal ct_fifo_full : std_logic; -signal ct_fifo_afull : std_logic; -signal last_ct_fifo_empty : std_logic; -signal last_ct_fifo_read : std_logic; - -signal idle_hist_i : std_logic_vector(3 downto 0) := x"0"; -signal got_link_ready_i : std_logic := '0'; -signal start_retr_i : std_logic; -signal start_retr_pos_i : std_logic_vector(7 downto 0); -signal rx_dlm_i : std_logic; -signal rx_dlm_word_i : std_logic_vector(7 downto 0); - -signal send_link_reset_i : std_logic; -signal make_reset_i : std_logic; -signal next_sop : std_logic; - -signal reg_rx_data_in : std_logic_vector(7 downto 0); -signal reg_rx_k_in : std_logic; - -signal reset_cnt : unsigned(11 downto 0); - -signal byte_align : std_logic := '0'; -signal last_reg_k_in : std_logic; -signal last_reg_rx_data_in : std_logic_vector(7 downto 0); -signal idle_wrd_cnt : unsigned(9 downto 0); - -signal last_rx_data : std_logic_vector(7 downto 0); -signal tn_reset_wrd_cnt : unsigned(9 downto 0); -signal make_reset_trbnet_i : std_logic; -signal make_reset_trbnet_sync : std_logic; -signal last_make_reset_trbnet_i : std_logic; -signal trbnetReset, trbnetReset_long : std_logic; - -attribute MARK_DEBUG : string; -attribute MARK_DEBUG of CLK_200 : signal is "TRUE"; -attribute MARK_DEBUG of ct_fifo_write : signal is "TRUE"; -attribute MARK_DEBUG of rx_data : signal is "TRUE"; -attribute MARK_DEBUG of rx_state_bits : signal is "TRUE"; -attribute MARK_DEBUG of reg_rx_data_in : signal is "TRUE"; -attribute MARK_DEBUG of reg_rx_k_in : signal is "TRUE"; -attribute MARK_DEBUG of reset_i : signal is "TRUE"; -attribute MARK_DEBUG of rx_packet_num : signal is "TRUE"; -attribute MARK_DEBUG of trbnetReset : signal is "TRUE"; -attribute MARK_DEBUG of make_reset_trbnet_i : signal is "TRUE"; -attribute MARK_DEBUG of tn_reset_wrd_cnt : signal is "TRUE"; -attribute KEEP : string; -attribute KEEP of CLK_200 : signal is "TRUE"; -attribute KEEP of ct_fifo_write : signal is "TRUE"; -attribute KEEP of rx_data : signal is "TRUE"; -attribute KEEP of rx_state_bits : signal is "TRUE"; -attribute KEEP of reg_rx_data_in : signal is "TRUE"; -attribute KEEP of reg_rx_k_in : signal is "TRUE"; -attribute KEEP of reset_i : signal is "TRUE"; -attribute KEEP of rx_packet_num : signal is "TRUE"; -attribute KEEP of trbnetReset : signal is "TRUE"; -attribute KEEP of make_reset_trbnet_i : signal is "TRUE"; -attribute KEEP of tn_reset_wrd_cnt : signal is "TRUE"; - -begin - ----------------------------------------------------------------------- --- Data to Endpoint ----------------------------------------------------------------------- -reset_i <= RESET_IN; - -ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; -- when rising_edge(CLK_100); -buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty when rising_edge(CLK_100); - -RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; -RX_WRITE_OUT <= buf_rx_write_out; -RX_PACKET_NUMBER_OUT <= rx_packet_num; - -last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100); -last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100); - -process begin - wait until rising_edge(CLK_100); - if RX_ALLOW_IN = '0' then - rx_packet_num <= "100"; - elsif (byte_align = '1') then - rx_packet_num <= "100"; - elsif buf_rx_write_out = '1' then - if rx_packet_num = "100" then - rx_packet_num <= "000"; - else - rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1); - end if; - end if; -end process; - ----------------------------------------------------------------------- --- Clock Domain Transfer ----------------------------------------------------------------------- -THE_CT_FIFO : entity work.fifo_18x16_dualport_oreg - port map( - Data => rx_data, - WrClock => CLK_200, - RdClock => CLK_100, - WrEn => ct_fifo_write, - RdEn => ct_fifo_read, - Reset => ct_fifo_reset, - RPReset => ct_fifo_reset, - Q(17 downto 0) => ct_fifo_data_out, - Empty => ct_fifo_empty, - Full => ct_fifo_full, - AlmostFull => ct_fifo_afull - ); - -ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200); - - ----------------------------------------------------------------------- --- Read incoming data ----------------------------------------------------------------------- -PROC_RX_FSM : process begin - wait until rising_edge(CLK_200); - ct_fifo_write <= '0'; - start_retr_i <= '0'; - rx_dlm_i <= '0'; - idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0); - idle_hist_i(0) <= got_link_ready_i; - byte_align <= '0'; - --newly added - make_reset_i <= '0'; - - case rx_state is - when SLEEP => - rx_state_bits <= x"1"; - got_link_ready_i <= '0'; - make_reset_i <= '0'; - rx_data(7 downto 0) <= reg_rx_data_in; - if reg_rx_k_in = '1' and reg_rx_data_in = x"BC" then - rx_state <= WAIT_1; - end if; - - when WAIT_1 => - rx_state <= FIRST; - - when FIRST => - rx_state_bits <= x"2"; - rx_data(7 downto 0) <= reg_rx_data_in; - if byte_align = '0' then - if reg_rx_k_in = '1' then - case reg_rx_data_in is - when K_IDLE => - rx_state <= GET_IDLE; - when K_RST => - rx_state <= MAKE_RESET; - reset_cnt <= x"000"; - when K_DLM => - rx_state <= GET_DLM; - when K_REQ => - rx_state <= START_RETR; - when others => null; - end case; - else - rx_state <= GET_DATA; - end if; - end if; - - when GET_IDLE => - rx_state_bits <= x"3"; - rx_state <= FIRST; - next_sop <= '1'; - if reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE1 then - idle_hist_i(0) <= '1'; - got_link_ready_i <= got_link_ready_i or (idle_hist_i(1) and idle_hist_i(3)); - elsif reg_rx_k_in = '1' then - rx_state <= FIRST; -- SLEEP; - end if; - - when GET_DATA => - rx_state_bits <= x"4"; - if reg_rx_k_in = '0' then - next_sop <= '0'; - rx_data(15 downto 8)<= reg_rx_data_in; - rx_data(16) <= next_sop; - rx_data(17) <= '0'; - ct_fifo_write <= '1'; - rx_state <= FIRST; - elsif reg_rx_k_in = '1' and reg_rx_data_in = K_IDLE then - --word is missaligned - byte_align <= '1'; - rx_state <= FIRST; - else - rx_state <= FIRST; -- SLEEP; - end if; - - when GET_DLM => - rx_state_bits <= x"5"; - rx_dlm_i <= '1'; - rx_dlm_word_i <= reg_rx_data_in; - rx_state <= FIRST; - - when START_RETR => - rx_state_bits <= x"6"; - start_retr_i <= '1'; - start_retr_pos_i <= reg_rx_data_in; - rx_state <= FIRST; - - when MAKE_RESET => - rx_state_bits <= x"F"; - if reg_rx_k_in = '1' and reg_rx_data_in = K_RST then - send_link_reset_i <= '1'; - make_reset_i <= '0'; - got_link_ready_i <= '0'; - if reset_cnt <= x"3ff" then - reset_cnt <= reset_cnt + 1; --- else --- make_reset_i <= '1'; - end if; - elsif reset_cnt > x"3ff" then -- or reset_cnt < x"40" - send_link_reset_i <= '0'; - make_reset_i <= '1'; - rx_state <= SLEEP; - else - if reset_cnt <= x"3ff" then - reset_cnt <= reset_cnt + 1; - end if; - send_link_reset_i <= '1'; - end if; - - end case; - - if reset_i = '1' or RX_RESET_FINISHED = '0' or (idle_wrd_cnt < IDLE_WORD_CKECK_LENGTH) then - rx_state <= SLEEP; - if rx_state = MAKE_RESET then - make_reset_i <= '1'; - else - make_reset_i <= '0'; - end if; - send_link_reset_i <= '0'; - end if; - - --fixing trbnetReset packetnumber misalignment - if trbnetReset_long = '1' then - rx_state <= SLEEP; - make_reset_i <= '1';--for debugging - end if; - -end process; - --- link_reset_pulse : pulse_sync port map( CLK_A_IN => CLK_100, CLK_B_IN => CLK_200, RESET_A_IN => '0', --- PULSE_A_IN => make_reset_trbnet_i, --- PULSE_B_OUT => make_reset_trbnet_sync, RESET_B_IN => '0'); - - -THE_IDLE_PROC : process begin -wait until rising_edge(CLK_200); --- Handles random data on RX line after reset. First right bc50 comes in, then random stuff, then again correct behavior. - last_reg_k_in <= reg_rx_k_in; - last_reg_rx_data_in <= reg_rx_data_in; - if reset_i = '1' then - idle_wrd_cnt <= (others=> '0'); - else - --check 50bc order - if idle_wrd_cnt < IDLE_WORD_CKECK_LENGTH then - - if (((reg_rx_k_in = '1') and (reg_rx_data_in = x"BC")) and ((last_reg_k_in = '0') and (last_reg_rx_data_in = x"50"))) then - idle_wrd_cnt <= idle_wrd_cnt + 1; - elsif (((reg_rx_k_in = '0') and (reg_rx_data_in = x"50")) and ((last_reg_k_in = '1') and (last_reg_rx_data_in = x"BC"))) then - idle_wrd_cnt <= idle_wrd_cnt + 1; - else - idle_wrd_cnt <= (others=> '0'); - end if; - - end if; - end if; -end process; - - -THE_TrbNet_RESET_PROC : process begin -wait until rising_edge(CLK_200); - last_rx_data <= reg_rx_data_in; - if reset_i = '1' then - tn_reset_wrd_cnt <= (others=> '0'); - make_reset_trbnet_i <= '0'; - else - --check 50bc order - if ((reg_rx_data_in = x"FE") and (last_rx_data = x"FE")) then - tn_reset_wrd_cnt <= tn_reset_wrd_cnt + 1; - else - tn_reset_wrd_cnt <= (others=> '0'); - end if; - - if (tn_reset_wrd_cnt >= RESET_WORD_CKECK_LENGTH) then --TODO: sync. Clocks - make_reset_trbnet_i <= '1'; - else - make_reset_trbnet_i <= '0'; - end if; - - last_make_reset_trbnet_i <= make_reset_trbnet_i; - trbnetReset <= '0'; - if make_reset_trbnet_i = '0' and last_make_reset_trbnet_i = '1'then --end of x"FEFE" chain - --make_reset_i <= '0';--for debugging - trbnetReset <= '1'; - end if; - end if; -end process; - -THE_TrbNet_RESET_PROC_strobe : process - variable loc_cnt : unsigned(3 downto 0); -begin -wait until rising_edge(CLK_200); - trbnetReset_long <= '0'; - if loc_cnt > 0 then - loc_cnt := loc_cnt + 1; - trbnetReset_long <= '1'; - end if; - - if trbnetReset = '1' then - loc_cnt := x"1"; - end if; - -end process; - -reg_rx_data_in <= RX_DATA_IN when rising_edge(CLK_200); -reg_rx_k_in <= RX_K_IN when rising_edge(CLK_200); - - ----------------------------------------------------------------------- --- Signals out ----------------------------------------------------------------------- -GOT_LINK_READY <= got_link_ready_i; - -START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200); -START_POSITION_OUT <= start_retr_pos_i when rising_edge(CLK_200); - -RX_DLM <= rx_dlm_i when rising_edge(CLK_200); -RX_DLM_WORD <= rx_dlm_word_i when rising_edge(CLK_200); - -REQUEST_RETRANSMIT_OUT <= '0'; --TODO: check incoming data -REQUEST_POSITION_OUT <= x"00"; --TODO: check incoming data - -SEND_LINK_RESET_OUT <= send_link_reset_i when rising_edge(CLK_200); -MAKE_RESET_OUT <= make_reset_i when rising_edge(CLK_200); - - ----------------------------------------------------------------------- --- Debug and Status ----------------------------------------------------------------------- -STAT_REG_OUT(3 downto 0) <= rx_state_bits; -STAT_REG_OUT(4) <= got_link_ready_i; -STAT_REG_OUT(5) <= ct_fifo_afull; -STAT_REG_OUT(6) <= ct_fifo_empty; -STAT_REG_OUT(7) <= ct_fifo_write; -STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(clk_100); --rx_data(7 downto 0); -STAT_REG_OUT(16) <= rx_data(16); -STAT_REG_OUT(17) <= '0'; -STAT_REG_OUT(31 downto 18) <= (others => '0'); - - -DEBUG_OUT(3 downto 0) <= rx_state_bits; -DEBUG_OUT(4) <= got_link_ready_i; -DEBUG_OUT(5) <= ct_fifo_afull; -DEBUG_OUT(6) <= ct_fifo_empty; -DEBUG_OUT(7) <= ct_fifo_write; -DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0); -DEBUG_OUT(16) <= reg_rx_k_in; -DEBUG_OUT(17) <= make_reset_i; -DEBUG_OUT(18) <= send_link_reset_i; -DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0'; ---DEBUG_OUT(16) <= rx_data(16); -DEBUG_OUT(31 downto 20) <= (others => '0'); --- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0); --- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0); - - - -end architecture; diff --git a/media_interfaces/sync/xcku/tx_control.vhd b/media_interfaces/sync/xcku/tx_control.vhd deleted file mode 100644 index 3fa06d0..0000000 --- a/media_interfaces/sync/xcku/tx_control.vhd +++ /dev/null @@ -1,585 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.med_sync_define.all; - -entity tx_control is - port( - CLK_200 : in std_logic; - CLK_100 : in std_logic; - RESET_IN : in std_logic; - - TX_DATA_IN : in std_logic_vector(15 downto 0); - TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); - TX_WRITE_IN : in std_logic; - TX_READ_OUT : out std_logic; - - TX_DATA_OUT : out std_logic_vector( 7 downto 0); - TX_K_OUT : out std_logic; - TX_CD_OUT : out std_logic; - - REQUEST_RETRANSMIT_IN : in std_logic := '0'; - REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); - - START_RETRANSMIT_IN : in std_logic := '0'; - START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); - --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM - SEND_DLM : in std_logic := '0'; - SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); - - SEND_LINK_RESET_IN : in std_logic := '0'; - TX_ALLOW_IN : in std_logic := '0'; - RX_ALLOW_IN : in std_logic := '0'; - - DEBUG_OUT : out std_logic_vector(31 downto 0); - STAT_REG_OUT : out std_logic_vector(31 downto 0) - ); -end entity; - - - -architecture arch of tx_control is - - - type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H, - SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H, - SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10 - signal current_state : state_t; - signal state_bits : std_logic_vector(3 downto 0); - - type ram_t is array(0 to 255) of std_logic_vector(17 downto 0); - signal ram : ram_t; - - signal ram_write : std_logic := '0'; - signal ram_write_addr : unsigned(7 downto 0) := (others => '0'); - signal last_ram_write_addr : unsigned(7 downto 0) := (others => '0'); - signal ram_read : std_logic := '0'; - signal ram_read_addr : unsigned(7 downto 0) := (others => '0'); - signal ram_dout : std_logic_vector(17 downto 0); - signal next_ram_dout : std_logic_vector(17 downto 0); - signal ram_fill_level : unsigned(7 downto 0); - signal ram_empty : std_logic; - signal ram_afull : std_logic; - - signal request_position_q : std_logic_vector( 7 downto 0); - signal restart_position_q : std_logic_vector( 7 downto 0); - signal request_position_i : std_logic_vector( 7 downto 0); - signal restart_position_i : std_logic_vector( 7 downto 0); - signal make_request_i : std_logic; - signal make_restart_i : std_logic; - signal load_read_pointer_i : std_logic; - signal send_dlm_in_i : std_logic; - signal send_dlm_i : std_logic; - signal start_retransmit_i : std_logic; - signal request_retransmit_i : std_logic; - - signal buf_tx_read_out : std_logic; - signal tx_data_200 : std_logic_vector(17 downto 0); - signal tx_allow_qtx : std_logic; - signal rx_allow_qtx : std_logic; - signal tx_allow_q : std_logic; - signal send_link_reset_qtx : std_logic; - signal ct_fifo_empty : std_logic; - signal ct_fifo_write : std_logic := '0'; - signal ct_fifo_read : std_logic := '0'; - signal ct_fifo_full : std_logic; - signal ct_fifo_afull : std_logic; - signal ct_fifo_reset : std_logic; - signal last_ct_fifo_empty : std_logic; - signal last_ct_fifo_read : std_logic; - signal debug_sending_dlm : std_logic; - - -- gk 05.10.10 - signal save_sop : std_logic; - signal save_eop : std_logic; - signal load_sop : std_logic; - signal load_eop : std_logic; - signal crc_reset : std_logic; - signal crc_q : std_logic_vector(7 downto 0); - signal crc_en : std_logic; - signal crc_data : std_logic_vector(7 downto 0); - signal first_idle : std_logic; - signal toggle_idle : std_logic; - - attribute MARK_DEBUG : string; - attribute MARK_DEBUG of CLK_100 : signal is "TRUE"; - attribute MARK_DEBUG of TX_DATA_IN : signal is "TRUE"; - attribute MARK_DEBUG of TX_PACKET_NUMBER_IN : signal is "TRUE"; - attribute MARK_DEBUG of TX_WRITE_IN : signal is "TRUE"; - attribute MARK_DEBUG of stat_reg_out : signal is "TRUE"; - attribute MARK_DEBUG of CLK_200 : signal is "TRUE"; - attribute MARK_DEBUG of TX_DATA_OUT : signal is "TRUE"; - attribute MARK_DEBUG of TX_K_OUT : signal is "TRUE"; - attribute MARK_DEBUG of state_bits : signal is "TRUE"; - attribute MARK_DEBUG of debug_out : signal is "TRUE"; - attribute KEEP : string; - attribute KEEP of CLK_100 : signal is "TRUE"; - attribute KEEP of TX_DATA_IN : signal is "TRUE"; - attribute KEEP of TX_PACKET_NUMBER_IN : signal is "TRUE"; - attribute KEEP of TX_WRITE_IN : signal is "TRUE"; - attribute KEEP of stat_reg_out : signal is "TRUE"; - attribute KEEP of CLK_200 : signal is "TRUE"; - attribute KEEP of TX_DATA_OUT : signal is "TRUE"; - attribute KEEP of TX_K_OUT : signal is "TRUE"; - attribute KEEP of state_bits : signal is "TRUE"; - attribute KEEP of debug_out : signal is "TRUE"; -begin - ----------------------------------------------------------------------- --- Clock Domain Transfer ----------------------------------------------------------------------- --- gk 05.10.10 - THE_CT_FIFO : entity work.fifo_18x16_dualport_oreg - port map( - Data(15 downto 0) => TX_DATA_IN, - Data(16) => save_sop, - Data(17) => save_eop, - WrClock => CLK_100, - RdClock => CLK_200, - WrEn => ct_fifo_write, - RdEn => ct_fifo_read, - Reset => ct_fifo_reset, - RPReset => ct_fifo_reset, - Q(17 downto 0) => tx_data_200, - Empty => ct_fifo_empty, - Full => ct_fifo_full, - AlmostFull => ct_fifo_afull - ); - - THE_RD_PROC : process(CLK_100) - begin - if rising_edge(CLK_100) then - buf_tx_read_out <= tx_allow_q and not ct_fifo_afull ; - end if; - end process; - - ct_fifo_reset <= not tx_allow_qtx; - TX_READ_OUT <= buf_tx_read_out; - - ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN; - ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty; - - last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_200); - last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_200); - - save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0'; - save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; - ----------------------------------------------------------------------- --- RAM ----------------------------------------------------------------------- - - - THE_RAM_WR_PROC : process(CLK_200) - begin --- if RESET_IN = '1' then --- ram_write <= '0'; --- els - if rising_edge(CLK_200) then - ram_write <= last_ct_fifo_read and not last_ct_fifo_empty; - end if; - end process; - ---RAM - THE_RAM_PROC : process(CLK_200) - begin - if rising_edge(CLK_200) then - if ram_write = '1' then - ram((to_integer(ram_write_addr))) <= tx_data_200; - end if; - next_ram_dout <= ram(to_integer(ram_read_addr)); - ram_dout <= next_ram_dout; - end if; - end process; - ---RAM read pointer - THE_READ_CNT : process(CLK_200) - begin --- if RESET_IN = '1' then --- ram_read_addr <= (others => '0'); --- els - if rising_edge(CLK_200) then - if tx_allow_qtx = '0' then - ram_read_addr <= (others => '0'); - elsif load_read_pointer_i = '1' then - ram_read_addr <= unsigned(restart_position_i); - elsif ram_read = '1' then - ram_read_addr <= ram_read_addr + to_unsigned(1,1); - end if; - end if; - end process; - ---RAM write pointer - THE_WRITE_CNT : process(CLK_200) - begin --- if RESET_IN = '1' then --- ram_write_addr <= (others => '0'); --- els - if rising_edge(CLK_200) then - if tx_allow_qtx = '0' then - ram_write_addr <= (others => '0'); - elsif ram_write = '1' then - ram_write_addr <= ram_write_addr + to_unsigned(1,1); - end if; - end if; - end process; - - ---RAM fill level counter - THE_FILL_CNT : process(CLK_200) - begin --- if RESET_IN = '1' then --- ram_fill_level <= (others => '0'); --- els - if rising_edge(CLK_200) then - if tx_allow_qtx = '0' then - ram_fill_level <= (others => '0'); - else - ram_fill_level <= last_ram_write_addr - ram_read_addr; - end if; - end if; - end process; - - ---RAM empty --- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN; - ram_empty <= '1' when (last_ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0'; - ram_afull <= '1' when ram_fill_level >= 4 else '0'; - - last_ram_write_addr <= ram_write_addr when rising_edge(CLK_200); - ----------------------------------------------------------------------- --- TX control state machine ----------------------------------------------------------------------- - - THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN) - begin - if rising_edge(CLK_200) then --- ram_read <= '0'; - TX_K_OUT <= '0'; - TX_CD_OUT <= '0'; - debug_sending_dlm <= '0'; - first_idle <= '1'; - case current_state is - when SEND_IDLE_L => - TX_DATA_OUT <= K_IDLE; - TX_K_OUT <= '1'; - current_state <= SEND_IDLE_H; - first_idle <= first_idle; - - when SEND_IDLE_H => - if rx_allow_qtx = '1' or toggle_idle = '1' then - TX_DATA_OUT <= D_IDLE1; - toggle_idle <= rx_allow_qtx; - else - TX_DATA_OUT <= D_IDLE0; - toggle_idle <= '1'; - end if; - TX_CD_OUT <= first_idle; - first_idle <= '0'; - - when SEND_DATA_L => - TX_DATA_OUT <= ram_dout(7 downto 0); - load_sop <= ram_dout(16); - load_eop <= ram_dout(17); - current_state <= SEND_DATA_H; - - when SEND_DATA_H => - TX_DATA_OUT <= ram_dout(15 downto 8); - - when SEND_CHKSUM_L => - TX_DATA_OUT <= K_EOP; - TX_K_OUT <= '1'; - load_sop <= '0'; - load_eop <= '0'; - current_state <= SEND_CHKSUM_H; - - when SEND_CHKSUM_H => - TX_DATA_OUT <= crc_q; - - when SEND_START_L => - TX_DATA_OUT <= K_BGN; - TX_K_OUT <= '1'; - current_state <= SEND_START_H; - - when SEND_START_H => - TX_DATA_OUT <= std_logic_vector(ram_read_addr); - - when SEND_REQUEST_L => - TX_DATA_OUT <= K_REQ; - TX_K_OUT <= '1'; - current_state <= SEND_REQUEST_H; - - when SEND_DLM_L => - TX_DATA_OUT <= K_DLM; - TX_K_OUT <= '1'; - current_state <= SEND_DLM_H; - debug_sending_dlm <= '1'; - - when SEND_DLM_H => - TX_DATA_OUT <= SEND_DLM_WORD; - debug_sending_dlm <= '1'; - - when SEND_REQUEST_H => - TX_DATA_OUT <= request_position_i; - - when SEND_RESET => - TX_DATA_OUT <= K_RST; - TX_K_OUT <= '1'; - if send_link_reset_qtx = '0' then - current_state <= SEND_IDLE_L; - end if; - - when others => - current_state <= SEND_IDLE_L; - end case; - - if current_state = SEND_START_H or - current_state = SEND_IDLE_H or - current_state = SEND_DATA_H or - current_state = SEND_DLM_H or - current_state = SEND_REQUEST_H or - current_state = SEND_CHKSUM_H then - if tx_allow_qtx = '0' then - current_state <= SEND_IDLE_L; - elsif send_link_reset_qtx = '1' then - current_state <= SEND_RESET; - elsif make_request_i = '1' then - current_state <= SEND_REQUEST_L; - elsif make_restart_i = '1' then - current_state <= SEND_START_L; - elsif send_dlm_i = '1' then - current_state <= SEND_DLM_L; --- elsif (load_eop = '1') then --- current_state <= SEND_CHKSUM_L; - elsif ram_empty = '0' then --- ram_read <= '1'; - current_state <= SEND_DATA_L; - else - current_state <= SEND_IDLE_L; - end if; - - end if; - end if; - --async because of oreg. - if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or - current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H) - and ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' - and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then --TODO: Sync these 3 signals - ram_read <= '1'; - else - ram_read <= '0'; - end if; - if RESET_IN = '1' then - ram_read <= '0'; - end if; - end process; - ----------------------------------------------------------------------- --- ----------------------------------------------------------------------- - - txallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, - D_IN(0) => TX_ALLOW_IN, - D_OUT(0) => tx_allow_qtx); - rxallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, - D_IN(0) => RX_ALLOW_IN, - D_OUT(0) => rx_allow_qtx); - sendres_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, - D_IN(0) => SEND_LINK_RESET_IN, - D_OUT(0) => send_link_reset_qtx); - txallow_sync2 : signal_sync port map(RESET => '0',CLK0 => CLK_100, CLK1 => CLK_100, - D_IN(0) => tx_allow_qtx, - D_OUT(0) => tx_allow_q); - - - THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync - port map( - CLK_A_IN => CLK_100, - RESET_A_IN => RESET_IN, - PULSE_A_IN => REQUEST_RETRANSMIT_IN, - CLK_B_IN => CLK_200, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => request_retransmit_i - ); - - THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync - port map( - CLK_A_IN => CLK_100, - RESET_A_IN => RESET_IN, - PULSE_A_IN => START_RETRANSMIT_IN, - CLK_B_IN => CLK_200, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => start_retransmit_i - ); - --- THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync --- port map( --- CLK_A_IN => CLK_100, --- RESET_A_IN => RESET_IN, --- PULSE_A_IN => SEND_DLM, --- CLK_B_IN => CLK_200, --- RESET_B_IN => RESET_IN, --- PULSE_B_OUT => send_dlm_in_i --- ); - send_dlm_in_i <= SEND_DLM; - - THE_POSITION_REG : process(CLK_100) - begin - if rising_edge(CLK_100) then - if REQUEST_RETRANSMIT_IN = '1' then - request_position_q <= REQUEST_POSITION_IN; - end if; - if START_RETRANSMIT_IN = '1' then - restart_position_q <= START_POSITION_IN; - end if; - end if; - end process; - - ---Store Request Retransmit position - THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN) - begin - if RESET_IN = '1' then - make_request_i <= '0'; - request_position_i <= (others => '0'); - elsif rising_edge(CLK_200) then - if tx_allow_qtx = '0' then - make_request_i <= '0'; - request_position_i <= (others => '0'); - elsif request_retransmit_i = '1' then - make_request_i <= '1'; - request_position_i <= request_position_q; - elsif current_state = SEND_REQUEST_L then - make_request_i <= '0'; - elsif current_state = SEND_REQUEST_H then - request_position_i <= (others => '0'); - end if; - end if; - end process; - - ---Store Restart position - THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN) - begin - if RESET_IN = '1' then - make_restart_i <= '0'; - restart_position_i <= (others => '0'); - elsif rising_edge(CLK_200) then - if tx_allow_qtx = '0' then - make_restart_i <= '0'; - restart_position_i <= (others => '0'); - elsif start_retransmit_i = '1' then - make_restart_i <= '1'; - restart_position_i <= restart_position_q; - elsif current_state = SEND_START_L then - make_restart_i <= '0'; - elsif current_state = SEND_START_H then - restart_position_i <= (others => '0'); - end if; - end if; - end process; - ---Store Restart position - THE_STORE_DLM_PROC : process(CLK_200, RESET_IN) - begin - if RESET_IN = '1' then - send_dlm_i <= '0'; - elsif rising_edge(CLK_200) then - if tx_allow_qtx = '0' then - send_dlm_i <= '0'; - elsif send_dlm_in_i = '1' then - send_dlm_i <= '1'; - elsif current_state = SEND_DLM_L then - send_dlm_i <= '0'; - end if; - end if; - end process; - - load_read_pointer_i <= '1' when current_state = SEND_START_L else '0'; - - -- gk 05.10.10 - crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0'; - crc_en <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0'; - crc_data <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0); - - -- gk 05.10.10 - CRC_CALC : trb_net_CRC8 - port map( - CLK => CLK_200, - RESET => crc_reset, - CLK_EN => crc_en, - DATA_IN => crc_data, - CRC_OUT => crc_q, - CRC_match => open - ); - - ----------------------------------------------------------------------- --- Debug ----------------------------------------------------------------------- - DEBUG_OUT(0) <= ct_fifo_afull; - DEBUG_OUT(1) <= ct_fifo_write; - DEBUG_OUT(2) <= ct_fifo_read; - DEBUG_OUT(3) <= tx_allow_qtx; --- DEBUG_OUT(4) <= ram_empty; - DEBUG_OUT(5) <= ram_afull; - DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200); - DEBUG_OUT(7) <= TX_WRITE_IN; --- DEBUG_OUT(8) <= ram_read; - DEBUG_OUT(9) <= ram_write; - DEBUG_OUT(13 downto 10) <= state_bits; - DEBUG_OUT(15 downto 14) <= "00"; - DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0); - DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0); - - process(CLK_100) - begin - if rising_edge(CLK_100) then - STAT_REG_OUT <= (others => '0'); --- STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level); - STAT_REG_OUT(3 downto 0) <= state_bits; - --- STAT_REG_OUT(7) <= TX_K_OUT; --- STAT_REG_OUT(15 downto 8) <= TX_DATA_OUT; - STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr); --- STAT_REG_OUT(16) <= ram_afull; - STAT_REG_OUT(17) <= ram_empty; - STAT_REG_OUT(18) <= tx_allow_qtx; - STAT_REG_OUT(19) <= TX_ALLOW_IN; - STAT_REG_OUT(20) <= make_restart_i; - STAT_REG_OUT(21) <= make_request_i; - STAT_REG_OUT(22) <= load_eop; - STAT_REG_OUT(23) <= send_dlm_i; - STAT_REG_OUT(24) <= make_restart_i; - STAT_REG_OUT(25) <= make_request_i; - STAT_REG_OUT(26) <= load_read_pointer_i; - STAT_REG_OUT(27) <= ct_fifo_afull; - STAT_REG_OUT(28) <= ct_fifo_read; - STAT_REG_OUT(29) <= ct_fifo_write; - STAT_REG_OUT(30) <= RESET_IN; - STAT_REG_OUT(31) <= '0'; --- STAT_REG_OUT(31 downto 27) <= (others => '0'); - end if; - end process; - -state_bits <= x"0" when current_state = SEND_IDLE_L else - x"1" when current_state = SEND_IDLE_H else - x"2" when current_state = SEND_DATA_L else - x"3" when current_state = SEND_DATA_H else - x"4" when current_state = SEND_DLM_L else - x"5" when current_state = SEND_DLM_H else - x"6" when current_state = SEND_START_L else - x"7" when current_state = SEND_START_H else - x"8" when current_state = SEND_REQUEST_L else - x"9" when current_state = SEND_REQUEST_H else - x"a" when current_state = SEND_CHKSUM_L else - x"b" when current_state = SEND_CHKSUM_H else - x"c" when current_state = SEND_RESET else - x"F"; - -end architecture; diff --git a/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xci b/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xci deleted file mode 100644 index bcca90e..0000000 --- a/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xci +++ /dev/null @@ -1,716 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - clk_wiz_sysclk - - - false - 100000000 - false - 100000000 - false - 100000000 - false - 100000000 - - - - 100000000 - 0 - 0 - 0.000 - - - - 100000000 - 0 - 0 - 0.000 - 1 - LEVEL_HIGH - - - - 100000000 - 0 - 0 - 0.000 - 0 - 0 - - 100000000 - 0 - 0 - 0.000 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - MMCM - cddcdone - cddcreq - 0000 - 0000 - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 50.0 - 100.0 - 0000 - 0000 - 200.00000 - 0000 - 0000 - 100.00000 - BUFG - 50.0 - false - 200.00000 - 0.000 - 50.000 - 200.000 - 0.000 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.0 - false - 100.00000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - VCO - clk_in_sel - clk_out1 - clk_out2 - clk_out3 - clk_out4 - clk_out5 - clk_out6 - clk_out7 - CLK_VALID - NA - daddr - dclk - den - din - 0000 - 1 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - dout - drdy - dwe - 93.000 - 1.000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - FDBK_AUTO - 0000 - 0000 - 0 - Input Clock Freq (MHz) Input Jitter (UI) - __primary_________200.000____________0.010 - no_secondary_input_clock - input_clk_stopped - 0 - Units_MHz - No_Jitter - locked - 0000 - 0000 - 0000 - false - false - false - false - false - false - false - false - OPTIMIZED - 5.000 - 0.000 - FALSE - 5.000 - 10.0 - 5.000 - 0.500 - 0.000 - FALSE - 10 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - AUTO - 1 - None - 0.010 - 0.010 - FALSE - 64.000 - 2.000 - 2 - Output Output Phase Duty Cycle Pk-to-Pk Phase - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1__200.00000______0.000______50.0_______98.146_____89.971 - clk_out2__100.00000______0.000______50.0______112.316_____89.971 - no_CLK_OUT3_output - no_CLK_OUT4_output - no_CLK_OUT5_output - no_CLK_OUT6_output - no_CLK_OUT7_output - 0 - 0 - 128.000 - 1.000 - WAVEFORM - UNKNOWN - false - false - false - false - false - OPTIMIZED - 1 - 0.000 - 1.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - No notes - 0.010 - power_down - 0000 - 1 - clk_in1 - MMCM - AUTO - 200.000 - 0.010 - 10.000 - Differential_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - 0 - reset - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 4000 - 0.004 - STATUS - 11 - 32 - 100.0 - 100.0 - 100.0 - 100.0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 1440.000 - 600.000 - clk_wiz_sysclk - MMCM - false - empty - cddcdone - cddcreq - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 50.0 - 0.010 - 100.0 - 0.010 - Buffer - 98.146 - false - 89.971 - 50.000 - 200.000 - 0.000 - 1 - true - Buffer - 112.316 - false - 89.971 - 50.000 - 100.000 - 0.000 - 1 - true - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - 600.000 - Custom - Custom - clk_in_sel - clk_out1 - false - clk_out2 - false - clk_out3 - false - clk_out4 - false - clk_out5 - false - clk_out6 - false - clk_out7 - false - CLK_VALID - auto - clk_wiz_sysclk - daddr - dclk - den - Custom - Custom - din - dout - drdy - dwe - false - false - false - false - false - false - false - false - false - FDBK_AUTO - input_clk_stopped - frequency - Enable_AXI - Units_MHz - Units_UI - UI - No_Jitter - locked - OPTIMIZED - 5.000 - 0.000 - false - 5.000 - 10.0 - 5.000 - 0.500 - 0.000 - false - 10 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - AUTO - 1 - None - 0.010 - 0.010 - false - 2 - false - false - WAVEFORM - false - UNKNOWN - OPTIMIZED - 4 - 0.000 - 10.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - None - 0.010 - power_down - 1 - clk_in1 - MMCM - mmcm_adv - 200.000 - 0.010 - 10.000 - Differential_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - REL_PRIMARY - Custom - reset - ACTIVE_HIGH - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 250 - 0.004 - STATUS - empty - 100.0 - 100.0 - 100.0 - 100.0 - false - false - false - false - false - false - false - true - false - false - true - false - false - false - false - false - true - false - false - false - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xml b/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xml deleted file mode 100644 index 888d934..0000000 --- a/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xml +++ /dev/null @@ -1,4589 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_sysclk - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - true - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:6c74f6e8 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in1_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - clk_in1_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - clk_in2_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - resetn - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - ref_clk - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_stop - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_glitch - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - interrupt - - out - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_oor - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk0 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk1 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk2 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk3 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_out1 - - out - - - std_logic - xilinx_elaborateports - - - - - - clk_out2 - - out - - - std_logic - xilinx_elaborateports - - - - - - locked - - out - - - std_logic - xilinx_elaborateports - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 0 - - - C_CLKOUT4_USED - 0 - - - C_CLKOUT5_USED - 0 - - - C_CLKOUT6_USED - 0 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_sysclk - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 0 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 200.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Differential_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 2 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________200.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1__200.00000______0.000______50.0_______98.146_____89.971 - - - C_OUTCLK_SUM_ROW2 - clk_out2__100.00000______0.000______50.0______112.316_____89.971 - - - C_OUTCLK_SUM_ROW3 - no_CLK_OUT3_output - - - C_OUTCLK_SUM_ROW4 - no_CLK_OUT4_output - - - C_OUTCLK_SUM_ROW5 - no_CLK_OUT5_output - - - C_OUTCLK_SUM_ROW6 - no_CLK_OUT6_output - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 200.000 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 200.00000 - - - C_CLKOUT2_OUT_FREQ - 100.00000 - - - C_CLKOUT3_OUT_FREQ - 100.000 - - - C_CLKOUT4_OUT_FREQ - 100.000 - - - C_CLKOUT5_OUT_FREQ - 100.000 - - - C_CLKOUT6_OUT_FREQ - 100.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 5.000 - - - C_MMCM_CLKIN1_PERIOD - 5.000 - - - C_MMCM_CLKIN2_PERIOD - 10.0 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - AUTO - - - C_MMCM_DIVCLK_DIVIDE - 1 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 5.000 - - - C_MMCM_CLKOUT1_DIVIDE - 10 - - - C_MMCM_CLKOUT2_DIVIDE - 1 - - - C_MMCM_CLKOUT3_DIVIDE - 1 - - - C_MMCM_CLKOUT4_DIVIDE - 1 - - - C_MMCM_CLKOUT5_DIVIDE - 1 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 50.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - MMCM - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 2.0 - - - C_DIVIDE3_AUTO - 2.0 - - - C_DIVIDE4_AUTO - 2.0 - - - C_DIVIDE5_AUTO - 2.0 - - - C_DIVIDE6_AUTO - 2.0 - - - C_DIVIDE7_AUTO - 2.0 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 200.00000 - - - C_CLKOUT1_ACTUAL_FREQ - 100.00000 - - - C_CLKOUT2_ACTUAL_FREQ - 100.000 - - - C_CLKOUT3_ACTUAL_FREQ - 100.000 - - - C_CLKOUT4_ACTUAL_FREQ - 100.000 - - - C_CLKOUT5_ACTUAL_FREQ - 100.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - C_M_MAX - 64.000 - - - C_M_MIN - 2.000 - - - C_D_MAX - 93.000 - - - C_D_MIN - 1.000 - - - C_O_MAX - 128.000 - - - C_O_MIN - 1.000 - - - C_VCO_MIN - 600.000 - - - C_VCO_MAX - 1440.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_d0ea4aeb - MMCM - PLL - Auto - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_39d99e50 - Buffer - Buffer_with_CE - BUFG - BUFGCE - BUFGCE_DIV - No_buffer - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_94e02745 - AUTO - EXTERNAL - INTERNAL - BUF_IN - ZHOLD - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_sysclk - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - MMCM - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - false - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 200.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 50.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - false - - - CLKOUT4_USED - false - - - CLKOUT5_USED - false - - - CLKOUT6_USED - false - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 2 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 200.000 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Differential_clock_capable_pin - - - CLKOUT1_DRIVES - Buffer - - - CLKOUT2_DRIVES - Buffer - - - CLKOUT3_DRIVES - Buffer - - - CLKOUT4_DRIVES - Buffer - - - CLKOUT5_DRIVES - Buffer - - - CLKOUT6_DRIVES - Buffer - - - CLKOUT7_DRIVES - Buffer - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 1 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 5.000 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 5.000 - - - MMCM_CLKIN2_PERIOD - 10.0 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - AUTO - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 5.000 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 10 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 1 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 1 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 1 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 1 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 98.146 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 89.971 - - - CLKOUT2_JITTER - Clkout2 Jitter - 112.316 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 89.971 - - - CLKOUT3_JITTER - Clkout3 Jitter - 0.0 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 0.0 - - - CLKOUT4_JITTER - Clkout4 Jitter - 0.0 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 0.0 - - - CLKOUT5_JITTER - Clkout5 Jitter - 0.0 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 0.0 - - - CLKOUT6_JITTER - Clkout6 Jitter - 0.0 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 0.0 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - diff --git a/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xci b/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xci deleted file mode 100644 index 6c5a0f0..0000000 --- a/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xci +++ /dev/null @@ -1,715 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - clk_wiz_tx_usrclk - - - false - 100000000 - false - 100000000 - false - 100000000 - false - 100000000 - - - - 100000000 - 0 - 0 - 0.000 - - - - 100000000 - 0 - 0 - 0.000 - - - - 100000000 - 0 - 0 - 0.000 - 1 - LEVEL_HIGH - - - - 100000000 - 0 - 0 - 0.000 - 0 - 0 - - 100000000 - 0 - 0 - 0.000 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - MMCM - cddcdone - cddcreq - 0000 - 0000 - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 100.0 - 100.0 - 0000 - 0000 - 200.00000 - 0000 - 0000 - 100.00000 - BUFG - 50.0 - false - 200.00000 - 0.000 - 50.000 - 200.000 - 0.000 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.0 - false - 100.00000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - VCO - clk_in_sel - clk_out1 - clk_out2 - clk_out3 - clk_out4 - clk_out5 - clk_out6 - clk_out7 - CLK_VALID - NA - daddr - dclk - den - din - 0000 - 1 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - dout - drdy - dwe - 93.000 - 1.000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - FDBK_AUTO - 0000 - 0000 - 0 - Input Clock Freq (MHz) Input Jitter (UI) - __primary_________100.000____________0.010 - no_secondary_input_clock - input_clk_stopped - 0 - Units_MHz - No_Jitter - locked - 0000 - 0000 - 0000 - false - false - false - false - false - false - false - false - OPTIMIZED - 10.000 - 0.000 - FALSE - 10.000 - 10.000 - 5.000 - 0.500 - 0.000 - FALSE - 10 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - AUTO - 1 - None - 0.010 - 0.010 - FALSE - 64.000 - 2.000 - 2 - Output Output Phase Duty Cycle Pk-to-Pk Phase - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1__200.00000______0.000______50.0______114.829_____98.575 - clk_out2__100.00000______0.000______50.0______130.958_____98.575 - no_CLK_OUT3_output - no_CLK_OUT4_output - no_CLK_OUT5_output - no_CLK_OUT6_output - no_CLK_OUT7_output - 0 - 0 - 128.000 - 1.000 - WAVEFORM - UNKNOWN - false - false - false - false - false - OPTIMIZED - 1 - 0.000 - 1.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - No notes - 0.010 - power_down - 0000 - 1 - clk_in1 - MMCM - AUTO - 100.000 - 0.010 - 10.000 - Single_ended_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - 0 - reset - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 4000 - 0.004 - STATUS - 11 - 32 - 100.0 - 100.0 - 100.0 - 100.0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 1440.000 - 600.000 - clk_wiz_tx_usrclk - MMCM - false - empty - cddcdone - cddcreq - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 100.0 - 0.010 - 100.0 - 0.010 - Buffer - 114.829 - false - 98.575 - 50.000 - 200.000 - 0.000 - 1 - true - Buffer - 130.958 - false - 98.575 - 50.000 - 100.000 - 0.000 - 1 - true - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - 600.000 - Custom - Custom - clk_in_sel - clk_out1 - false - clk_out2 - false - clk_out3 - false - clk_out4 - false - clk_out5 - false - clk_out6 - false - clk_out7 - false - CLK_VALID - auto - clk_wiz_tx_usrclk - daddr - dclk - den - Custom - Custom - din - dout - drdy - dwe - false - false - false - false - false - false - false - false - false - FDBK_AUTO - input_clk_stopped - frequency - Enable_AXI - Units_MHz - Units_UI - UI - No_Jitter - locked - OPTIMIZED - 10.000 - 0.000 - false - 10.000 - 10.000 - 5.000 - 0.500 - 0.000 - false - 10 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - AUTO - 1 - None - 0.010 - 0.010 - false - 2 - false - false - WAVEFORM - false - UNKNOWN - OPTIMIZED - 4 - 0.000 - 10.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - None - 0.010 - power_down - 1 - clk_in1 - MMCM - mmcm_adv - 100.000 - 0.010 - 10.000 - Single_ended_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - REL_PRIMARY - Custom - reset - ACTIVE_HIGH - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 250 - 0.004 - STATUS - empty - 100.0 - 100.0 - 100.0 - 100.0 - false - false - false - false - false - false - false - true - false - false - true - false - false - false - false - false - true - false - false - false - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xml b/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xml deleted file mode 100644 index 81cf3f7..0000000 --- a/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xml +++ /dev/null @@ -1,4678 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_tx_usrclk - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:f3d36923 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in1_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in1_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in2_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - resetn - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - ref_clk - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_stop - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_glitch - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - interrupt - - out - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_oor - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk0 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk1 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk2 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk3 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in1 - - in - - - std_logic - xilinx_elaborateports - - - - - - clk_out1 - - out - - - std_logic - xilinx_elaborateports - - - - - - clk_out2 - - out - - - std_logic - xilinx_elaborateports - - - - - - locked - - out - - - std_logic - xilinx_elaborateports - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 0 - - - C_CLKOUT4_USED - 0 - - - C_CLKOUT5_USED - 0 - - - C_CLKOUT6_USED - 0 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_tx_usrclk - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 0 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 2 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1__200.00000______0.000______50.0______114.829_____98.575 - - - C_OUTCLK_SUM_ROW2 - clk_out2__100.00000______0.000______50.0______130.958_____98.575 - - - C_OUTCLK_SUM_ROW3 - no_CLK_OUT3_output - - - C_OUTCLK_SUM_ROW4 - no_CLK_OUT4_output - - - C_OUTCLK_SUM_ROW5 - no_CLK_OUT5_output - - - C_OUTCLK_SUM_ROW6 - no_CLK_OUT6_output - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 200.000 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 200.00000 - - - C_CLKOUT2_OUT_FREQ - 100.00000 - - - C_CLKOUT3_OUT_FREQ - 100.000 - - - C_CLKOUT4_OUT_FREQ - 100.000 - - - C_CLKOUT5_OUT_FREQ - 100.000 - - - C_CLKOUT6_OUT_FREQ - 100.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 10.000 - - - C_MMCM_CLKIN1_PERIOD - 10.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - AUTO - - - C_MMCM_DIVCLK_DIVIDE - 1 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 5.000 - - - C_MMCM_CLKOUT1_DIVIDE - 10 - - - C_MMCM_CLKOUT2_DIVIDE - 1 - - - C_MMCM_CLKOUT3_DIVIDE - 1 - - - C_MMCM_CLKOUT4_DIVIDE - 1 - - - C_MMCM_CLKOUT5_DIVIDE - 1 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - MMCM - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 2.0 - - - C_DIVIDE3_AUTO - 2.0 - - - C_DIVIDE4_AUTO - 2.0 - - - C_DIVIDE5_AUTO - 2.0 - - - C_DIVIDE6_AUTO - 2.0 - - - C_DIVIDE7_AUTO - 2.0 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 200.00000 - - - C_CLKOUT1_ACTUAL_FREQ - 100.00000 - - - C_CLKOUT2_ACTUAL_FREQ - 100.000 - - - C_CLKOUT3_ACTUAL_FREQ - 100.000 - - - C_CLKOUT4_ACTUAL_FREQ - 100.000 - - - C_CLKOUT5_ACTUAL_FREQ - 100.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - C_M_MAX - 64.000 - - - C_M_MIN - 2.000 - - - C_D_MAX - 93.000 - - - C_D_MIN - 1.000 - - - C_O_MAX - 128.000 - - - C_O_MIN - 1.000 - - - C_VCO_MIN - 600.000 - - - C_VCO_MAX - 1440.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_d0ea4aeb - MMCM - PLL - Auto - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_39d99e50 - Buffer - Buffer_with_CE - BUFG - BUFGCE - BUFGCE_DIV - No_buffer - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_94e02745 - AUTO - EXTERNAL - INTERNAL - BUF_IN - ZHOLD - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_tx_usrclk - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - MMCM - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - false - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - false - - - CLKOUT4_USED - false - - - CLKOUT5_USED - false - - - CLKOUT6_USED - false - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 2 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 200.000 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - Buffer - - - CLKOUT2_DRIVES - Buffer - - - CLKOUT3_DRIVES - Buffer - - - CLKOUT4_DRIVES - Buffer - - - CLKOUT5_DRIVES - Buffer - - - CLKOUT6_DRIVES - Buffer - - - CLKOUT7_DRIVES - Buffer - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 1 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 10.000 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - AUTO - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 5.000 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 10 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 1 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 1 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 1 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 1 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 114.829 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 98.575 - - - CLKOUT2_JITTER - Clkout2 Jitter - 130.958 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 98.575 - - - CLKOUT3_JITTER - Clkout3 Jitter - 0.0 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 0.0 - - - CLKOUT4_JITTER - Clkout4 Jitter - 0.0 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 0.0 - - - CLKOUT5_JITTER - Clkout5 Jitter - 0.0 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 0.0 - - - CLKOUT6_JITTER - Clkout6 Jitter - 0.0 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 0.0 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - diff --git a/media_interfaces/xcku/common/gth_xcku_components.vhd b/media_interfaces/xcku/common/gth_xcku_components.vhd deleted file mode 100644 index cd63634..0000000 --- a/media_interfaces/xcku/common/gth_xcku_components.vhd +++ /dev/null @@ -1,48 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package gth_xcku_components is - component clk_wiz_sysclk is - port ( - clk_in1_p : in std_logic; - clk_in1_n : in std_logic; - reset : in std_logic; - clk_out1 : out std_logic; - clk_out2 : out std_logic; - locked : out std_logic - ); - end component; - - component clk_wiz_tx_usrclk is - port ( - clk_in1 : in std_logic; - reset : in std_logic; - clk_out1 : out std_logic; - clk_out2 : out std_logic; - locked : out std_logic - ); - end component; - - component IBUFDS_GTE3 is - generic ( - REFCLK_EN_TX_PATH : std_logic := '0'; - REFCLK_HROW_CK_SEL : std_logic_vector(1 downto 0) := "00"; - REFCLK_ICNTL_RX : std_logic_vector(1 downto 0) := "00" - ); - port ( - I : in std_logic; - IB : in std_logic; - CEB : in std_logic; - O : out std_logic; - ODIV2 : out std_logic_vector(0 downto 0) - ); - end component; - - component gtwizard_ultrascale_v1_7_8_bit_synchronizer - port ( - clk_in : in std_logic; - i_in : in std_logic; - o_out : out std_logic - ); - end component; -end package gth_xcku_components; diff --git a/media_interfaces/xcku/common/gth_xcku_init.v b/media_interfaces/xcku/common/gth_xcku_init.v index ec2f2b6..98491da 100644 --- a/media_interfaces/xcku/common/gth_xcku_init.v +++ b/media_interfaces/xcku/common/gth_xcku_init.v @@ -191,7 +191,7 @@ module gth_xcku_init # ( localparam [1:0] ST_START = 2'd0; localparam [1:0] ST_TX_WAIT = 2'd1; localparam [1:0] ST_RX_WAIT = 2'd2; - localparam [1:0] ST_END = 2'd3; + localparam [1:0] ST_MONITOR = 2'd3; reg [1:0] sm_init = ST_START; reg sm_init_active = 1'b0; @@ -216,7 +216,7 @@ module gth_xcku_init # ( ST_START: begin if (sm_init_active) begin timer_clr <= 1'b1; - reset_all_out <= 1'b1; + reset_all_out <= 1'b0; reset_rx_out <= 1'b0; retry_ctr_incr <= 1'b0; sm_init <= ST_TX_WAIT; @@ -228,7 +228,6 @@ module gth_xcku_init # ( // reset_all_out output (which in this example causes a master reset_all assertion), and increment the retry // counter. Completion conditions for TX initialization are described above. ST_TX_WAIT: begin - reset_all_out <= 1'b0; if (tx_init_done_sync) begin timer_clr <= 1'b1; sm_init <= ST_RX_WAIT; @@ -236,6 +235,7 @@ module gth_xcku_init # ( else begin if (tx_timer_sat) begin timer_clr <= 1'b1; + reset_all_out <= 1'b1; retry_ctr_incr <= 1'b1; sm_init <= ST_START; end @@ -251,29 +251,33 @@ module gth_xcku_init # ( // either drives gtwiz_reset_rx_pll_and_datapath_in or gtwiz_reset_rx_datapath_in, depending on PLL sharing), // and increnent the retry counter. ST_RX_WAIT: begin - reset_all_out <= 1'b0; - if (rx_init_done_sync) begin - timer_clr <= 1'b1; - sm_init <= ST_END; - end - else begin - if (rx_timer_sat) begin - timer_clr <= 1'b1; - retry_ctr_incr <= 1'b1; - reset_all_out <= 1'b1; - sm_init <= ST_RX_WAIT; + if (rx_timer_sat) begin + if (rx_init_done_sync && rx_data_good_sync) begin + init_done_out <= 1'b1; + sm_init <= ST_MONITOR; end else begin - timer_clr <= 1'b0; + timer_clr <= 1'b1; + reset_rx_out <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; end end + else begin + timer_clr <= 1'b0; + end end // In this MONITOR state, assert the init_done_out output for use as desired. If RX initialization or the data // good indicator is lost while in this state, reset the RX components as described in the ST_RX_WAIT state. - ST_END: begin - init_done_out <= 1'b1; - sm_init_active <= 1'b0; + ST_MONITOR: begin + if (~rx_init_done_sync || ~rx_data_good_sync) begin + init_done_out <= 1'b0; + timer_clr <= 1'b1; + reset_rx_out <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end end endcase diff --git a/media_interfaces/xcku/common/gth_xcku_init_orig.v b/media_interfaces/xcku/common/gth_xcku_init_orig.v deleted file mode 100644 index 98491da..0000000 --- a/media_interfaces/xcku/common/gth_xcku_init_orig.v +++ /dev/null @@ -1,288 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - - -`timescale 1ps/1ps - -// ===================================================================================================================== -// This example design initialization module provides a demonstration of how initialization logic can be constructed to -// interact with and enhance the reset controller helper block in order to assist with successful system bring-up. This -// example initialization logic monitors for timely reset completion, retrying resets as necessary to mitigate problems -// with system bring-up such as clock or data connection readiness. This is an example and can be modified as necessary. -// ===================================================================================================================== - -module gth_xcku_init # ( - - parameter real P_FREERUN_FREQUENCY = 100, - parameter real P_TX_TIMER_DURATION_US = 30000, - parameter real P_RX_TIMER_DURATION_US = 130000 - -)( - - input wire clk_freerun_in, - input wire reset_all_in, - input wire tx_init_done_in, - input wire rx_init_done_in, - input wire rx_data_good_in, - output reg reset_all_out = 1'b0, - output reg reset_rx_out = 1'b0, - output reg init_done_out = 1'b0, - output reg [3:0] retry_ctr_out = 4'd0 - -); - - - // ------------------------------------------------------------------------------------------------------------------- - // Synchronizers - // ------------------------------------------------------------------------------------------------------------------- - - // Synchronize the "reset all" input signal into the free-running clock domain - // The reset_all_in input should be driven by the master "reset all" example design input - wire reset_all_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_reset_synchronizer reset_synchronizer_reset_all_inst ( - .clk_in (clk_freerun_in), - .rst_in (reset_all_in), - .rst_out (reset_all_sync) - ); - - // Synchronize the TX initialization done indicator into the free-running clock domain - // The tx_init_done_in input should be driven by the signal or logical combination of signals that represents a - // completed TX initialization process; for example, the reset helper block gtwiz_reset_tx_done_out signal, or the - // logical AND of gtwiz_reset_tx_done_out with gtwiz_buffbypass_tx_done_out if the TX buffer is bypassed. - wire tx_init_done_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_tx_init_done_inst ( - .clk_in (clk_freerun_in), - .i_in (tx_init_done_in), - .o_out (tx_init_done_sync) - ); - - // Synchronize the RX initialization done indicator into the free-running clock domain - // The rx_init_done_in input should be driven by the signal or logical combination of signals that represents a - // completed RX initialization process; for example, the reset helper block gtwiz_reset_rx_done_out signal, or the - // logical AND of gtwiz_reset_rx_done_out with gtwiz_buffbypass_rx_done_out if the RX elastic buffer is bypassed. - wire rx_init_done_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_init_done_inst ( - .clk_in (clk_freerun_in), - .i_in (rx_init_done_in), - .o_out (rx_init_done_sync) - ); - - // Synchronize the RX data good indicator into the free-running clock domain - // The rx_data_good_in input should be driven the user application's indication of continual good data reception. - // The example design drives rx_data_good_in high when no PRBS checker errors are seen in the 8 most recent - // consecutive clock cycles of data reception. - wire rx_data_good_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_data_good_inst ( - .clk_in (clk_freerun_in), - .i_in (rx_data_good_in), - .o_out (rx_data_good_sync) - ); - - - // ------------------------------------------------------------------------------------------------------------------- - // Timer - // ------------------------------------------------------------------------------------------------------------------- - - // Declare registers and local parameters used for the shared TX and RX initialization timer - // The free-running clock frequency is specified by the P_FREERUN_FREQUENCY parameter. The TX initialization timer - // duration is specified by the P_TX_TIMER_DURATION_US parameter (default 30,000us), and the resulting terminal count - // is assigned to p_tx_timer_term_cyc_int. The RX initialization timer duration is specified by the - // P_RX_TIMER_DURATION_US parameter (default 130,000us), and the resulting terminal count is assigned to - // p_rx_timer_term_cyc_int. - reg timer_clr = 1'b1; - reg [24:0] timer_ctr = 25'd0; - reg tx_timer_sat = 1'b0; - reg rx_timer_sat = 1'b0; - wire [24:0] p_tx_timer_term_cyc_int = P_TX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; - wire [24:0] p_rx_timer_term_cyc_int = P_RX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; - - // When the timer is enabled by the initialization state machine, increment the timer_ctr counter until its value - // reaches p_rx_timer_term_cyc_int RX terminal count and rx_timer_sat is asserted. Assert tx_timer_sat when the - // counter value reaches the p_tx_timer_term_cyc_int TX terminal count. Clear the timer and remove assertions when the - // timer is disabled by the initialization state machine. - always @(posedge clk_freerun_in) begin - if (timer_clr) begin - timer_ctr <= 25'd0; - tx_timer_sat <= 1'b0; - rx_timer_sat <= 1'b0; - end - else begin - if (timer_ctr == p_tx_timer_term_cyc_int) - tx_timer_sat <= 1'b1; - - if (timer_ctr == p_rx_timer_term_cyc_int) - rx_timer_sat <= 1'b1; - else - timer_ctr <= timer_ctr + 25'd1; - end - end - - - // ------------------------------------------------------------------------------------------------------------------- - // Retry counter - // ------------------------------------------------------------------------------------------------------------------- - - // Increment the retry_ctr_out register for each TX or RX reset asserted by the initialization state machine until the - // register saturates at 4'd15. This value, which is initialized on device programming and is never reset, could be - // useful for debugging purposes. The initialization state machine will continue to retry as needed beyond the retry - // register saturation point indicated, so 4'd15 should be interpreted as "15 or more attempts since programming." - reg retry_ctr_incr = 1'b0; - - always @(posedge clk_freerun_in) begin - if ((retry_ctr_incr == 1'b1) && (retry_ctr_out != 4'd15)) - retry_ctr_out <= retry_ctr_out + 4'd1; - end - - - // ------------------------------------------------------------------------------------------------------------------- - // Initialization state machine - // ------------------------------------------------------------------------------------------------------------------- - - // Declare local parameters and state register for the initialization state machine - localparam [1:0] ST_START = 2'd0; - localparam [1:0] ST_TX_WAIT = 2'd1; - localparam [1:0] ST_RX_WAIT = 2'd2; - localparam [1:0] ST_MONITOR = 2'd3; - reg [1:0] sm_init = ST_START; - reg sm_init_active = 1'b0; - - // Implement the initialization state machine control and its outputs as a single sequential process. The state - // machine is reset by the synchronized reset_all_in input, and does not begin operating until its first use. Note - // that this state machine is designed to interact with and enhance the reset controller helper block. - always @(posedge clk_freerun_in) begin - if (reset_all_sync) begin - timer_clr <= 1'b1; - reset_all_out <= 1'b0; - reset_rx_out <= 1'b0; - retry_ctr_incr <= 1'b0; - init_done_out <= 1'b0; - sm_init_active <= 1'b1; - sm_init <= ST_START; - end - else begin - case (sm_init) - - // When starting the initialization procedure, clear the timer and remove reset outputs, then proceed to wait - // for completion of TX initialization - ST_START: begin - if (sm_init_active) begin - timer_clr <= 1'b1; - reset_all_out <= 1'b0; - reset_rx_out <= 1'b0; - retry_ctr_incr <= 1'b0; - sm_init <= ST_TX_WAIT; - end - end - - // Enable the timer. If TX initialization completes before the counter's TX terminal count, clear the timer and - // proceed to wait for RX initialization. If the TX terminal count is reached, clear the timer, assert the - // reset_all_out output (which in this example causes a master reset_all assertion), and increment the retry - // counter. Completion conditions for TX initialization are described above. - ST_TX_WAIT: begin - if (tx_init_done_sync) begin - timer_clr <= 1'b1; - sm_init <= ST_RX_WAIT; - end - else begin - if (tx_timer_sat) begin - timer_clr <= 1'b1; - reset_all_out <= 1'b1; - retry_ctr_incr <= 1'b1; - sm_init <= ST_START; - end - else begin - timer_clr <= 1'b0; - end - end - end - - // Enable the timer. When the RX terminal count is reached, check whether RX initialization has completed and - // whether the data good indicator is high. If both conditions are met, transition to the MONITOR state. If - // either condition is not met, then clear the timer, assert the reset_rx_out output (which in this example - // either drives gtwiz_reset_rx_pll_and_datapath_in or gtwiz_reset_rx_datapath_in, depending on PLL sharing), - // and increnent the retry counter. - ST_RX_WAIT: begin - if (rx_timer_sat) begin - if (rx_init_done_sync && rx_data_good_sync) begin - init_done_out <= 1'b1; - sm_init <= ST_MONITOR; - end - else begin - timer_clr <= 1'b1; - reset_rx_out <= 1'b1; - retry_ctr_incr <= 1'b1; - sm_init <= ST_START; - end - end - else begin - timer_clr <= 1'b0; - end - end - - // In this MONITOR state, assert the init_done_out output for use as desired. If RX initialization or the data - // good indicator is lost while in this state, reset the RX components as described in the ST_RX_WAIT state. - ST_MONITOR: begin - if (~rx_init_done_sync || ~rx_data_good_sync) begin - init_done_out <= 1'b0; - timer_clr <= 1'b1; - reset_rx_out <= 1'b1; - retry_ctr_incr <= 1'b1; - sm_init <= ST_START; - end - end - - endcase - end - end - - -endmodule diff --git a/media_interfaces/xcku/common/gth_xcku_wrapper_functions.v b/media_interfaces/xcku/common/gth_xcku_wrapper_functions.v deleted file mode 100644 index b158f07..0000000 --- a/media_interfaces/xcku/common/gth_xcku_wrapper_functions.v +++ /dev/null @@ -1,241 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - - -// ===================================================================================================================== -// This file contains functions available for example design HDL generation as required -// ===================================================================================================================== - -// Function to populate a bit mapping of enabled transceiver common blocks to transceiver quads -function [47:0] f_pop_cm_en ( - input integer in_null -); -begin : main_f_pop_cm_en - integer i; - reg [47:0] tmp; - for (i = 0; i < 192; i = i + 4) begin - if ((P_CHANNEL_ENABLE[i] == 1'b1) || - (P_CHANNEL_ENABLE[i+1] == 1'b1) || - (P_CHANNEL_ENABLE[i+2] == 1'b1) || - (P_CHANNEL_ENABLE[i+3] == 1'b1)) - tmp[i/4] = 1'b1; - else - tmp[i/4] = 1'b0; - end - f_pop_cm_en = tmp; -end -endfunction - -// Function to calculate a pointer to a master channel's packed index -function integer f_calc_pk_mc_idx ( - input integer idx_mc -); -begin : main_f_calc_pk_mc_idx - integer i, j; - integer tmp; - j = 0; - for (i = 0; i < 192; i = i + 1) begin - if (P_CHANNEL_ENABLE[i] == 1'b1) begin - if (i == idx_mc) - tmp = j; - else - j = j + 1; - end - end - f_calc_pk_mc_idx = tmp; -end -endfunction - -// Function to calculate the upper bound of a transceiver common-related signal within a packed vector, for a given -// signal width and unpacked common index -function integer f_ub_cm ( - input integer width, - input integer index -); -begin : main_f_ub_cm - integer i, j; - j = 0; - for (i = 0; i <= index; i = i + 4) begin - if (P_CHANNEL_ENABLE[i] == 1'b1 || - P_CHANNEL_ENABLE[i+1] == 1'b1 || - P_CHANNEL_ENABLE[i+2] == 1'b1 || - P_CHANNEL_ENABLE[i+3] == 1'b1) - j = j + 1; - end - f_ub_cm = (width * j) - 1; -end -endfunction - -// Function to calculate the lower bound of a transceiver common-related signal within a packed vector, for a given -// signal width and unpacked common index -function integer f_lb_cm ( - input integer width, - input integer index -); -begin : main_f_lb_cm - integer i, j; - j = 0; - for (i = 0; i < index; i = i + 4) begin - if (P_CHANNEL_ENABLE[i] == 1'b1 || - P_CHANNEL_ENABLE[i+1] == 1'b1 || - P_CHANNEL_ENABLE[i+2] == 1'b1 || - P_CHANNEL_ENABLE[i+3] == 1'b1) - j = j + 1; - end - f_lb_cm = (width * j); -end -endfunction - -// Function to calculate the packed vector index of a transceiver common, provided the packed vector index of the -// associated transceiver channel -function integer f_idx_cm ( - input integer index -); -begin : main_f_idx_cm - integer i, j, k, flag, result; - j = 0; - k = 0; - flag = 0; - for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin - if (P_CHANNEL_ENABLE[i] == 1'b1 || - P_CHANNEL_ENABLE[i+1] == 1'b1 || - P_CHANNEL_ENABLE[i+2] == 1'b1 || - P_CHANNEL_ENABLE[i+3] == 1'b1) begin - k = k + 1; - if (P_CHANNEL_ENABLE[i+3] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+2] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+1] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i] == 1'b1) - j = j + 1; - end - - if (j >= (index + 1)) begin - flag = 1; - result = k; - end - end - f_idx_cm = result - 1; -end -endfunction - -// Function to calculate the packed vector index of the upper bound transceiver channel which is associated with the -// provided transceiver common packed vector index -function integer f_idx_ch_ub ( - input integer index -); -begin : main_f_idx_ch_ub - integer i, j, k, flag, result; - j = 0; - k = 0; - flag = 0; - for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin - - if (P_CHANNEL_ENABLE[i] == 1'b1 || - P_CHANNEL_ENABLE[i+1] == 1'b1 || - P_CHANNEL_ENABLE[i+2] == 1'b1 || - P_CHANNEL_ENABLE[i+3] == 1'b1) begin - k = k + 1; - if (P_CHANNEL_ENABLE[i] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+1] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+2] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+3] == 1'b1) - j = j + 1; - if (k == index + 1) begin - flag = 1; - result = j; - end - end - - end - f_idx_ch_ub = result - 1; -end -endfunction - -// Function to calculate the packed vector index of the lower bound transceiver channel which is associated with the -// provided transceiver common packed vector index -function integer f_idx_ch_lb ( - input integer index -); -begin : main_f_idx_ch_lb - integer i, j, k, flag, result; - j = 0; - k = 0; - flag = 0; - for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin - - if (P_CHANNEL_ENABLE[i] == 1'b1 || - P_CHANNEL_ENABLE[i+1] == 1'b1 || - P_CHANNEL_ENABLE[i+2] == 1'b1 || - P_CHANNEL_ENABLE[i+3] == 1'b1) begin - k = k + 1; - if (k == index + 1) begin - flag = 1; - result = j + 1; - end - else begin - if (P_CHANNEL_ENABLE[i] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+1] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+2] == 1'b1) - j = j + 1; - if (P_CHANNEL_ENABLE[i+3] == 1'b1) - j = j + 1; - end - end - - end - f_idx_ch_lb = result - 1; -end -endfunction diff --git a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v deleted file mode 100644 index 544ceaf..0000000 --- a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v +++ /dev/null @@ -1,140 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - -// *************************** -// * DO NOT MODIFY THIS FILE * -// *************************** - -`timescale 1ps/1ps - -module gtwizard_ultrascale_v1_7_8_gtwiz_userclk_rx #( - - parameter integer P_CONTENTS = 0, - parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1, - parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1 - -)( - - input wire gtwiz_userclk_rx_srcclk_in, - input wire gtwiz_userclk_rx_reset_in, - output wire gtwiz_userclk_rx_usrclk_out, - output wire gtwiz_userclk_rx_usrclk2_out, - output wire gtwiz_userclk_rx_active_out - -); - - - // ------------------------------------------------------------------------------------------------------------------- - // Local parameters - // ------------------------------------------------------------------------------------------------------------------- - - // Convert integer parameters with known, limited legal range to a 3-bit local parameter values - localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1; - localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0]; - localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1; - localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0]; - - - // ------------------------------------------------------------------------------------------------------------------- - // Receiver user clocking network conditional generation, based on parameter values in module instantiation - // ------------------------------------------------------------------------------------------------------------------- - generate if (1) begin: gen_gtwiz_userclk_rx_main - - // Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio - if (P_CONTENTS == 0) begin - - // Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK - // frequency ratio - BUFG_GT bufg_gt_usrclk_inst ( - .CE (1'b1), - .CEMASK (1'b0), - .CLR (gtwiz_userclk_rx_reset_in), - .CLRMASK (1'b0), - .DIV (P_USRCLK_DIV), - .I (gtwiz_userclk_rx_srcclk_in), - .O (gtwiz_userclk_rx_usrclk_out) - ); - - // If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive - // RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency. - if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1) - assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out; - else begin - BUFG_GT bufg_gt_usrclk2_inst ( - .CE (1'b1), - .CEMASK (1'b0), - .CLR (gtwiz_userclk_rx_reset_in), - .CLRMASK (1'b0), - .DIV (P_USRCLK2_DIV), - .I (gtwiz_userclk_rx_srcclk_in), - .O (gtwiz_userclk_rx_usrclk2_out) - ); - end - - // Indicate active helper block functionality when the BUFG_GT divider is not held in reset - (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0; - (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0; - always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin - if (gtwiz_userclk_rx_reset_in) begin - gtwiz_userclk_rx_active_meta <= 1'b0; - gtwiz_userclk_rx_active_sync <= 1'b0; - end - else begin - gtwiz_userclk_rx_active_meta <= 1'b1; - gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta; - end - end - assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync; - - end - - end - endgenerate - - -endmodule diff --git a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v deleted file mode 100644 index 38b0b82..0000000 --- a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v +++ /dev/null @@ -1,140 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - -// *************************** -// * DO NOT MODIFY THIS FILE * -// *************************** - -`timescale 1ps/1ps - -module gtwizard_ultrascale_v1_7_8_gtwiz_userclk_tx #( - - parameter integer P_CONTENTS = 0, - parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1, - parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1 - -)( - - input wire gtwiz_userclk_tx_srcclk_in, - input wire gtwiz_userclk_tx_reset_in, - output wire gtwiz_userclk_tx_usrclk_out, - output wire gtwiz_userclk_tx_usrclk2_out, - output wire gtwiz_userclk_tx_active_out - -); - - - // ------------------------------------------------------------------------------------------------------------------- - // Local parameters - // ------------------------------------------------------------------------------------------------------------------- - - // Convert integer parameters with known, limited legal range to a 3-bit local parameter values - localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1; - localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0]; - localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1; - localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0]; - - - // ------------------------------------------------------------------------------------------------------------------- - // Transmitter user clocking network conditional generation, based on parameter values in module instantiation - // ------------------------------------------------------------------------------------------------------------------- - generate if (1) begin: gen_gtwiz_userclk_tx_main - - // Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio - if (P_CONTENTS == 0) begin - - // Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK - // frequency ratio - BUFG_GT bufg_gt_usrclk_inst ( - .CE (1'b1), - .CEMASK (1'b0), - .CLR (gtwiz_userclk_tx_reset_in), - .CLRMASK (1'b0), - .DIV (P_USRCLK_DIV), - .I (gtwiz_userclk_tx_srcclk_in), - .O (gtwiz_userclk_tx_usrclk_out) - ); - - // If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive - // TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency. - if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1) - assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out; - else begin - BUFG_GT bufg_gt_usrclk2_inst ( - .CE (1'b1), - .CEMASK (1'b0), - .CLR (gtwiz_userclk_tx_reset_in), - .CLRMASK (1'b0), - .DIV (P_USRCLK2_DIV), - .I (gtwiz_userclk_tx_srcclk_in), - .O (gtwiz_userclk_tx_usrclk2_out) - ); - end - - // Indicate active helper block functionality when the BUFG_GT divider is not held in reset - (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_meta = 1'b0; - (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_sync = 1'b0; - always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin - if (gtwiz_userclk_tx_reset_in) begin - gtwiz_userclk_tx_active_meta <= 1'b0; - gtwiz_userclk_tx_active_sync <= 1'b0; - end - else begin - gtwiz_userclk_tx_active_meta <= 1'b1; - gtwiz_userclk_tx_active_sync <= gtwiz_userclk_tx_active_meta; - end - end - assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_sync; - - end - - end - endgenerate - - -endmodule diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci index 6b87839..707f21f 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci @@ -39,17 +39,17 @@ 2 0 "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - "00110000" + "00000000" 1 - "00100010" + "00000010" 2 - 2 + 1 5000 - "00000000000000000000001011110000010100000000000000000000000000101111000001010000" + "00000000000000000000000000000000000000000000000000000000000000101111000001010000" 1 - "0101111100" + "1010000011" 1 - "1010000011" + "0101111100" 1 1 20 @@ -105,7 +105,7 @@ gth_xcku_quad_x0y2 0 0 - + rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out 100 BOTH 0 @@ -651,10 +651,10 @@ -1 -1 -1 - 13 + 14 0 None - 9 + 8 100.0000000 4 1 @@ -722,23 +722,23 @@ 00000000 00000000 00000000 - 00110000 + 00000000 false false false false - true - true + false + false false false - 00100010 - DISABLE + 00000010 + ENABLE false true false false false - true + false false false 2 @@ -751,27 +751,27 @@ false false false - 2 + 1 5000 ENABLE 0 - 00000000000000000000001011110000010100000000000000000000000000101111000001010000 + 00000000000000000000000000000000000000000000000000000000000000101111000001010000 01010000 10111100 00000000 00000000 - 01010000 - 10111100 + 00000000 + 00000000 00000000 00000000 - 1 + 2 false - 0011111111 + 1111111111 true - 0101111100 - NONE + 1010000011 + K28.5 true - 1010000011 + 0101111100 true 0 AC @@ -1044,7 +1044,7 @@ false false false - false + true false false false @@ -1165,7 +1165,7 @@ false false true - false + true false false false @@ -1175,7 +1175,7 @@ false false false - false + true true false false @@ -1195,7 +1195,7 @@ false false false - false + true false false false @@ -1280,7 +1280,7 @@ false false false - false + true false false false @@ -1299,7 +1299,7 @@ false false false - false + true true false false @@ -1318,7 +1318,7 @@ false false false - false + true false false false @@ -1379,24 +1379,21 @@ + - - + - - - + - + - diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml index b329d6d..928b263 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml @@ -14,7 +14,7 @@ outputProductCRC - 9:f772f0fd + 9:d5f7824f @@ -6217,13 +6217,13 @@ - 0x0 + 0 - false + true @@ -8545,13 +8545,13 @@ - 0x0 + 0 - false + true @@ -8753,13 +8753,13 @@ - 0x0 + 0 - false + true @@ -10280,13 +10280,13 @@ - 0x0 + 0 - false + true @@ -10722,13 +10722,13 @@ - 0x0 + 0 - false + true @@ -13406,7 +13406,7 @@ - false + true @@ -14033,7 +14033,7 @@ - false + true @@ -14218,7 +14218,7 @@ C_RX_CC_DISP - "00110000" + "00000000" C_RX_CC_ENABLE @@ -14230,7 +14230,7 @@ C_RX_CC_K - "00100010" + "00000010" C_RX_CC_LEN_SEQ @@ -14238,7 +14238,7 @@ C_RX_CC_NUM_SEQ - 2 + 1 C_RX_CC_PERIODICITY @@ -14246,7 +14246,7 @@ C_RX_CC_VAL - "00000000000000000000001011110000010100000000000000000000000000101111000001010000" + "00000000000000000000000000000000000000000000000000000000000000101111000001010000" C_RX_COMMA_M_ENABLE @@ -14254,7 +14254,7 @@ C_RX_COMMA_M_VAL - "0101111100" + "1010000011" C_RX_COMMA_P_ENABLE @@ -14262,7 +14262,7 @@ C_RX_COMMA_P_VAL - "1010000011" + "0101111100" C_RX_DATA_DECODING @@ -15561,7 +15561,7 @@ RX_COMMA_PRESET Comma value preset - NONE + K28.5 RX_COMMA_VALID_ONLY @@ -15591,25 +15591,25 @@ RX_COMMA_P_VAL Plus comma value Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 1010000011 + 0101111100 RX_COMMA_M_VAL Minus comma value Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 0101111100 + 1010000011 RX_COMMA_MASK Mask Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 0011111111 + 1111111111 RX_COMMA_ALIGN_WORD Alignment boundary Select which data byte boundaries are allowed for comma alignment - 1 + 2 RX_COMMA_SHOW_REALIGN_ENABLE @@ -16132,7 +16132,7 @@ RX_CC_NUM_SEQ Enable and select number of sequences to use Select whether to enable clock correction, and how many sequences to use if enabled - 2 + 1 RX_CC_LEN_SEQ @@ -16150,7 +16150,7 @@ RX_CC_KEEP_IDLE Keep idle Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - DISABLE + ENABLE RX_CC_PRECEDENCE @@ -16186,11 +16186,11 @@ RX_CC_VAL - 00000000000000000000001011110000010100000000000000000000000000101111000001010000 + 00000000000000000000000000000000000000000000000000000000000000101111000001010000 RX_CC_K - 00100010 + 00000010 @@ -16201,7 +16201,7 @@ RX_CC_DISP - 00110000 + 00000000 @@ -16367,48 +16367,104 @@ Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false + + + + false + + + RX_CC_VAL_1_0 Value Specify the value for this clock correction sequence and pattern - 01010000 + 00000000 + + + + false + + + RX_CC_K_1_0 K character Indicate whether or not the corresponding clock correction value is a K character false + + + + false + + + RX_CC_DISP_1_0 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - true + false + + + + false + + + RX_CC_MASK_1_1 Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false + + + + false + + + RX_CC_VAL_1_1 Value Specify the value for this clock correction sequence and pattern - 10111100 + 00000000 + + + + false + + + RX_CC_K_1_1 K character Indicate whether or not the corresponding clock correction value is a K character - true + false + + + + false + + + RX_CC_DISP_1_1 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - true + false + + + + false + + + RX_CC_MASK_1_2 @@ -16518,7 +16574,7 @@ ENABLE_OPTIONAL_PORTS Enable optional ports Indicate whether a port should be included - + rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out RX_REFCLK_SOURCE @@ -16624,7 +16680,7 @@ INTERNAL_PORT_ENABLEMENT_UPDATED - 13 + 14 @@ -16657,7 +16713,7 @@ INTERNAL_RX_COMMA_PRESET_UPDATE - 9 + 8 @@ -22688,24 +22744,21 @@ 8 + - - + - - - + - + - diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd index 47cc1d7..25f9269 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd @@ -6,82 +6,103 @@ use unisim.vcomponents.all; entity gth_xcku_quad_x0y2_top is port ( - clk_100 : in std_logic; - clk_200 : in std_logic; - reset_all : in std_logic; - mgtrefclk0_x0y3_int : in std_logic; - FREECLK : in std_logic; - - ch0_gthrxn_in : in std_logic_vector(3 downto 0); - ch0_gthrxp_in : in std_logic_vector(3 downto 0); - ch0_gthtxn_out : out std_logic_vector(3 downto 0); - ch0_gthtxp_out : out std_logic_vector(3 downto 0); - - tx_clk : out std_logic; - tx_data : in std_logic_vector(31 downto 0); - tx_k : in std_logic_vector(3 downto 0); - - rx_clk : out std_logic; - rx_data : out std_logic_vector(31 downto 0); - rx_k : out std_logic_vector(3 downto 0); - - rx_cdr_stable : out std_logic; - tx_pll_reset : in std_logic; - rx_pll_reset : in std_logic; - - tx_ready : out std_logic; - rx_ready : out std_logic; - - tx_active : out std_logic; - rx_active : out std_logic; - gtpowergood : out std_logic_vector(3 downto 0); - - init_done : out std_logic; - - TX_USRCLK : out std_logic + CLK_100 : in std_logic; + GTREFCLK : in std_logic; + USRCLK_FULL : out std_logic; + USRCLK_HALF : out std_logic; + + RESET_ALL : in std_logic; + RXPMARESET : in std_logic_vector(3 downto 0); + RXPCSRESET : in std_logic_vector(3 downto 0); + TXPMARESET : in std_logic_vector(3 downto 0); + TXPCSRESET : in std_logic_vector(3 downto 0); + + USRCLK_LOCKED : out std_logic; + INIT_DONE : out std_logic; + RXRESETDONE : out std_logic_vector(3 downto 0); + TXRESETDONE : out std_logic_vector(3 downto 0); + RXPMARESETDONE : out std_logic_vector(3 downto 0); + TXPMARESETDONE : out std_logic_vector(3 downto 0); + RXBYTEISALIGNED : out std_logic_vector(3 downto 0); + + RXN : in std_logic_vector(3 downto 0); + RXP : in std_logic_vector(3 downto 0); + TXN : out std_logic_vector(3 downto 0); + TXP : out std_logic_vector(3 downto 0); + + TXDATA : in std_logic_vector(31 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + + RXDATA : out std_logic_vector(31 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0) ); end entity gth_xcku_quad_x0y2_top; architecture behavioral of gth_xcku_quad_x0y2_top is - component gth_xcku_quad_x0y2_wrapper + component gth_xcku_init is + generic ( + P_FREERUN_FREQUENCY : integer := 100; + P_TX_TIMER_DURATION_US : integer := 30000; + P_RX_TIMER_DURATION_US : integer := 130000 + ); port ( - gthrxn_in : in std_logic_vector(3 downto 0); - gthrxp_in : in std_logic_vector(3 downto 0); - gthtxn_out : out std_logic_vector(3 downto 0); - gthtxp_out : out std_logic_vector(3 downto 0); - gtwiz_userclk_tx_reset_in : in std_logic; - gtwiz_userclk_tx_srcclk_out : out std_logic; - gtwiz_userclk_tx_usrclk_out : out std_logic; - gtwiz_userclk_tx_usrclk2_out : out std_logic; - gtwiz_userclk_tx_active_out : out std_logic; - gtwiz_userclk_rx_reset_in : in std_logic; - gtwiz_userclk_rx_srcclk_out : out std_logic; - gtwiz_userclk_rx_usrclk_out : out std_logic; - gtwiz_userclk_rx_usrclk2_out : out std_logic; - gtwiz_userclk_rx_active_out : out std_logic; - gtwiz_reset_clk_freerun_in : in std_logic; - gtwiz_reset_all_in : in std_logic; - gtwiz_reset_tx_pll_and_datapath_in : in std_logic; - gtwiz_reset_tx_datapath_in : in std_logic; - gtwiz_reset_rx_pll_and_datapath_in : in std_logic; - gtwiz_reset_rx_datapath_in : in std_logic; - gtwiz_reset_rx_cdr_stable_out : out std_logic; - gtwiz_reset_tx_done_out : out std_logic; - gtwiz_reset_rx_done_out : out std_logic; + clk_freerun_in : in std_logic; + reset_all_in : in std_logic; + tx_init_done_in : in std_logic; + rx_init_done_in : in std_logic; + rx_data_good_in : in std_logic; + reset_all_out : out std_logic := '0'; + reset_rx_out : out std_logic := '0'; + init_done_out : out std_logic := '0'; + retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" + ); + end component; + + component gth_xcku_quad_x0y2 + port ( + gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); + gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); + gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); + gtwiz_reset_all_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); + gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); + gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); gtwiz_userdata_tx_in : in std_logic_vector(63 downto 0); gtwiz_userdata_rx_out : out std_logic_vector(63 downto 0); - gtrefclk00_in : in std_logic; - qpll0outclk_out : out std_logic; - qpll0outrefclk_out : out std_logic; + gtrefclk00_in : in std_logic_vector(0 downto 0); + qpll0outclk_out : out std_logic_vector(0 downto 0); + qpll0outrefclk_out : out std_logic_vector(0 downto 0); + gthrxn_in : in std_logic_vector(3 downto 0); + gthrxp_in : in std_logic_vector(3 downto 0); rx8b10ben_in : in std_logic_vector(3 downto 0); rxbufreset_in : in std_logic_vector(3 downto 0); + rxcdrreset_in : in std_logic_vector(3 downto 0); rxcommadeten_in : in std_logic_vector(3 downto 0); rxmcommaalignen_in : in std_logic_vector(3 downto 0); rxpcommaalignen_in : in std_logic_vector(3 downto 0); + rxpcsreset_in : in std_logic_vector(3 downto 0); + rxpmareset_in : in std_logic_vector(3 downto 0); + rxusrclk_in : in std_logic_vector(3 downto 0); + rxusrclk2_in : in std_logic_vector(3 downto 0); tx8b10ben_in : in std_logic_vector(3 downto 0); txctrl0_in : in std_logic_vector(63 downto 0); txctrl1_in : in std_logic_vector(63 downto 0); txctrl2_in : in std_logic_vector(31 downto 0); + txpcsreset_in : in std_logic_vector(3 downto 0); + txpmareset_in : in std_logic_vector(3 downto 0); + txusrclk_in : in std_logic_vector(3 downto 0); + txusrclk2_in : in std_logic_vector(3 downto 0); + gthtxn_out : out std_logic_vector(3 downto 0); + gthtxp_out : out std_logic_vector(3 downto 0); gtpowergood_out : out std_logic_vector(3 downto 0); rxbufstatus_out : out std_logic_vector(11 downto 0); rxbyteisaligned_out : out std_logic_vector(3 downto 0); @@ -92,289 +113,314 @@ architecture behavioral of gth_xcku_quad_x0y2_top is rxctrl1_out : out std_logic_vector(63 downto 0); rxctrl2_out : out std_logic_vector(31 downto 0); rxctrl3_out : out std_logic_vector(31 downto 0); + rxoutclk_out : out std_logic_vector(3 downto 0); rxpmaresetdone_out : out std_logic_vector(3 downto 0); - txpmaresetdone_out : out std_logic_vector(3 downto 0) - ); - end component gth_xcku_quad_x0y2_wrapper; - - component gth_xcku_init is - generic ( - P_FREERUN_FREQUENCY : integer := 100; - P_TX_TIMER_DURATION_US : integer := 30000; - P_RX_TIMER_DURATION_US : integer := 130000 - ); - port ( - clk_freerun_in : in std_logic; - reset_all_in : in std_logic; - tx_init_done_in : in std_logic; - rx_init_done_in : in std_logic; - rx_data_good_in : in std_logic; - reset_all_out : out std_logic := '0'; - reset_rx_out : out std_logic := '0'; - init_done_out : out std_logic := '0'; - retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" + rxresetdone_out : out std_logic_vector(3 downto 0); + txoutclk_out : out std_logic_vector(3 downto 0); + txpmaresetdone_out : out std_logic_vector(3 downto 0); + txresetdone_out : out std_logic_vector(3 downto 0) ); end component; - signal gtpowergood_i : std_logic_vector(3 downto 0); - signal reset_rx_cdr_stable_i : std_logic; - signal reset_tx_done_i : std_logic; - signal reset_rx_done_i : std_logic; - signal userclk_tx_active_i : std_logic; - signal userclk_tx_reset_i : std_logic := '0'; - signal userclk_tx_srcclk_i : std_logic; - signal userclk_tx_usrclk_i : std_logic; - signal userclk_tx_usrclk2_i : std_logic; - signal userclk_rx_reset_i : std_logic := '0'; - signal userclk_rx_srcclk_i : std_logic; - signal userclk_rx_usrclk_i : std_logic; - signal userclk_rx_usrclk2_i : std_logic; - signal userclk_rx_active_i : std_logic; - signal reset_tx_pll_and_datapath_i : std_logic; - signal reset_tx_datapath_i : std_logic := '0'; - signal reset_rx_pll_and_datapath_i : std_logic; - signal reset_rx_datapath_i : std_logic := '0'; - signal qpll0outclk_i : std_logic; - signal qpll0outrefclk_i : std_logic; - signal txctrl0_i : std_logic_vector(63 downto 0); - signal txctrl1_i : std_logic_vector(63 downto 0); - signal txctrl2_i : std_logic_vector(31 downto 0); - signal userdata_tx_i : std_logic_vector(63 downto 0); - signal userdata_rx_i : std_logic_vector(63 downto 0); - signal rxpmaresetdone_i : std_logic_vector(3 downto 0); - signal txpmaresetdone_i : std_logic_vector(3 downto 0); - - signal rxctrl0_i : std_logic_vector(63 downto 0); - signal rxctrl1_i : std_logic_vector(63 downto 0); - signal rxctrl2_i : std_logic_vector(31 downto 0); - signal rxctrl3_i : std_logic_vector(31 downto 0); - - signal gthrxp_i : std_logic_vector(3 downto 0); - signal gthrxn_i : std_logic_vector(3 downto 0); - signal gthtxp_i : std_logic_vector(3 downto 0); - signal gthtxn_i : std_logic_vector(3 downto 0); - - signal reset_all_i : std_logic; - signal reset_all_init : std_logic; - - signal rxcommadeten_i : std_logic_vector(3 downto 0); - signal rxmcommaalignen_i : std_logic_vector(3 downto 0); - signal rxpcommaalignen_i : std_logic_vector(3 downto 0); - - signal rxcommadet_i : std_logic_vector(3 downto 0); - signal rxbyteisaligned_i : std_logic_vector(3 downto 0); - signal rxbyterealign_i : std_logic_vector(3 downto 0); - - signal init_done_i : std_logic; - signal enable_i : std_logic; - - --VIO - signal rxclkcorcnt_i : std_logic_vector(7 downto 0); - signal rxbufstatus_i : std_logic_vector(11 downto 0); - - --RX FIFO - signal rx_empty : std_logic_vector(3 downto 0); - - --TX FIFO - signal tx_fifo_full_i : std_logic_vector(3 downto 0); - signal tx_fifo_empty_i : std_logic_vector(3 downto 0); - signal tx_fifo_valid_i : std_logic_vector(3 downto 0); - signal tx_fifo_almempty_i : std_logic_vector(3 downto 0); - signal tx_fifo_almfull_i : std_logic_vector(3 downto 0); - signal tx_fifo_wr_cnt : std_logic_vector(39 downto 0); - signal tx_fifo_wren_i : std_logic_vector(3 downto 0); - - attribute MARK_DEBUG : string; - attribute MARK_DEBUG of clk_200 : signal is "TRUE"; - attribute MARK_DEBUG of tx_data : signal is "TRUE"; - attribute MARK_DEBUG of tx_k : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_full_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_almfull_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_wr_cnt : signal is "TRUE"; - attribute MARK_DEBUG of userclk_tx_usrclk2_i : signal is "TRUE"; - attribute MARK_DEBUG of reset_all : signal is "TRUE"; - attribute MARK_DEBUG of userclk_tx_active_i : signal is "TRUE"; - attribute MARK_DEBUG of reset_tx_done_i : signal is "TRUE"; - attribute MARK_DEBUG of userdata_tx_i : signal is "TRUE"; - attribute MARK_DEBUG of txctrl2_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_empty_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_valid_i : signal is "TRUE"; - attribute KEEP : string; - attribute KEEP of clk_200 : signal is "TRUE"; - attribute KEEP of tx_data : signal is "TRUE"; - attribute KEEP of tx_k : signal is "TRUE"; - attribute KEEP of tx_fifo_full_i : signal is "TRUE"; - attribute KEEP of tx_fifo_almfull_i : signal is "TRUE"; - attribute KEEP of tx_fifo_wr_cnt : signal is "TRUE"; - attribute KEEP of userclk_tx_usrclk2_i : signal is "TRUE"; - attribute KEEP of reset_all : signal is "TRUE"; - attribute KEEP of userclk_tx_active_i : signal is "TRUE"; - attribute KEEP of reset_tx_done_i : signal is "TRUE"; - attribute KEEP of userdata_tx_i : signal is "TRUE"; - attribute KEEP of txctrl2_i : signal is "TRUE"; - attribute KEEP of tx_fifo_empty_i : signal is "TRUE"; - attribute KEEP of tx_fifo_valid_i : signal is "TRUE"; + signal reset_tx_done_i : std_logic; + signal reset_rx_done_i : std_logic; + signal userclk_tx_reset_i : std_logic := '0'; + signal txpmaresetdone_i : std_logic_vector(3 downto 0); + + signal usrclk : std_logic; + signal usrclk_double : std_logic; + + signal txdata_reg : std_logic_vector(31 downto 0); + signal txcharisk_reg : std_logic_vector(3 downto 0); + signal txchardispmode_reg : std_logic_vector(3 downto 0); + signal txchardispval_reg : std_logic_vector(3 downto 0); + + signal tx16data : std_logic_vector(63 downto 0); + signal tx16charisk : std_logic_vector(7 downto 0); + signal tx16chardispmode : std_logic_vector(7 downto 0); + signal tx16chardispval : std_logic_vector(7 downto 0); + + signal rxctrl0 : std_logic_vector(63 downto 0); + signal rxctrl1 : std_logic_vector(63 downto 0); + signal rxctrl2 : std_logic_vector(31 downto 0); + signal rxctrl3 : std_logic_vector(31 downto 0); + + signal rx16data : std_logic_vector(63 downto 0); + signal rx16charisk : std_logic_vector(7 downto 0); + signal rx16chariscomma : std_logic_vector(7 downto 0); + signal rx16notintable : std_logic_vector(7 downto 0); + signal rx16disperr : std_logic_vector(7 downto 0); + + signal rx16data_reg : std_logic_vector(63 downto 0); + signal rx16charisk_reg : std_logic_vector(7 downto 0); + signal rx16chariscomma_reg : std_logic_vector(7 downto 0); + signal rx16notintable_reg : std_logic_vector(7 downto 0); + signal rx16disperr_reg : std_logic_vector(7 downto 0); + + signal rxdata_i : std_logic_vector(31 downto 0); + signal rxcharisk_i : std_logic_vector(3 downto 0); + signal rxchariscomma_i : std_logic_vector(3 downto 0); + signal rxnotintable_i : std_logic_vector(3 downto 0); + signal rxdisperr_i : std_logic_vector(3 downto 0); + + signal usrclk_toggle : std_logic := '0'; + signal usrclk_toggle_reg : std_logic := '0'; + signal usrclk_phase : std_logic := '0'; + + signal reset_all_i : std_logic; + + signal txoutclk_int : std_logic_vector(3 downto 0); + signal usrclk_int : std_logic; + + signal usrclk_mmcm_fb : std_logic; + + signal usrclk_active_meta : std_logic := '0'; + signal usrclk_active : std_logic := '0'; + signal not_usrclk_active : std_logic; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of usrclk_active_meta : signal is "true"; + attribute ASYNC_REG of usrclk_active : signal is "true"; begin - init_done <= init_done_i; - tx_clk <= userclk_tx_usrclk2_i; - txctrl0_i <= x"0000000000000000"; - txctrl1_i <= x"0000000000000000"; - txctrl2_i(7 downto 2) <= "000000"; - txctrl2_i(15 downto 10) <= "000000"; - txctrl2_i(23 downto 18) <= "000000"; - txctrl2_i(31 downto 26) <= "000000"; - - rx_clk <= userclk_rx_usrclk2_i; + USRCLK_FULL <= usrclk_double; + USRCLK_HALF <= usrclk; - rx_cdr_stable <= reset_rx_cdr_stable_i; - reset_tx_pll_and_datapath_i <= tx_pll_reset; - reset_rx_pll_and_datapath_i <= rx_pll_reset; - - tx_ready <= reset_tx_done_i; - rx_ready <= reset_rx_done_i; - - tx_active <= userclk_tx_active_i; - rx_active <= userclk_rx_active_i; - - gthrxn_i <= ch0_gthrxn_in; - gthrxp_i <= ch0_gthrxp_in; - ch0_gthtxn_out <= gthtxn_i; - ch0_gthtxp_out <= gthtxp_i; - - reset_all_init <= reset_all; userclk_tx_reset_i <= not (txpmaresetdone_i(0) and txpmaresetdone_i(1) and txpmaresetdone_i(2) and txpmaresetdone_i(3)); - userclk_rx_reset_i <= not (rxpmaresetdone_i(0) and rxpmaresetdone_i(1) - and rxpmaresetdone_i(2) and rxpmaresetdone_i(3)); - - reset_rx_datapath_i <= '0'; - reset_tx_datapath_i <= '0'; - gtpowergood <= gtpowergood_i; - - --enable Comma detection on K28.5 - rxcommadeten_i <= "1111"; - rxmcommaalignen_i <= "1111"; - rxpcommaalignen_i <= "1111"; - TX_USRCLK <= userclk_tx_usrclk2_i; + TXPMARESETDONE <= txpmaresetdone_i; THE_INIT : gth_xcku_init port map ( - clk_freerun_in => FREECLK, - reset_all_in => reset_all_init, + clk_freerun_in => CLK_100, + reset_all_in => RESET_ALL, tx_init_done_in => reset_tx_done_i, rx_init_done_in => reset_rx_done_i, rx_data_good_in => '1', reset_all_out => reset_all_i, reset_rx_out => open, - init_done_out => init_done_i, + init_done_out => INIT_DONE, retry_ctr_out => open ); - enable_i <= '1'; - generate_fifos: - for i in 0 to 3 generate + process (usrclk) is begin - THE_RX_FIFO : entity work.fifo_16x18x9_oreg - port map ( - Data(17) => rxctrl2_i(8 * i), - Data(16 downto 9) => userdata_rx_i(16 * i + 7 downto 16 * i), - Data( 8) => rxctrl2_i(8 * i + 1), - Data( 7 downto 0) => userdata_rx_i(16 * i + 15 downto 16 * i + 8), - WrClock => userclk_rx_usrclk2_i, - RdClock => clk_200, - WrEn => enable_i, - RdEn => enable_i, - Reset => reset_all, - Q(7 downto 0) => rx_data(8 * i + 7 downto 8 * i), - Q(8) => rx_k(i), - Empty => rx_empty(i), - Full => open, - AlmostEmpty => open, - AlmostFull => open - ); + if rising_edge(usrclk) then + usrclk_toggle <= not usrclk_toggle; + + rx16data_reg <= rx16data; + rx16charisk_reg <= rx16charisk; + rx16chariscomma_reg <= rx16chariscomma; + rx16notintable_reg <= rx16notintable; + rx16disperr_reg <= rx16disperr; + + for i in 0 to 3 loop + tx16data(16 * i + 15 downto 16 * i) <= TXDATA(8 * i + 7 downto 8 * i) & txdata_reg(8 * i + 7 downto 8 * i); + tx16charisk(2 * i + 1 downto 2 * i) <= TXCHARISK(i) & txcharisk_reg(i); + tx16chardispmode(2 * i + 1 downto 2 * i) <= TXCHARDISPMODE(i) & txchardispmode_reg(i); + tx16chardispval(2 * i + 1 downto 2 * i) <= TXCHARDISPVAL(i) & txchardispval_reg(i); + end loop; + end if; + end process; + + process (usrclk_double) is + begin + if rising_edge(usrclk_double) then + usrclk_toggle_reg <= usrclk_toggle; + usrclk_phase <= usrclk_toggle xor usrclk_toggle_reg; + + for i in 0 to 3 loop + if usrclk_phase = '0' then + rxdata_i(8 * i + 7 downto 8 * i) <= rx16data_reg(16 * i + 7 downto 16 * i); + rxcharisk_i(i) <= rx16charisk_reg(2 * i); + rxchariscomma_i(i) <= rx16chariscomma_reg(2 * i); + rxnotintable_i(i) <= rx16notintable_reg(2 * i); + rxdisperr_i(i) <= rx16disperr_reg(2 * i); + else + rxdata_i(8 * i + 7 downto 8 * i) <= rx16data_reg(16 * i + 15 downto 16 * i + 8); + rxcharisk_i(i) <= rx16charisk_reg(2 * i + 1); + rxchariscomma_i(i) <= rx16chariscomma_reg(2 * i + 1); + rxnotintable_i(i) <= rx16notintable_reg(2 * i + 1); + rxdisperr_i(i) <= rx16disperr_reg(2 * i + 1); + end if; + end loop; + + txdata_reg <= TXDATA; + txcharisk_reg <= TXCHARISK; + txchardispmode_reg <= TXCHARDISPMODE; + txchardispval_reg <= TXCHARDISPVAL; + end if; + end process; + + RXDATA <= rxdata_i; + RXCHARISK <= rxcharisk_i; + RXCHARISCOMMA <= rxchariscomma_i; + RXNOTINTABLE <= rxnotintable_i; + RXDISPERR <= rxdisperr_i; + + + THE_GTH : gth_xcku_quad_x0y2 + port map ( + gtwiz_userclk_tx_active_in(0) => usrclk_active, + gtwiz_userclk_rx_active_in(0) => usrclk_active, + gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_all_in(0) => reset_all_i, + gtwiz_reset_tx_pll_and_datapath_in(0) => '0', + gtwiz_reset_tx_datapath_in(0) => '0', + gtwiz_reset_rx_pll_and_datapath_in(0) => '0', + gtwiz_reset_rx_datapath_in(0) => '0', + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out(0) => reset_tx_done_i, + gtwiz_reset_rx_done_out(0) => reset_rx_done_i, + gtwiz_userdata_tx_in => tx16data, + gtwiz_userdata_rx_out => rx16data, + gtrefclk00_in(0) => GTREFCLK, + qpll0outclk_out => open, + qpll0outrefclk_out => open, + gthrxn_in => RXN, + gthrxp_in => RXP, + rx8b10ben_in => "1111", + rxbufreset_in => "0000", + rxcdrreset_in => "0000", + rxcommadeten_in => "1111", + rxmcommaalignen_in => "1111", + rxpcommaalignen_in => "1111", + rxpcsreset_in => RXPCSRESET, + rxpmareset_in => RXPMARESET, + rxusrclk_in(0) => usrclk_int, + rxusrclk_in(1) => usrclk_int, + rxusrclk_in(2) => usrclk_int, + rxusrclk_in(3) => usrclk_int, + rxusrclk2_in(0) => usrclk_int, + rxusrclk2_in(1) => usrclk_int, + rxusrclk2_in(2) => usrclk_int, + rxusrclk2_in(3) => usrclk_int, + tx8b10ben_in => "1111", + txctrl0_in(63 downto 8) => x"00000000000000", + txctrl0_in(7 downto 0) => tx16chardispval, + txctrl1_in(63 downto 8) => x"00000000000000", + txctrl1_in(7 downto 0) => tx16chardispmode, + txctrl2_in(31 downto 8) => x"000000", + txctrl2_in(7 downto 0) => tx16charisk, + txpcsreset_in => TXPCSRESET, + txpmareset_in => TXPMARESET, + txusrclk_in(0) => usrclk_int, + txusrclk_in(1) => usrclk_int, + txusrclk_in(2) => usrclk_int, + txusrclk_in(3) => usrclk_int, + txusrclk2_in(0) => usrclk_int, + txusrclk2_in(1) => usrclk_int, + txusrclk2_in(2) => usrclk_int, + txusrclk2_in(3) => usrclk_int, + gthtxn_out => TXN, + gthtxp_out => TXP, + gtpowergood_out => open, + rxbufstatus_out => open, + rxbyteisaligned_out => RXBYTEISALIGNED, + rxbyterealign_out => open, + rxclkcorcnt_out => open, + rxcommadet_out => open, + rxctrl0_out => rxctrl0, + rxctrl1_out => rxctrl1, + rxctrl2_out => rxctrl2, + rxctrl3_out => rxctrl3, + rxoutclk_out => open, + rxpmaresetdone_out => RXPMARESETDONE, + rxresetdone_out => RXRESETDONE, + txoutclk_out => txoutclk_int, + txpmaresetdone_out => txpmaresetdone_i, + txresetdone_out => TXRESETDONE + ); + + rx16charisk <= rxctrl0(7 downto 0); + rx16notintable <= rxctrl1(7 downto 0); + rx16chariscomma <= rxctrl2(7 downto 0); + rx16disperr <= rxctrl3(7 downto 0); + + bufg_gt_usrclk_inst : BUFG_GT + port map ( + O => usrclk_int, + CE => '1', + CEMASK => '0', + CLR => userclk_tx_reset_i, + CLRMASK => '0', + DIV => "000", + I => txoutclk_int(0) + ); - THE_TX_FIFO : entity work.fifo_1024x9x18_oreg_wcnt - port map ( - Data(8) => tx_k(i), - Data(7 downto 0) => tx_data(8 * i + 7 downto 8 * i), - WrClock => clk_200, - RdClock => userclk_tx_usrclk2_i, - WrEn => tx_fifo_wren_i(i), - RdEn => enable_i, - Reset => reset_all, - Q( 7 downto 0) => userdata_tx_i(16 * i + 15 downto 16 * i + 8), - Q( 8) => txctrl2_i(8 * i + 1), - Q(16 downto 9) => userdata_tx_i(16 * i + 7 downto 16 * i), - Q(17) => txctrl2_i(8 * i), - WCNT => tx_fifo_wr_cnt(10 * i + 9 downto 10 * i), - Empty => tx_fifo_empty_i(i), - Full => tx_fifo_full_i(i), - AlmostEmpty => tx_fifo_almempty_i(i), - AlmostFull => tx_fifo_almfull_i(i) - ); - process (userclk_tx_usrclk2_i) is - begin - if rising_edge(userclk_tx_usrclk2_i) then - tx_fifo_valid_i(i) <= enable_i and not tx_fifo_empty_i(i); - end if; - end process; - - tx_fifo_wren_i(i) <= userclk_tx_active_i and reset_tx_done_i; - end generate generate_fifos; - - THE_GTH : gth_xcku_quad_x0y2_wrapper - port map( - gthrxn_in => gthrxn_i, - gthrxp_in => gthrxp_i, - gthtxn_out => gthtxn_i, - gthtxp_out => gthtxp_i, - gtwiz_userclk_tx_reset_in => userclk_tx_reset_i, - gtwiz_userclk_tx_srcclk_out => userclk_tx_srcclk_i, - gtwiz_userclk_tx_usrclk_out => userclk_tx_usrclk_i, - gtwiz_userclk_tx_usrclk2_out => userclk_tx_usrclk2_i, - gtwiz_userclk_tx_active_out => userclk_tx_active_i, - gtwiz_userclk_rx_reset_in => userclk_rx_reset_i, - gtwiz_userclk_rx_srcclk_out => userclk_rx_srcclk_i, - gtwiz_userclk_rx_usrclk_out => userclk_rx_usrclk_i, - gtwiz_userclk_rx_usrclk2_out => userclk_rx_usrclk2_i, - gtwiz_userclk_rx_active_out => userclk_rx_active_i, - gtwiz_reset_clk_freerun_in => FREECLK, - gtwiz_reset_all_in => reset_all_i, - gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_i, - gtwiz_reset_tx_datapath_in => reset_tx_datapath_i, - gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_i, - gtwiz_reset_rx_datapath_in => reset_rx_datapath_i, - gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_i, - gtwiz_reset_tx_done_out => reset_tx_done_i, - gtwiz_reset_rx_done_out => reset_rx_done_i, - gtwiz_userdata_tx_in => userdata_tx_i, - gtwiz_userdata_rx_out => userdata_rx_i, - gtrefclk00_in => mgtrefclk0_x0y3_int, - qpll0outclk_out => qpll0outclk_i, - qpll0outrefclk_out => qpll0outrefclk_i, - rx8b10ben_in => "1111", - rxbufreset_in => "0000", - rxcommadeten_in => rxcommadeten_i, - rxmcommaalignen_in => rxmcommaalignen_i, - rxpcommaalignen_in => rxpcommaalignen_i, - tx8b10ben_in => "1111", - txctrl0_in => txctrl0_i, - txctrl1_in => txctrl1_i, - txctrl2_in => txctrl2_i, - gtpowergood_out => gtpowergood_i, - rxbufstatus_out => rxbufstatus_i, - rxbyteisaligned_out => rxbyteisaligned_i, - rxbyterealign_out => rxbyterealign_i, - rxclkcorcnt_out => rxclkcorcnt_i, - rxcommadet_out => rxcommadet_i, - rxctrl0_out => rxctrl0_i, - rxctrl1_out => rxctrl1_i, - rxctrl2_out => rxctrl2_i, - rxctrl3_out => rxctrl3_i, - rxpmaresetdone_out => rxpmaresetdone_i, - txpmaresetdone_out => txpmaresetdone_i + -- Indicate active helper block functionality when the BUFG_GT divider is + -- not held in reset + process (userclk_tx_reset_i, usrclk_int) is + begin + if userclk_tx_reset_i = '1' then + usrclk_active_meta <= '0'; + usrclk_active <= '0'; + elsif rising_edge(usrclk_int) then + usrclk_active_meta <= '1'; + usrclk_active <= usrclk_active_meta; + end if; + end process; + + not_usrclk_active <= not usrclk_active; + + + mmcme3_adv_usrclk : MMCME3_ADV + generic map ( + BANDWIDTH => "OPTIMIZED", + CLKOUT4_CASCADE => "FALSE", + COMPENSATION => "AUTO", + STARTUP_WAIT => "FALSE", + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT_F => 10.000, + CLKFBOUT_PHASE => 0.000, + CLKFBOUT_USE_FINE_PS => "FALSE", + CLKOUT0_DIVIDE_F => 10.000, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT0_USE_FINE_PS => "FALSE", + CLKOUT1_DIVIDE => 5, + CLKOUT1_PHASE => 0.000, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT1_USE_FINE_PS => "FALSE", + CLKIN1_PERIOD => 10.000 + ) + port map ( + CLKFBOUT => usrclk_mmcm_fb, + CLKFBOUTB => open, + CLKOUT0 => usrclk, + CLKOUT0B => open, + CLKOUT1 => usrclk_double, + CLKOUT1B => open, + CLKOUT2 => open, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBIN => usrclk_mmcm_fb, + CLKIN1 => usrclk_int, + CLKIN2 => '0', + CLKINSEL => '1', + DADDR => "0000000", + DCLK => '0', + DEN => '0', + DI => x"0000", + DO => open, + DRDY => open, + DWE => '0', + CDDCDONE => open, + CDDCREQ => '0', + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => open, + LOCKED => USRCLK_LOCKED, + CLKINSTOPPED => open, + CLKFBSTOPPED => open, + PWRDWN => '0', + RST => not_usrclk_active ); end architecture behavioral; diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_wrapper.v b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_wrapper.v deleted file mode 100644 index 0f77c01..0000000 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_wrapper.v +++ /dev/null @@ -1,263 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - - -`timescale 1ps/1ps - -// ===================================================================================================================== -// This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from -// the core, connects them as appropriate, and maps enabled ports -// ===================================================================================================================== - -module gth_xcku_quad_x0y2_wrapper ( - input wire [3:0] gthrxn_in - ,input wire [3:0] gthrxp_in - ,output wire [3:0] gthtxn_out - ,output wire [3:0] gthtxp_out - ,input wire [0:0] gtwiz_userclk_tx_reset_in - ,output wire [0:0] gtwiz_userclk_tx_srcclk_out - ,output wire [0:0] gtwiz_userclk_tx_usrclk_out - ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out - ,output wire [0:0] gtwiz_userclk_tx_active_out - ,input wire [0:0] gtwiz_userclk_rx_reset_in - ,output wire [0:0] gtwiz_userclk_rx_srcclk_out - ,output wire [0:0] gtwiz_userclk_rx_usrclk_out - ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out - ,output wire [0:0] gtwiz_userclk_rx_active_out - ,input wire [0:0] gtwiz_reset_clk_freerun_in - ,input wire [0:0] gtwiz_reset_all_in - ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in - ,input wire [0:0] gtwiz_reset_tx_datapath_in - ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in - ,input wire [0:0] gtwiz_reset_rx_datapath_in - ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out - ,output wire [0:0] gtwiz_reset_tx_done_out - ,output wire [0:0] gtwiz_reset_rx_done_out - ,input wire [63:0] gtwiz_userdata_tx_in - ,output wire [63:0] gtwiz_userdata_rx_out - ,input wire [0:0] gtrefclk00_in - ,output wire [0:0] qpll0outclk_out - ,output wire [0:0] qpll0outrefclk_out - ,input wire [3:0] rx8b10ben_in - ,input wire [3:0] rxbufreset_in - ,input wire [3:0] rxcommadeten_in - ,input wire [3:0] rxmcommaalignen_in - ,input wire [3:0] rxpcommaalignen_in - ,input wire [3:0] tx8b10ben_in - ,input wire [63:0] txctrl0_in - ,input wire [63:0] txctrl1_in - ,input wire [31:0] txctrl2_in - ,output wire [3:0] gtpowergood_out - ,output wire [11:0] rxbufstatus_out - ,output wire [3:0] rxbyteisaligned_out - ,output wire [3:0] rxbyterealign_out - ,output wire [7:0] rxclkcorcnt_out - ,output wire [3:0] rxcommadet_out - ,output wire [63:0] rxctrl0_out - ,output wire [63:0] rxctrl1_out - ,output wire [31:0] rxctrl2_out - ,output wire [31:0] rxctrl3_out - ,output wire [3:0] rxpmaresetdone_out - ,output wire [3:0] txpmaresetdone_out -); - - - // =================================================================================================================== - // PARAMETERS AND FUNCTIONS - // =================================================================================================================== - - // Declare and initialize local parameters and functions used for HDL generation - localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000; - `include "gth_xcku_wrapper_functions.v" - localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); - localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); - - - // =================================================================================================================== - // HELPER BLOCKS - // =================================================================================================================== - - // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal - // assignments related to optionally-enabled ports may appear below. - - // ------------------------------------------------------------------------------------------------------------------- - // Transmitter user clocking network helper block - // ------------------------------------------------------------------------------------------------------------------- - - wire [3:0] txusrclk_int; - wire [3:0] txusrclk2_int; - wire [3:0] txoutclk_int; - - // Generate a single module instance which is driven by a clock source associated with the master transmitter channel, - // and which drives TXUSRCLK and TXUSRCLK2 for all channels - - // The source clock is TXOUTCLK from the master transmitter channel - assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX]; - - // Instantiate a single instance of the transmitter user clocking network helper block - gtwizard_ultrascale_v1_7_8_gtwiz_userclk_tx gtwiz_userclk_tx_inst ( - .gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out), - .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in), - .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out), - .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out), - .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out) - ); - - // Drive TXUSRCLK and TXUSRCLK2 for all channels with the respective helper block outputs - assign txusrclk_int = {4{gtwiz_userclk_tx_usrclk_out}}; - assign txusrclk2_int = {4{gtwiz_userclk_tx_usrclk2_out}}; - - // ------------------------------------------------------------------------------------------------------------------- - // Receiver user clocking network helper block - // ------------------------------------------------------------------------------------------------------------------- - - wire [3:0] rxusrclk_int; - wire [3:0] rxusrclk2_int; - wire [3:0] rxoutclk_int; - - // Generate a single module instance which is driven by a clock source associated with the master receiver channel, - // and which drives RXUSRCLK and RXUSRCLK2 for all channels - - // The source clock is RXOUTCLK from the master receiver channel - assign gtwiz_userclk_rx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX]; - - // Instantiate a single instance of the receiver user clocking network helper block - gtwizard_ultrascale_v1_7_8_gtwiz_userclk_rx gtwiz_userclk_rx_inst ( - .gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out), - .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in), - .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out), - .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out), - .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out) - ); - - // Drive RXUSRCLK and RXUSRCLK2 for all channels with the respective helper block outputs - assign rxusrclk_int = {4{gtwiz_userclk_rx_usrclk_out}}; - assign rxusrclk2_int = {4{gtwiz_userclk_rx_usrclk2_out}}; - wire [3:0] gtpowergood_int; - - // Required assignment to expose the GTPOWERGOOD port per user request - assign gtpowergood_out = gtpowergood_int; - - // ---------------------------------------------------------------------------------------------------------------- - // Assignments to expose data ports, or data control ports, per configuration requirement or user request - // ---------------------------------------------------------------------------------------------------------------- - - wire [63:0] txctrl0_int; - - // Required assignment to expose the TXCTRL0 port per configuration requirement or user request - assign txctrl0_int = txctrl0_in; - wire [63:0] txctrl1_int; - - // Required assignment to expose the TXCTRL1 port per configuration requirement or user request - assign txctrl1_int = txctrl1_in; - wire [63:0] rxctrl0_int; - - // Required assignment to expose the RXCTRL0 port per configuration requirement or user request - assign rxctrl0_out = rxctrl0_int; - wire [63:0] rxctrl1_int; - - // Required assignment to expose the RXCTRL1 port per configuration requirement or user request - assign rxctrl1_out = rxctrl1_int; - - - // =================================================================================================================== - // CORE INSTANCE - // =================================================================================================================== - - // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate - gth_xcku_quad_x0y2 gth_xcku_quad_x0y2_inst ( - .gthrxn_in (gthrxn_in) - ,.gthrxp_in (gthrxp_in) - ,.gthtxn_out (gthtxn_out) - ,.gthtxp_out (gthtxp_out) - ,.gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_out) - ,.gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_out) - ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in) - ,.gtwiz_reset_all_in (gtwiz_reset_all_in) - ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in) - ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in) - ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in) - ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in) - ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out) - ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out) - ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out) - ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in) - ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out) - ,.gtrefclk00_in (gtrefclk00_in) - ,.qpll0outclk_out (qpll0outclk_out) - ,.qpll0outrefclk_out (qpll0outrefclk_out) - ,.rx8b10ben_in (rx8b10ben_in) - ,.rxbufreset_in (rxbufreset_in) - ,.rxcommadeten_in (rxcommadeten_in) - ,.rxmcommaalignen_in (rxmcommaalignen_in) - ,.rxpcommaalignen_in (rxpcommaalignen_in) - ,.rxusrclk_in (rxusrclk_int) - ,.rxusrclk2_in (rxusrclk2_int) - ,.tx8b10ben_in (tx8b10ben_in) - ,.txctrl0_in (txctrl0_int) - ,.txctrl1_in (txctrl1_int) - ,.txctrl2_in (txctrl2_in) - ,.txusrclk_in (txusrclk_int) - ,.txusrclk2_in (txusrclk2_int) - ,.gtpowergood_out (gtpowergood_int) - ,.rxbufstatus_out (rxbufstatus_out) - ,.rxbyteisaligned_out (rxbyteisaligned_out) - ,.rxbyterealign_out (rxbyterealign_out) - ,.rxclkcorcnt_out (rxclkcorcnt_out) - ,.rxcommadet_out (rxcommadet_out) - ,.rxctrl0_out (rxctrl0_int) - ,.rxctrl1_out (rxctrl1_int) - ,.rxctrl2_out (rxctrl2_out) - ,.rxctrl3_out (rxctrl3_out) - ,.rxoutclk_out (rxoutclk_int) - ,.rxpmaresetdone_out (rxpmaresetdone_out) - ,.txoutclk_out (txoutclk_int) - ,.txpmaresetdone_out (txpmaresetdone_out) -); - -endmodule diff --git a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci index 6cfdeda..cce5250 100644 --- a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci +++ b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci @@ -39,17 +39,17 @@ 1 0 "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - "00110000" + "00000000" 1 - "00100010" + "00000010" 2 - 2 + 1 5000 - "00000000000000000000001011110000010100000000000000000000000000101111000001010000" + "00000000000000000000000000000000000000000000000000000000000000101111000001010000" 1 - "0101111100" + "1010000011" 1 - "1010000011" + "0101111100" 1 1 20 @@ -105,7 +105,7 @@ gth_xcku_x0y8 0 0 - + rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out 100 BOTH 0 @@ -651,10 +651,10 @@ -1 -1 -1 - 12 + 13 0 None - 9 + 8 100.0000000 1 1 @@ -722,23 +722,23 @@ 00000000 00000000 00000000 - 00110000 + 00000000 false false false false - true - true + false + false false false - 00100010 - DISABLE + 00000010 + ENABLE false true false false false - true + false false false 2 @@ -751,27 +751,27 @@ false false false - 2 + 1 5000 ENABLE 0 - 00000000000000000000001011110000010100000000000000000000000000101111000001010000 + 00000000000000000000000000000000000000000000000000000000000000101111000001010000 01010000 10111100 00000000 00000000 - 01010000 - 10111100 + 00000000 + 00000000 00000000 00000000 - 1 + 2 false - 0011111111 + 1111111111 true - 0101111100 - NONE + 1010000011 + K28.5 true - 1010000011 + 0101111100 true 0 AC @@ -1044,7 +1044,7 @@ false false false - false + true false false false @@ -1165,7 +1165,7 @@ false false true - false + true false false false @@ -1175,7 +1175,7 @@ false false false - false + true true false false @@ -1195,7 +1195,7 @@ false false false - false + true false false false @@ -1280,7 +1280,7 @@ false false false - false + true false false false @@ -1299,7 +1299,7 @@ false false false - false + true true false false @@ -1318,7 +1318,7 @@ false false false - false + true false false false @@ -1378,23 +1378,20 @@ + - - + - - - + - + - diff --git a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml index 9bc32ad..8cb06cd 100644 --- a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml +++ b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml @@ -14,7 +14,7 @@ outputProductCRC - 9:dfbfd79b + 9:f9a6829c @@ -6217,13 +6217,13 @@ - 0x0 + 0 - false + true @@ -8545,13 +8545,13 @@ - 0x0 + 0 - false + true @@ -8753,13 +8753,13 @@ - 0x0 + 0 - false + true @@ -10280,13 +10280,13 @@ - 0x0 + 0 - false + true @@ -10722,13 +10722,13 @@ - 0x0 + 0 - false + true @@ -13406,7 +13406,7 @@ - false + true @@ -14033,7 +14033,7 @@ - false + true @@ -14218,7 +14218,7 @@ C_RX_CC_DISP - "00110000" + "00000000" C_RX_CC_ENABLE @@ -14230,7 +14230,7 @@ C_RX_CC_K - "00100010" + "00000010" C_RX_CC_LEN_SEQ @@ -14238,7 +14238,7 @@ C_RX_CC_NUM_SEQ - 2 + 1 C_RX_CC_PERIODICITY @@ -14246,7 +14246,7 @@ C_RX_CC_VAL - "00000000000000000000001011110000010100000000000000000000000000101111000001010000" + "00000000000000000000000000000000000000000000000000000000000000101111000001010000" C_RX_COMMA_M_ENABLE @@ -14254,7 +14254,7 @@ C_RX_COMMA_M_VAL - "0101111100" + "1010000011" C_RX_COMMA_P_ENABLE @@ -14262,7 +14262,7 @@ C_RX_COMMA_P_VAL - "1010000011" + "0101111100" C_RX_DATA_DECODING @@ -15572,7 +15572,7 @@ RX_COMMA_PRESET Comma value preset - NONE + K28.5 RX_COMMA_VALID_ONLY @@ -15602,25 +15602,25 @@ RX_COMMA_P_VAL Plus comma value Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 1010000011 + 0101111100 RX_COMMA_M_VAL Minus comma value Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 0101111100 + 1010000011 RX_COMMA_MASK Mask Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 0011111111 + 1111111111 RX_COMMA_ALIGN_WORD Alignment boundary Select which data byte boundaries are allowed for comma alignment - 1 + 2 RX_COMMA_SHOW_REALIGN_ENABLE @@ -16150,7 +16150,7 @@ RX_CC_NUM_SEQ Enable and select number of sequences to use Select whether to enable clock correction, and how many sequences to use if enabled - 2 + 1 RX_CC_LEN_SEQ @@ -16168,7 +16168,7 @@ RX_CC_KEEP_IDLE Keep idle Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - DISABLE + ENABLE RX_CC_PRECEDENCE @@ -16204,11 +16204,11 @@ RX_CC_VAL - 00000000000000000000001011110000010100000000000000000000000000101111000001010000 + 00000000000000000000000000000000000000000000000000000000000000101111000001010000 RX_CC_K - 00100010 + 00000010 @@ -16219,7 +16219,7 @@ RX_CC_DISP - 00110000 + 00000000 @@ -16385,48 +16385,104 @@ Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false + + + + false + + + RX_CC_VAL_1_0 Value Specify the value for this clock correction sequence and pattern - 01010000 + 00000000 + + + + false + + + RX_CC_K_1_0 K character Indicate whether or not the corresponding clock correction value is a K character false + + + + false + + + RX_CC_DISP_1_0 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - true + false + + + + false + + + RX_CC_MASK_1_1 Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false + + + + false + + + RX_CC_VAL_1_1 Value Specify the value for this clock correction sequence and pattern - 10111100 + 00000000 + + + + false + + + RX_CC_K_1_1 K character Indicate whether or not the corresponding clock correction value is a K character - true + false + + + + false + + + RX_CC_DISP_1_1 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - true + false + + + + false + + + RX_CC_MASK_1_2 @@ -16536,7 +16592,7 @@ ENABLE_OPTIONAL_PORTS Enable optional ports Indicate whether a port should be included - + rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out RX_REFCLK_SOURCE @@ -16649,7 +16705,7 @@ INTERNAL_PORT_ENABLEMENT_UPDATED - 12 + 13 @@ -16682,7 +16738,7 @@ INTERNAL_RX_COMMA_PRESET_UPDATE - 9 + 8 @@ -22712,23 +22768,20 @@ UltraScale FPGAs Transceivers Wizard 8 + - - + - - - + - + - diff --git a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd index d091ac7..59715c1 100644 --- a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd +++ b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd @@ -6,97 +6,44 @@ use unisim.vcomponents.all; entity gth_xcku_x0y8_top is port ( - clk_100 : in std_logic; - clk_200 : in std_logic; - reset_all : in std_logic; - mgtrefclk0_x0y3_int : in std_logic; - FREECLK : in std_logic; - - ch0_gthrxn_in : in std_logic; - ch0_gthrxp_in : in std_logic; - ch0_gthtxn_out : out std_logic; - ch0_gthtxp_out : out std_logic; - - tx_clk : out std_logic; - tx_data : in std_logic_vector(7 downto 0); - tx_k : in std_logic; - - rx_clk : out std_logic; - rx_data : out std_logic_vector(7 downto 0); - rx_k : out std_logic; - - rx_cdr_stable : out std_logic; - tx_pll_reset : in std_logic; - rx_pll_reset : in std_logic; - - tx_ready : out std_logic; - rx_ready : out std_logic; - - tx_active : out std_logic; - rx_active : out std_logic; - gtpowergood : out std_logic; - - init_done : out std_logic; - - TX_USRCLK : out std_logic + CLK_100 : in std_logic; + GTREFCLK : in std_logic; + USRCLK_FULL : out std_logic; + USRCLK_HALF : out std_logic; + + RESET_ALL : in std_logic; + RXPMARESET : in std_logic; + RXPCSRESET : in std_logic; + TXPMARESET : in std_logic; + TXPCSRESET : in std_logic; + + USRCLK_LOCKED : out std_logic; + INIT_DONE : out std_logic; + RXRESETDONE : out std_logic; + TXRESETDONE : out std_logic; + RXPMARESETDONE : out std_logic; + TXPMARESETDONE : out std_logic; + RXBYTEISALIGNED : out std_logic; + + RXN : in std_logic; + RXP : in std_logic; + TXN : out std_logic; + TXP : out std_logic; + + TXDATA : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic; + TXCHARDISPMODE : in std_logic; + TXCHARDISPVAL : in std_logic; + + RXDATA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic; + RXCHARISCOMMA : out std_logic; + RXNOTINTABLE : out std_logic; + RXDISPERR : out std_logic ); end entity gth_xcku_x0y8_top; architecture behavioral of gth_xcku_x0y8_top is - component gth_xcku_x0y8_wrapper - port ( - gthrxn_in : in std_logic; - gthrxp_in : in std_logic; - gthtxn_out : out std_logic; - gthtxp_out : out std_logic; - gtwiz_userclk_tx_reset_in : in std_logic; - gtwiz_userclk_tx_srcclk_out : out std_logic; - gtwiz_userclk_tx_usrclk_out : out std_logic; - gtwiz_userclk_tx_usrclk2_out : out std_logic; - gtwiz_userclk_tx_active_out : out std_logic; - gtwiz_userclk_rx_reset_in : in std_logic; - gtwiz_userclk_rx_srcclk_out : out std_logic; - gtwiz_userclk_rx_usrclk_out : out std_logic; - gtwiz_userclk_rx_usrclk2_out : out std_logic; - gtwiz_userclk_rx_active_out : out std_logic; - gtwiz_reset_clk_freerun_in : in std_logic; - gtwiz_reset_all_in : in std_logic; - gtwiz_reset_tx_pll_and_datapath_in : in std_logic; - gtwiz_reset_tx_datapath_in : in std_logic; - gtwiz_reset_rx_pll_and_datapath_in : in std_logic; - gtwiz_reset_rx_datapath_in : in std_logic; - gtwiz_reset_rx_cdr_stable_out : out std_logic; - gtwiz_reset_tx_done_out : out std_logic; - gtwiz_reset_rx_done_out : out std_logic; - gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); - gtrefclk00_in : in std_logic; - qpll0outclk_out : out std_logic; - qpll0outrefclk_out : out std_logic; - rx8b10ben_in : in std_logic; - rxbufreset_in : in std_logic; - rxcommadeten_in : in std_logic; - rxmcommaalignen_in : in std_logic; - rxpcommaalignen_in : in std_logic; - tx8b10ben_in : in std_logic; - txctrl0_in : in std_logic_vector(15 downto 0); - txctrl1_in : in std_logic_vector(15 downto 0); - txctrl2_in : in std_logic_vector(7 downto 0); - gtpowergood_out : out std_logic; - rxbufstatus_out : out std_logic_vector(2 downto 0); - rxbyteisaligned_out : out std_logic; - rxbyterealign_out : out std_logic; - rxclkcorcnt_out : out std_logic_vector(1 downto 0); - rxcommadet_out : out std_logic; - rxctrl0_out : out std_logic_vector(15 downto 0); - rxctrl1_out : out std_logic_vector(15 downto 0); - rxctrl2_out : out std_logic_vector(7 downto 0); - rxctrl3_out : out std_logic_vector(7 downto 0); - rxpmaresetdone_out : out std_logic; - txpmaresetdone_out : out std_logic - ); - end component; - component gth_xcku_init is generic ( P_FREERUN_FREQUENCY : integer := 100; @@ -116,255 +63,347 @@ architecture behavioral of gth_xcku_x0y8_top is ); end component; - signal gtpowergood_i : std_logic; - signal reset_rx_cdr_stable_i : std_logic; - signal reset_tx_done_i : std_logic; - signal reset_rx_done_i : std_logic; - signal userclk_tx_active_i : std_logic; - signal userclk_tx_reset_i : std_logic := '0'; - signal userclk_tx_srcclk_i : std_logic; - signal userclk_tx_usrclk_i : std_logic; - signal userclk_tx_usrclk2_i : std_logic; - signal userclk_rx_reset_i : std_logic := '0'; - signal userclk_rx_srcclk_i : std_logic; - signal userclk_rx_usrclk_i : std_logic; - signal userclk_rx_usrclk2_i : std_logic; - signal userclk_rx_active_i : std_logic; - signal reset_tx_pll_and_datapath_i : std_logic; - signal reset_tx_datapath_i : std_logic := '0'; - signal reset_rx_pll_and_datapath_i : std_logic; - signal reset_rx_datapath_i : std_logic := '0'; - signal qpll0outclk_i : std_logic; - signal qpll0outrefclk_i : std_logic; - signal txctrl0_i : std_logic_vector(15 downto 0); - signal txctrl1_i : std_logic_vector(15 downto 0); - signal txctrl2_i : std_logic_vector(7 downto 0); - signal userdata_tx_i : std_logic_vector(15 downto 0); - signal userdata_rx_i : std_logic_vector(15 downto 0); - signal rxpmaresetdone_i : std_logic; - signal txpmaresetdone_i : std_logic; - - signal rxctrl0_i : std_logic_vector(15 downto 0); - signal rxctrl1_i : std_logic_vector(15 downto 0); - signal rxctrl2_i : std_logic_vector(7 downto 0); - signal rxctrl3_i : std_logic_vector(7 downto 0); - - signal gthrxp_i : std_logic; - signal gthrxn_i : std_logic; - signal gthtxp_i : std_logic; - signal gthtxn_i : std_logic; - - signal reset_all_i : std_logic; - signal reset_all_init : std_logic; - - signal rxcommadeten_i : std_logic; - signal rxmcommaalignen_i : std_logic; - signal rxpcommaalignen_i : std_logic; - - signal rxcommadet_i : std_logic; - signal rxbyteisaligned_i : std_logic; - signal rxbyterealign_i : std_logic; - - signal init_done_i : std_logic; - signal enable_i : std_logic; - - --VIO - signal rxclkcorcnt_i : std_logic_vector(1 downto 0); - signal rxbufstatus_i : std_logic_vector(2 downto 0); - - --RX FIFO - signal rx_empty : std_logic; - - --TX FIFO - signal tx_fifo_full_i : std_logic; - signal tx_fifo_empty_i : std_logic; - signal tx_fifo_valid_i : std_logic; - signal tx_fifo_almempty_i : std_logic; - signal tx_fifo_almfull_i : std_logic; - signal tx_fifo_wr_cnt : std_logic_vector( 9 downto 0); - signal tx_fifo_wren_i : std_logic; - - attribute MARK_DEBUG : string; - attribute MARK_DEBUG of clk_200 : signal is "TRUE"; - attribute MARK_DEBUG of tx_data : signal is "TRUE"; - attribute MARK_DEBUG of tx_k : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_full_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_almfull_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_wr_cnt : signal is "TRUE"; - attribute MARK_DEBUG of userclk_tx_usrclk2_i : signal is "TRUE"; - attribute MARK_DEBUG of reset_all : signal is "TRUE"; - attribute MARK_DEBUG of userclk_tx_active_i : signal is "TRUE"; - attribute MARK_DEBUG of reset_tx_done_i : signal is "TRUE"; - attribute MARK_DEBUG of userdata_tx_i : signal is "TRUE"; - attribute MARK_DEBUG of txctrl2_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_empty_i : signal is "TRUE"; - attribute MARK_DEBUG of tx_fifo_valid_i : signal is "TRUE"; - attribute KEEP : string; - attribute KEEP of clk_200 : signal is "TRUE"; - attribute KEEP of tx_data : signal is "TRUE"; - attribute KEEP of tx_k : signal is "TRUE"; - attribute KEEP of tx_fifo_full_i : signal is "TRUE"; - attribute KEEP of tx_fifo_almfull_i : signal is "TRUE"; - attribute KEEP of tx_fifo_wr_cnt : signal is "TRUE"; - attribute KEEP of userclk_tx_usrclk2_i : signal is "TRUE"; - attribute KEEP of reset_all : signal is "TRUE"; - attribute KEEP of userclk_tx_active_i : signal is "TRUE"; - attribute KEEP of reset_tx_done_i : signal is "TRUE"; - attribute KEEP of userdata_tx_i : signal is "TRUE"; - attribute KEEP of txctrl2_i : signal is "TRUE"; - attribute KEEP of tx_fifo_empty_i : signal is "TRUE"; - attribute KEEP of tx_fifo_valid_i : signal is "TRUE"; -begin - init_done <= init_done_i; - tx_clk <= userclk_tx_usrclk2_i; - txctrl0_i <= x"0000"; - txctrl1_i <= x"0000"; - txctrl2_i(7 downto 2) <= "000000"; - - rx_clk <= userclk_rx_usrclk2_i; - - rx_cdr_stable <= reset_rx_cdr_stable_i; - reset_tx_pll_and_datapath_i <= tx_pll_reset; - reset_rx_pll_and_datapath_i <= rx_pll_reset; - - tx_ready <= reset_tx_done_i; - rx_ready <= reset_rx_done_i; - - tx_active <= userclk_tx_active_i; - rx_active <= userclk_rx_active_i; - - gthrxn_i <= ch0_gthrxn_in; - gthrxp_i <= ch0_gthrxp_in; - ch0_gthtxn_out <= gthtxn_i; - ch0_gthtxp_out <= gthtxp_i; - - reset_all_init <= reset_all; - userclk_tx_reset_i <= not (txpmaresetdone_i); --AND over all - userclk_rx_reset_i <= not (rxpmaresetdone_i); --AND over all + component gth_xcku_x0y8 + port ( + gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); + gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); + gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); + gtwiz_reset_all_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); + gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); + gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); + gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); + gtrefclk00_in : in std_logic_vector(0 downto 0); + qpll0outclk_out : out std_logic_vector(0 downto 0); + qpll0outrefclk_out : out std_logic_vector(0 downto 0); + gthrxn_in : in std_logic_vector(0 downto 0); + gthrxp_in : in std_logic_vector(0 downto 0); + rx8b10ben_in : in std_logic_vector(0 downto 0); + rxbufreset_in : in std_logic_vector(0 downto 0); + rxcdrreset_in : in std_logic_vector(0 downto 0); + rxcommadeten_in : in std_logic_vector(0 downto 0); + rxmcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcsreset_in : in std_logic_vector(0 downto 0); + rxpmareset_in : in std_logic_vector(0 downto 0); + rxusrclk_in : in std_logic_vector(0 downto 0); + rxusrclk2_in : in std_logic_vector(0 downto 0); + tx8b10ben_in : in std_logic_vector(0 downto 0); + txctrl0_in : in std_logic_vector(15 downto 0); + txctrl1_in : in std_logic_vector(15 downto 0); + txctrl2_in : in std_logic_vector(7 downto 0); + txpcsreset_in : in std_logic_vector(0 downto 0); + txpmareset_in : in std_logic_vector(0 downto 0); + txusrclk_in : in std_logic_vector(0 downto 0); + txusrclk2_in : in std_logic_vector(0 downto 0); + gthtxn_out : out std_logic_vector(0 downto 0); + gthtxp_out : out std_logic_vector(0 downto 0); + gtpowergood_out : out std_logic_vector(0 downto 0); + rxbufstatus_out : out std_logic_vector(2 downto 0); + rxbyteisaligned_out : out std_logic_vector(0 downto 0); + rxbyterealign_out : out std_logic_vector(0 downto 0); + rxclkcorcnt_out : out std_logic_vector(1 downto 0); + rxcommadet_out : out std_logic_vector(0 downto 0); + rxctrl0_out : out std_logic_vector(15 downto 0); + rxctrl1_out : out std_logic_vector(15 downto 0); + rxctrl2_out : out std_logic_vector(7 downto 0); + rxctrl3_out : out std_logic_vector(7 downto 0); + rxoutclk_out : out std_logic_vector(0 downto 0); + rxpmaresetdone_out : out std_logic_vector(0 downto 0); + rxresetdone_out : out std_logic_vector(0 downto 0); + txoutclk_out : out std_logic_vector(0 downto 0); + txpmaresetdone_out : out std_logic_vector(0 downto 0); + txresetdone_out : out std_logic_vector(0 downto 0) + ); + end component; - reset_rx_datapath_i <= '0'; - reset_tx_datapath_i <= '0'; + signal reset_tx_done_i : std_logic; + signal reset_rx_done_i : std_logic; + signal userclk_tx_reset_i : std_logic := '0'; + signal txpmaresetdone_i : std_logic; + + signal usrclk : std_logic; + signal usrclk_double : std_logic; + + signal txdata_reg : std_logic_vector(7 downto 0); + signal txcharisk_reg : std_logic; + signal txchardispmode_reg : std_logic; + signal txchardispval_reg : std_logic; + + signal tx16data : std_logic_vector(15 downto 0); + signal tx16charisk : std_logic_vector(1 downto 0); + signal tx16chardispmode : std_logic_vector(1 downto 0); + signal tx16chardispval : std_logic_vector(1 downto 0); + + signal rxctrl0 : std_logic_vector(15 downto 0); + signal rxctrl1 : std_logic_vector(15 downto 0); + signal rxctrl2 : std_logic_vector(7 downto 0); + signal rxctrl3 : std_logic_vector(7 downto 0); + + signal rx16data : std_logic_vector(15 downto 0); + signal rx16charisk : std_logic_vector(1 downto 0); + signal rx16chariscomma : std_logic_vector(1 downto 0); + signal rx16notintable : std_logic_vector(1 downto 0); + signal rx16disperr : std_logic_vector(1 downto 0); + + signal rx16data_reg : std_logic_vector(15 downto 0); + signal rx16charisk_reg : std_logic_vector(1 downto 0); + signal rx16chariscomma_reg : std_logic_vector(1 downto 0); + signal rx16notintable_reg : std_logic_vector(1 downto 0); + signal rx16disperr_reg : std_logic_vector(1 downto 0); + + signal rxdata_i : std_logic_vector(7 downto 0); + signal rxcharisk_i : std_logic; + signal rxchariscomma_i : std_logic; + signal rxnotintable_i : std_logic; + signal rxdisperr_i : std_logic; + + signal usrclk_toggle : std_logic := '0'; + signal usrclk_toggle_reg : std_logic := '0'; + signal usrclk_phase : std_logic := '0'; + + signal reset_all_i : std_logic; + + signal txoutclk_int : std_logic; + signal usrclk_int : std_logic; + + signal usrclk_mmcm_fb : std_logic; + + signal usrclk_active_meta : std_logic := '0'; + signal usrclk_active : std_logic := '0'; + signal not_usrclk_active : std_logic; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of usrclk_active_meta : signal is "true"; + attribute ASYNC_REG of usrclk_active : signal is "true"; +begin + USRCLK_FULL <= usrclk_double; + USRCLK_HALF <= usrclk; - gtpowergood <= gtpowergood_i; + userclk_tx_reset_i <= not txpmaresetdone_i; - --enable Comma detection on K28.5 - rxcommadeten_i <= '1'; - rxmcommaalignen_i <= '1'; - rxpcommaalignen_i <= '1'; - TX_USRCLK <= userclk_tx_usrclk2_i; + TXPMARESETDONE <= txpmaresetdone_i; THE_INIT : gth_xcku_init port map ( - clk_freerun_in => FREECLK, - reset_all_in => reset_all_init, + clk_freerun_in => CLK_100, + reset_all_in => RESET_ALL, tx_init_done_in => reset_tx_done_i, rx_init_done_in => reset_rx_done_i, rx_data_good_in => '1', reset_all_out => reset_all_i, reset_rx_out => open, - init_done_out => init_done_i, + init_done_out => INIT_DONE, retry_ctr_out => open ); - enable_i <= '1'; - THE_RX_FIFO : entity work.fifo_16x18x9_oreg + + process (usrclk) is + begin + if rising_edge(usrclk) then + usrclk_toggle <= not usrclk_toggle; + + rx16data_reg <= rx16data; + rx16charisk_reg <= rx16charisk; + rx16chariscomma_reg <= rx16chariscomma; + rx16notintable_reg <= rx16notintable; + rx16disperr_reg <= rx16disperr; + + tx16data <= TXDATA & txdata_reg; + tx16charisk <= TXCHARISK & txcharisk_reg; + tx16chardispmode <= TXCHARDISPMODE & txchardispmode_reg; + tx16chardispval <= TXCHARDISPVAL & txchardispval_reg; + end if; + end process; + + process (usrclk_double) is + begin + if rising_edge(usrclk_double) then + usrclk_toggle_reg <= usrclk_toggle; + usrclk_phase <= usrclk_toggle xor usrclk_toggle_reg; + + if usrclk_phase = '0' then + rxdata_i <= rx16data_reg(7 downto 0); + rxcharisk_i <= rx16charisk_reg(0); + rxchariscomma_i <= rx16chariscomma_reg(0); + rxnotintable_i <= rx16notintable_reg(0); + rxdisperr_i <= rx16disperr_reg(0); + else + rxdata_i <= rx16data_reg(15 downto 8); + rxcharisk_i <= rx16charisk_reg(1); + rxchariscomma_i <= rx16chariscomma_reg(1); + rxnotintable_i <= rx16notintable_reg(1); + rxdisperr_i <= rx16disperr_reg(1); + end if; + + txdata_reg <= TXDATA; + txcharisk_reg <= TXCHARISK; + txchardispmode_reg <= TXCHARDISPMODE; + txchardispval_reg <= TXCHARDISPVAL; + end if; + end process; + + RXDATA <= rxdata_i; + RXCHARISK <= rxcharisk_i; + RXCHARISCOMMA <= rxchariscomma_i; + RXNOTINTABLE <= rxnotintable_i; + RXDISPERR <= rxdisperr_i; + + + THE_GTH : gth_xcku_x0y8 port map ( - Data(17) => rxctrl2_i(0), - Data(16 downto 9) => userdata_rx_i( 7 downto 0), - Data( 8) => rxctrl2_i(1), - Data( 7 downto 0) => userdata_rx_i(15 downto 8), - WrClock => userclk_rx_usrclk2_i, - RdClock => clk_200, - WrEn => enable_i, - RdEn => enable_i, - Reset => reset_all, - Q(7 downto 0) => rx_data, - Q(8) => rx_k, - Empty => rx_empty, - Full => open, - AlmostEmpty => open, - AlmostFull => open + gtwiz_userclk_tx_active_in(0) => usrclk_active, + gtwiz_userclk_rx_active_in(0) => usrclk_active, + gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_all_in(0) => reset_all_i, + gtwiz_reset_tx_pll_and_datapath_in(0) => '0', + gtwiz_reset_tx_datapath_in(0) => '0', + gtwiz_reset_rx_pll_and_datapath_in(0) => '0', + gtwiz_reset_rx_datapath_in(0) => '0', + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out(0) => reset_tx_done_i, + gtwiz_reset_rx_done_out(0) => reset_rx_done_i, + gtwiz_userdata_tx_in => tx16data, + gtwiz_userdata_rx_out => rx16data, + gtrefclk00_in(0) => GTREFCLK, + qpll0outclk_out => open, + qpll0outrefclk_out => open, + gthrxn_in(0) => RXN, + gthrxp_in(0) => RXP, + rx8b10ben_in(0) => '1', + rxbufreset_in(0) => '0', + rxcdrreset_in(0) => '0', + rxcommadeten_in(0) => '1', + rxmcommaalignen_in(0) => '1', + rxpcommaalignen_in(0) => '1', + rxpcsreset_in(0) => RXPCSRESET, + rxpmareset_in(0) => RXPMARESET, + rxusrclk_in(0) => usrclk_int, + rxusrclk2_in(0) => usrclk_int, + tx8b10ben_in(0) => '1', + txctrl0_in(15 downto 2) => (others => '0'), + txctrl0_in(1 downto 0) => tx16chardispval, + txctrl1_in(15 downto 2) => (others => '0'), + txctrl1_in(1 downto 0) => tx16chardispmode, + txctrl2_in(7 downto 2) => (others => '0'), + txctrl2_in(1 downto 0) => tx16charisk, + txpcsreset_in(0) => TXPCSRESET, + txpmareset_in(0) => TXPMARESET, + txusrclk_in(0) => usrclk_int, + txusrclk2_in(0) => usrclk_int, + gthtxn_out(0) => TXN, + gthtxp_out(0) => TXP, + gtpowergood_out => open, + rxbufstatus_out => open, + rxbyteisaligned_out(0) => RXBYTEISALIGNED, + rxbyterealign_out => open, + rxclkcorcnt_out => open, + rxcommadet_out => open, + rxctrl0_out => rxctrl0, + rxctrl1_out => rxctrl1, + rxctrl2_out => rxctrl2, + rxctrl3_out => rxctrl3, + rxoutclk_out => open, + rxpmaresetdone_out(0) => RXPMARESETDONE, + rxresetdone_out(0) => RXRESETDONE, + txoutclk_out(0) => txoutclk_int, + txpmaresetdone_out(0) => txpmaresetdone_i, + txresetdone_out(0) => TXRESETDONE ); - THE_TX_FIFO : entity work.fifo_1024x9x18_oreg_wcnt + rx16charisk <= rxctrl0(1 downto 0); + rx16notintable <= rxctrl1(1 downto 0); + rx16chariscomma <= rxctrl2(1 downto 0); + rx16disperr <= rxctrl3(1 downto 0); + + bufg_gt_usrclk_inst : BUFG_GT port map ( - Data(8) => tx_k, - Data(7 downto 0) => tx_data, - WrClock => clk_200, - RdClock => userclk_tx_usrclk2_i, - WrEn => tx_fifo_wren_i, - RdEn => enable_i, - Reset => reset_all, - Q( 7 downto 0) => userdata_tx_i(15 downto 8), - Q( 8) => txctrl2_i(1), - Q(16 downto 9) => userdata_tx_i( 7 downto 0), - Q(17) => txctrl2_i(0), - WCNT => tx_fifo_wr_cnt, - Empty => tx_fifo_empty_i, - Full => tx_fifo_full_i, - AlmostEmpty => tx_fifo_almempty_i, - AlmostFull => tx_fifo_almfull_i + O => usrclk_int, + CE => '1', + CEMASK => '0', + CLR => userclk_tx_reset_i, + CLRMASK => '0', + DIV => "000", + I => txoutclk_int ); - process (userclk_tx_usrclk2_i) is + + -- Indicate active helper block functionality when the BUFG_GT divider is + -- not held in reset + process (userclk_tx_reset_i, usrclk_int) is begin - if rising_edge(userclk_tx_usrclk2_i) then - tx_fifo_valid_i <= enable_i and not tx_fifo_empty_i; + if userclk_tx_reset_i = '1' then + usrclk_active_meta <= '0'; + usrclk_active <= '0'; + elsif rising_edge(usrclk_int) then + usrclk_active_meta <= '1'; + usrclk_active <= usrclk_active_meta; end if; end process; - tx_fifo_wren_i <= userclk_tx_active_i and reset_tx_done_i; - - THE_GTH : gth_xcku_x0y8_wrapper - port map( - gthrxn_in => gthrxn_i, - gthrxp_in => gthrxp_i, - gthtxn_out => gthtxn_i, - gthtxp_out => gthtxp_i, - gtwiz_userclk_tx_reset_in => userclk_tx_reset_i, - gtwiz_userclk_tx_srcclk_out => userclk_tx_srcclk_i, - gtwiz_userclk_tx_usrclk_out => userclk_tx_usrclk_i, - gtwiz_userclk_tx_usrclk2_out => userclk_tx_usrclk2_i, - gtwiz_userclk_tx_active_out => userclk_tx_active_i, - gtwiz_userclk_rx_reset_in => userclk_rx_reset_i, - gtwiz_userclk_rx_srcclk_out => userclk_rx_srcclk_i, - gtwiz_userclk_rx_usrclk_out => userclk_rx_usrclk_i, - gtwiz_userclk_rx_usrclk2_out => userclk_rx_usrclk2_i, - gtwiz_userclk_rx_active_out => userclk_rx_active_i, - gtwiz_reset_clk_freerun_in => FREECLK, - gtwiz_reset_all_in => reset_all_i, - gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_i, - gtwiz_reset_tx_datapath_in => reset_tx_datapath_i, - gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_i, - gtwiz_reset_rx_datapath_in => reset_rx_datapath_i, - gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_i, - gtwiz_reset_tx_done_out => reset_tx_done_i, - gtwiz_reset_rx_done_out => reset_rx_done_i, - gtwiz_userdata_tx_in => userdata_tx_i, - gtwiz_userdata_rx_out => userdata_rx_i, - gtrefclk00_in => mgtrefclk0_x0y3_int, - qpll0outclk_out => qpll0outclk_i, - qpll0outrefclk_out => qpll0outrefclk_i, - rx8b10ben_in => '1', - rxbufreset_in => '0', - rxcommadeten_in => rxcommadeten_i, - rxmcommaalignen_in => rxmcommaalignen_i, - rxpcommaalignen_in => rxpcommaalignen_i, - tx8b10ben_in => '1', - txctrl0_in => txctrl0_i, - txctrl1_in => txctrl1_i, - txctrl2_in => txctrl2_i, - gtpowergood_out => gtpowergood_i, - rxbufstatus_out => rxbufstatus_i, - rxbyteisaligned_out => rxbyteisaligned_i, - rxbyterealign_out => rxbyterealign_i, - rxclkcorcnt_out => rxclkcorcnt_i, - rxcommadet_out => rxcommadet_i, - rxctrl0_out => rxctrl0_i, - rxctrl1_out => rxctrl1_i, - rxctrl2_out => rxctrl2_i, - rxctrl3_out => rxctrl3_i, - rxpmaresetdone_out => rxpmaresetdone_i, - txpmaresetdone_out => txpmaresetdone_i + not_usrclk_active <= not usrclk_active; + + + mmcme3_adv_usrclk : MMCME3_ADV + generic map ( + BANDWIDTH => "OPTIMIZED", + CLKOUT4_CASCADE => "FALSE", + COMPENSATION => "AUTO", + STARTUP_WAIT => "FALSE", + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT_F => 10.000, + CLKFBOUT_PHASE => 0.000, + CLKFBOUT_USE_FINE_PS => "FALSE", + CLKOUT0_DIVIDE_F => 10.000, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT0_USE_FINE_PS => "FALSE", + CLKOUT1_DIVIDE => 5, + CLKOUT1_PHASE => 0.000, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT1_USE_FINE_PS => "FALSE", + CLKIN1_PERIOD => 10.000 + ) + port map ( + CLKFBOUT => usrclk_mmcm_fb, + CLKFBOUTB => open, + CLKOUT0 => usrclk, + CLKOUT0B => open, + CLKOUT1 => usrclk_double, + CLKOUT1B => open, + CLKOUT2 => open, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBIN => usrclk_mmcm_fb, + CLKIN1 => usrclk_int, + CLKIN2 => '0', + CLKINSEL => '1', + DADDR => "0000000", + DCLK => '0', + DEN => '0', + DI => x"0000", + DO => open, + DRDY => open, + DWE => '0', + CDDCDONE => open, + CDDCREQ => '0', + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => open, + LOCKED => USRCLK_LOCKED, + CLKINSTOPPED => open, + CLKFBSTOPPED => open, + PWRDWN => '0', + RST => not_usrclk_active ); end architecture behavioral; diff --git a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_wrapper.v b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_wrapper.v deleted file mode 100644 index 627857c..0000000 --- a/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_wrapper.v +++ /dev/null @@ -1,263 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. 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Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - - -`timescale 1ps/1ps - -// ===================================================================================================================== -// This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from -// the core, connects them as appropriate, and maps enabled ports -// ===================================================================================================================== - -module gth_xcku_x0y8_wrapper ( - input wire [0:0] gthrxn_in - ,input wire [0:0] gthrxp_in - ,output wire [0:0] gthtxn_out - ,output wire [0:0] gthtxp_out - ,input wire [0:0] gtwiz_userclk_tx_reset_in - ,output wire [0:0] gtwiz_userclk_tx_srcclk_out - ,output wire [0:0] gtwiz_userclk_tx_usrclk_out - ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out - ,output wire [0:0] gtwiz_userclk_tx_active_out - ,input wire [0:0] gtwiz_userclk_rx_reset_in - ,output wire [0:0] gtwiz_userclk_rx_srcclk_out - ,output wire [0:0] gtwiz_userclk_rx_usrclk_out - ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out - ,output wire [0:0] gtwiz_userclk_rx_active_out - ,input wire [0:0] gtwiz_reset_clk_freerun_in - ,input wire [0:0] gtwiz_reset_all_in - ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in - ,input wire [0:0] gtwiz_reset_tx_datapath_in - ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in - ,input wire [0:0] gtwiz_reset_rx_datapath_in - ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out - ,output wire [0:0] gtwiz_reset_tx_done_out - ,output wire [0:0] gtwiz_reset_rx_done_out - ,input wire [15:0] gtwiz_userdata_tx_in - ,output wire [15:0] gtwiz_userdata_rx_out - ,input wire [0:0] gtrefclk00_in - ,output wire [0:0] qpll0outclk_out - ,output wire [0:0] qpll0outrefclk_out - ,input wire [0:0] rx8b10ben_in - ,input wire [0:0] rxbufreset_in - ,input wire [0:0] rxcommadeten_in - ,input wire [0:0] rxmcommaalignen_in - ,input wire [0:0] rxpcommaalignen_in - ,input wire [0:0] tx8b10ben_in - ,input wire [15:0] txctrl0_in - ,input wire [15:0] txctrl1_in - ,input wire [7:0] txctrl2_in - ,output wire [0:0] gtpowergood_out - ,output wire [2:0] rxbufstatus_out - ,output wire [0:0] rxbyteisaligned_out - ,output wire [0:0] rxbyterealign_out - ,output wire [1:0] rxclkcorcnt_out - ,output wire [0:0] rxcommadet_out - ,output wire [15:0] rxctrl0_out - ,output wire [15:0] rxctrl1_out - ,output wire [7:0] rxctrl2_out - ,output wire [7:0] rxctrl3_out - ,output wire [0:0] rxpmaresetdone_out - ,output wire [0:0] txpmaresetdone_out -); - - - // =================================================================================================================== - // PARAMETERS AND FUNCTIONS - // =================================================================================================================== - - // Declare and initialize local parameters and functions used for HDL generation - localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000; - `include "gth_xcku_wrapper_functions.v" - localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); - localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); - - - // =================================================================================================================== - // HELPER BLOCKS - // =================================================================================================================== - - // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal - // assignments related to optionally-enabled ports may appear below. - - // ------------------------------------------------------------------------------------------------------------------- - // Transmitter user clocking network helper block - // ------------------------------------------------------------------------------------------------------------------- - - wire [0:0] txusrclk_int; - wire [0:0] txusrclk2_int; - wire [0:0] txoutclk_int; - - // Generate a single module instance which is driven by a clock source associated with the master transmitter channel, - // and which drives TXUSRCLK and TXUSRCLK2 for all channels - - // The source clock is TXOUTCLK from the master transmitter channel - assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX]; - - // Instantiate a single instance of the transmitter user clocking network helper block - gtwizard_ultrascale_v1_7_8_gtwiz_userclk_tx gtwiz_userclk_tx_inst ( - .gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out), - .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in), - .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out), - .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out), - .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out) - ); - - // Drive TXUSRCLK and TXUSRCLK2 for all channels with the respective helper block outputs - assign txusrclk_int = {1{gtwiz_userclk_tx_usrclk_out}}; - assign txusrclk2_int = {1{gtwiz_userclk_tx_usrclk2_out}}; - - // ------------------------------------------------------------------------------------------------------------------- - // Receiver user clocking network helper block - // ------------------------------------------------------------------------------------------------------------------- - - wire [0:0] rxusrclk_int; - wire [0:0] rxusrclk2_int; - wire [0:0] rxoutclk_int; - - // Generate a single module instance which is driven by a clock source associated with the master receiver channel, - // and which drives RXUSRCLK and RXUSRCLK2 for all channels - - // The source clock is RXOUTCLK from the master receiver channel - assign gtwiz_userclk_rx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX]; - - // Instantiate a single instance of the receiver user clocking network helper block - gtwizard_ultrascale_v1_7_8_gtwiz_userclk_rx gtwiz_userclk_rx_inst ( - .gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out), - .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in), - .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out), - .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out), - .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out) - ); - - // Drive RXUSRCLK and RXUSRCLK2 for all channels with the respective helper block outputs - assign rxusrclk_int = {1{gtwiz_userclk_rx_usrclk_out}}; - assign rxusrclk2_int = {1{gtwiz_userclk_rx_usrclk2_out}}; - wire [0:0] gtpowergood_int; - - // Required assignment to expose the GTPOWERGOOD port per user request - assign gtpowergood_out = gtpowergood_int; - - // ---------------------------------------------------------------------------------------------------------------- - // Assignments to expose data ports, or data control ports, per configuration requirement or user request - // ---------------------------------------------------------------------------------------------------------------- - - wire [15:0] txctrl0_int; - - // Required assignment to expose the TXCTRL0 port per configuration requirement or user request - assign txctrl0_int = txctrl0_in; - wire [15:0] txctrl1_int; - - // Required assignment to expose the TXCTRL1 port per configuration requirement or user request - assign txctrl1_int = txctrl1_in; - wire [15:0] rxctrl0_int; - - // Required assignment to expose the RXCTRL0 port per configuration requirement or user request - assign rxctrl0_out = rxctrl0_int; - wire [15:0] rxctrl1_int; - - // Required assignment to expose the RXCTRL1 port per configuration requirement or user request - assign rxctrl1_out = rxctrl1_int; - - - // =================================================================================================================== - // CORE INSTANCE - // =================================================================================================================== - - // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate - gth_xcku_x0y8 gth_xcku_x0y8_inst ( - .gthrxn_in (gthrxn_in) - ,.gthrxp_in (gthrxp_in) - ,.gthtxn_out (gthtxn_out) - ,.gthtxp_out (gthtxp_out) - ,.gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_out) - ,.gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_out) - ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in) - ,.gtwiz_reset_all_in (gtwiz_reset_all_in) - ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in) - ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in) - ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in) - ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in) - ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out) - ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out) - ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out) - ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in) - ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out) - ,.gtrefclk00_in (gtrefclk00_in) - ,.qpll0outclk_out (qpll0outclk_out) - ,.qpll0outrefclk_out (qpll0outrefclk_out) - ,.rx8b10ben_in (rx8b10ben_in) - ,.rxbufreset_in (rxbufreset_in) - ,.rxcommadeten_in (rxcommadeten_in) - ,.rxmcommaalignen_in (rxmcommaalignen_in) - ,.rxpcommaalignen_in (rxpcommaalignen_in) - ,.rxusrclk_in (rxusrclk_int) - ,.rxusrclk2_in (rxusrclk2_int) - ,.tx8b10ben_in (tx8b10ben_in) - ,.txctrl0_in (txctrl0_int) - ,.txctrl1_in (txctrl1_int) - ,.txctrl2_in (txctrl2_in) - ,.txusrclk_in (txusrclk_int) - ,.txusrclk2_in (txusrclk2_int) - ,.gtpowergood_out (gtpowergood_int) - ,.rxbufstatus_out (rxbufstatus_out) - ,.rxbyteisaligned_out (rxbyteisaligned_out) - ,.rxbyterealign_out (rxbyterealign_out) - ,.rxclkcorcnt_out (rxclkcorcnt_out) - ,.rxcommadet_out (rxcommadet_out) - ,.rxctrl0_out (rxctrl0_int) - ,.rxctrl1_out (rxctrl1_int) - ,.rxctrl2_out (rxctrl2_out) - ,.rxctrl3_out (rxctrl3_out) - ,.rxoutclk_out (rxoutclk_int) - ,.rxpmaresetdone_out (rxpmaresetdone_out) - ,.txoutclk_out (txoutclk_int) - ,.txpmaresetdone_out (txpmaresetdone_out) -); - -endmodule diff --git a/media_interfaces/xcku/gtwizard_options.txt b/media_interfaces/xcku/gtwizard_options.txt index fba870f..c55763b 100644 --- a/media_interfaces/xcku/gtwizard_options.txt +++ b/media_interfaces/xcku/gtwizard_options.txt @@ -15,21 +15,32 @@ Tab "Physical Resources": Tab "Optional Features": Receiver comma detection and alignment: Plus comma: - (X), 1010000011 - Minus comma: (X), 0101111100 - Mask: - 0011111111 + Minus comma: + (X), 1010000011 + (= preset K28.5) + Alignment boundary + Two byte boundary Receiver clock correction: Enable and select number of sequences to use: - 2 + 1 Length of each sequence: 2 Sequence 0, pattern 0: 01010000 Sequence 0, pattern 1: 10111100, K character - Sequence 1, pattern 0: - 01010000, Inverted disparity - Sequence 1, pattern 1: - 10111100, K character, Inverted disparity + Keep Idle + Enable + +Tab "Structural Options" + Expose additional ports by functionality, for advanced feature usage + TX Initialization and Reset Ports + txpcsreset_in + txpmareset_in + txresetdone_out + RX Initialization and Reset Ports + rxcdrreset_in + rxpcsreset_in + rxpmareset_in + rxresetdone_out diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 892aa7d..c87aad4 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -2537,10 +2537,10 @@ end component; component pulse_sync is port( CLK_A_IN : in std_logic; - RESET_A_IN : in std_logic; + RESET_A_IN : in std_logic := '0'; PULSE_A_IN : in std_logic; CLK_B_IN : in std_logic; - RESET_B_IN : in std_logic; + RESET_B_IN : in std_logic := '0'; PULSE_B_OUT : out std_logic ); end component; diff --git a/xilinx/xcku/lattice_ecp3_fifo_18x16_dualport_oreg.vhd b/xilinx/xcku/lattice_ecp3_fifo_18x16_dualport_oreg.vhd new file mode 100644 index 0000000..b49437d --- /dev/null +++ b/xilinx/xcku/lattice_ecp3_fifo_18x16_dualport_oreg.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity lattice_ecp3_fifo_18x16_dualport_oreg is + port ( + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(17 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end entity lattice_ecp3_fifo_18x16_dualport_oreg; + +architecture structural of lattice_ecp3_fifo_18x16_dualport_oreg is + component fifo_18x16_dualport_oreg_xcku + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(17 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(17 downto 0); + full : out std_logic; + empty : out std_logic; + prog_full : out std_logic + ); + end component; +begin + fifo : fifo_18x16_dualport_oreg_xcku + port map ( + rst => Reset, + wr_clk => WrClock, + rd_clk => RdClock, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => Full, + empty => Empty, + prog_full => AlmostFull + ); +end architecture structural;