From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Wed, 20 Jul 2022 09:49:28 +0000 (+0200)
Subject: direct port for internal SCTRL added
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d3242325b34f0609a411b9b0b36b8b7b4b4dec6a;p=trbnet.git

direct port for internal SCTRL added
---

diff --git a/gbe_trb_ecp3/base/gbe_med_fifo.vhd b/gbe_trb_ecp3/base/gbe_med_fifo.vhd
index bec8163..23afea0 100644
--- a/gbe_trb_ecp3/base/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp3/base/gbe_med_fifo.vhd
@@ -11,7 +11,8 @@ use work.med_sync_define_RS.all;
 
 entity gbe_med_fifo is
   generic(
-    LINKS_ACTIVE          : std_logic_vector(3 downto 0) := "1111"
+    LINKS_ACTIVE          : std_logic_vector(3 downto 0) := "1111";
+    SNIFFER_PORT          : integer range 0 to 3         := 0
   );
   port(
     RESET                 : in  std_logic;
@@ -36,13 +37,20 @@ entity gbe_med_fifo is
     SD_PRSNT_N_IN         : in  std_logic_vector(3 downto 0)          := (others => '1');
     SD_LOS_IN             : in  std_logic_vector(3 downto 0)          := (others => '1');
     SD_TXDIS_OUT          : out std_logic_vector(3 downto 0);
+    -- internal sniffer port
+    MAC_RX_DATA_OUT       : out std_logic_vector(7 downto 0);
+    MAC_RX_WRITE_OUT      : out std_logic;
+    MAC_RX_EOF_OUT        : out std_logic;
+    MAC_RX_ERROR_OUT      : out std_logic;
     -- SerDes control
     TX_PLOL_LOL_OUT       : out std_logic;
     TX_PCS_RST_IN         : in  std_logic;
     RX_LINK_READY_OUT     : out std_logic_vector(3 downto 0);
     TX_LINK_READY_IN      : in  std_logic;
+    -- Status
     PCS_AN_READY_OUT      : out std_logic_vector(3 downto 0); -- for internal SCTRL
     LINK_ACTIVE_OUT       : out std_logic_vector(3 downto 0); -- for internal SCTRL
+    TICK_MS_IN            : in  std_logic;
     -- Debug
     STATUS_OUT            : out std_logic_vector(4 * 8 - 1 downto 0);
     DEBUG_OUT             : out std_logic_vector(63 downto 0)
@@ -244,7 +252,7 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is
 --  attribute BBOX   of ddmtd_arch : architecture is "2,2";
 
 begin
-  
+
   gbe_serdes: entity serdes_gbe_4ch_ds
   port map(
     -- CH0 --
@@ -680,6 +688,12 @@ begin
     
   end generate CHANNEL_GEN;
 
+  MAC_RX_DATA_OUT  <= mac_rx_data((SNIFFER_PORT + 1) * 8 - 1 downto SNIFFER_PORT * 8);
+  MAC_RX_WRITE_OUT <= mac_rx_wr(SNIFFER_PORT);
+  MAC_RX_EOF_OUT   <= mac_rx_eof(SNIFFER_PORT);
+  MAC_RX_ERROR_OUT <= mac_rx_err(SNIFFER_PORT);
+
+  
   THE_LED_TIMER_PROC: process( CLK_125 )
   begin
     if( rising_edge(CLK_125) ) then