From: hadeshyp Date: Wed, 12 May 2010 19:52:03 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~286 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d380fd27486c9e9a19be38e405432c4ee226e21e;p=trbnet.git *** empty log message *** --- diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index 643408d..9bb4e5e 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -13,12 +13,14 @@ entity handler_trigger_and_data is DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + DATA_0_IS_STATUS : integer range 0 to 1 := c_NO; HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 ); port( CLOCK : in std_logic; RESET : in std_logic; + RESET_IPU : in std_logic; --To Endpoint --Timing Trigger (registered) @@ -105,6 +107,7 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is signal buf_lvl1_trg_release : std_logic; signal status_ipu_handler_i : std_logic_vector(31 downto 0); signal debug_data_handler_i : std_logic_vector(31 downto 0); + signal reset_ipu_i : std_logic; begin @@ -153,7 +156,7 @@ begin ) port map( CLOCK => CLOCK, - RESET => RESET, + RESET => reset_ipu_i, --From LVL1 Handler LVL1_VALID_TRIGGER_IN => LVL1_VALID_TRIGGER_IN, @@ -196,7 +199,7 @@ begin ) port map( CLOCK => CLOCK, - RESET => RESET, + RESET => reset_ipu_i, --From Data Handler DAT_DATA_IN => ipu_data, DAT_DATA_READ_OUT => ipu_data_read, @@ -226,6 +229,8 @@ begin ----------------------------------------------------------------------- -- Connect Outputs ----------------------------------------------------------------------- + reset_ipu_i <= RESET or RESET_IPU; + LVL1_TRG_RELEASE_OUT <= buf_lvl1_trg_release; buf_lvl1_trg_release <= and_all(fee_trg_release); LVL1_ERROR_PATTERN_OUT <= fee_trg_statusbits; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index e3b9e52..de34873 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -796,10 +796,13 @@ begin if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then got_timing_trigger <= '0'; got_timingless_trigger <= '0'; + timing_trigger_missing <= '0'; elsif TRG_TIMING_TRG_RECEIVED_IN = '1' then got_timing_trigger <= '1'; elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then got_timingless_trigger <= '1'; + elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1')) then + timing_trigger_missing <= '1'; end if; end if; end process; @@ -817,7 +820,19 @@ begin and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7); buf_LVL1_INVALID_TRG_OUT <= '0'; ---TODO: timing_trigger_missing; +-- proc_count_timing_trg : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- last_TRG_TIMING_TRG_RECEIVED_IN <= TRG_TIMING_TRG_RECEIVED_IN; +-- last_timingtrg_counter_write <= timingtrg_counter_write; +-- last_timingtrg_counter_read <= timingtrg_counter_read; +-- if RESET = '1' or timingtrg_counter_write = '1' then +-- timingtrg_counter <= (others => '0'); +-- elsif TRG_TIMING_TRG_RECEIVED_IN = '1' and last_TRG_TIMING_TRG_RECEIVED_IN = '0' then +-- timingtrg_counter <= (others => '0'); +-- end if; +-- end if; +-- end process; ------------------------------------------------- -- Connect Outputs diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 0f7dbfe..11aef82 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -156,6 +156,7 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal ipu_read_i : std_logic; signal ipu_length_i : std_logic_vector (15 downto 0); signal ipu_error_pattern_i : std_logic_vector (31 downto 0); + signal reset_ipu_i : std_logic; signal common_stat_reg_i : std_logic_vector (std_COMSTATREG*32-1 downto 0); signal common_ctrl_reg_i : std_logic_vector (std_COMCTRLREG*32-1 downto 0); @@ -201,6 +202,9 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal last_write_enable : std_logic_vector(5 downto 0); signal last_read_enable : std_logic_vector(5 downto 0); + signal debug_data_handler_i : std_logic_vector(31 downto 0); + signal debug_ipu_handler_i : std_logic_vector(31 downto 0); + begin --------------------------------------------------------------------------- -- TrbNet Endpoint @@ -453,7 +457,7 @@ begin port map( CLOCK => CLK, RESET => RESET, - + RESET_IPU => reset_ipu_i, --LVL1 channel LVL1_VALID_TRIGGER_IN => lvl1_valid_i, LVL1_INT_TRG_NUMBER_IN => lvl1_int_trg_number_i, @@ -491,13 +495,15 @@ begin STATUS_OUT => stat_handler_i, --Debug - DEBUG_DATA_HANDLER_OUT => STAT_DEBUG_DATA_HANDLER_OUT, - DEBUG_IPU_HANDLER_OUT => STAT_DEBUG_IPU_HANDLER_OUT + DEBUG_DATA_HANDLER_OUT => debug_data_handler_i, + DEBUG_IPU_HANDLER_OUT => debug_ipu_handler_i ); - lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i; - + reset_ipu_i <= RESET or common_ctrl_reg_i(2); + lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i; + STAT_DEBUG_IPU_HANDLER_OUT <= debug_ipu_handler_i; + STAT_DEBUG_DATA_HANDLER_OUT <= debug_data_handler_i; --------------------------------------------------------------------------- -- Connect Status Registers @@ -545,7 +551,6 @@ begin REGIO_STAT_STROBE_OUT <= stat_strobe_i; REGIO_CTRL_STROBE_OUT <= ctrl_strobe_i; - common_stat_reg_i <= REGIO_COMMON_STAT_REG_IN; stat_reg_i <= REGIO_STAT_REG_IN; TIME_GLOBAL_OUT <= time_global_i; @@ -553,4 +558,22 @@ begin TIME_SINCE_LAST_TRG_OUT <= time_since_last_trg_i; TIME_TICKS_OUT <= time_ticks_i; + process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i) + begin + common_stat_reg_i(47 downto 0) <= REGIO_COMMON_STAT_REG_IN(47 downto 0); + common_stat_reg_i(6) <= debug_ipu_handler_i(15) or REGIO_COMMON_STAT_REG_IN(6); --not configured + common_stat_reg_i(9) <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9); + common_stat_reg_i(10) <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10); + common_stat_reg_i(11) <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11); + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if ipu_start_readout_i = '1' then + common_stat_reg_i(63 downto 48) <= ipu_number_i; + end if; + end if; + end process; + end architecture; \ No newline at end of file diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index d977519..7844e68 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -1191,7 +1191,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); begin if rising_edge(CLK) then HC_STAT_REGS(8*32-1 downto 0) <= buf_HC_STAT_REGS(8*32-1 downto 0); - HC_STAT_REGS(31*32-1 downto 12*32) <= buf_HC_STAT_REGS(31*32-1 downto 12*32); + HC_STAT_REGS(36*32-1 downto 12*32) <= buf_HC_STAT_REGS(36*32-1 downto 12*32); HC_STAT_REGS(48*32-1 downto 37*32) <= buf_HC_STAT_REGS(48*32-1 downto 37*32); HC_STAT_REGS(64*32-1 downto 48*32) <= buf_HC_STAT_REGS(64*32-1 downto 48*32); end if; diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 2dfea73..4d970f0 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -88,6 +88,7 @@ package trb_net16_hub_func is --hub control HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL; HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; + HUB_CTRL_BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FE"; HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES); USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES); USE_VENDOR_CORES : integer range 0 to 1 := c_YES; @@ -359,6 +360,179 @@ component trb_net16_hub_streaming_port is ); end component; +component trb_net16_gbe_buf is +generic( + DO_SIMULATION : integer range 0 to 1 := 1; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); +port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- PacketConstructor interface + IG_CTS_CTR_TST : out std_logic_vector(2 downto 0); + IG_REM_CTR_TST : out std_logic_vector(3 downto 0); + IG_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + IG_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + IG_DATA_TST : out std_logic_vector(15 downto 0); + IG_WCNT_TST : out std_logic_vector(15 downto 0); + IG_RCNT_TST : out std_logic_vector(16 downto 0); + IG_RD_EN_TST : out std_logic; + IG_WR_EN_TST : out std_logic; + IG_EMPTY_TST : out std_logic; + IG_AEMPTY_TST : out std_logic; + IG_FULL_TST : out std_logic; + IG_AFULL_TST : out std_logic; + PC_WR_EN_TST : out std_logic; + PC_DATA_TST : out std_logic_vector (7 downto 0); + PC_READY_TST : out std_logic; + PC_START_OF_SUB_TST : out std_logic; + PC_END_OF_DATA_TST : out std_logic; + PC_SUB_SIZE_TST : out std_logic_vector(31 downto 0); + PC_TRIG_NR_TST : out std_logic_vector(31 downto 0); + PC_PADDING_TST : out std_logic; + PC_DECODING_TST : out std_logic_vector(31 downto 0); + PC_EVENT_ID_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_DEC_TST : out std_logic_vector(31 downto 0); + PC_BSM_CONSTR_TST : out std_logic_vector(3 downto 0); + PC_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + PC_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + PC_SHF_EMPTY_TST : out std_logic; + PC_SHF_FULL_TST : out std_logic; + PC_SHF_WR_EN_TST : out std_logic; + PC_SHF_RD_EN_TST : out std_logic; + PC_SHF_Q_TST : out std_logic_vector(7 downto 0); + PC_DF_EMPTY_TST : out std_logic; + PC_DF_FULL_TST : out std_logic; + PC_DF_WR_EN_TST : out std_logic; + PC_DF_RD_EN_TST : out std_logic; + PC_DF_Q_TST : out std_logic_vector(7 downto 0); + PC_ALL_CTR_TST : out std_logic_vector(4 downto 0); + PC_SUB_CTR_TST : out std_logic_vector(4 downto 0); + PC_BYTES_LOADED_TST : out std_logic_vector(15 downto 0); + PC_SIZE_LEFT_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_TO_SAVE_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_LOADED_TST : out std_logic_vector(31 downto 0); + PC_SUB_BYTES_LOADED_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + PC_ACT_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameConstructor interface + FC_WR_EN_TST : out std_logic; + FC_DATA_TST : out std_logic_vector(7 downto 0); + FC_H_READY_TST : out std_logic; + FC_READY_TST : out std_logic; + FC_IP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_IDENT_TST : out std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_TST : out std_logic_vector(15 downto 0); + FC_SOD_TST : out std_logic; + FC_EOD_TST : out std_logic; + FC_BSM_CONSTR_TST : out std_logic_vector(7 downto 0); + FC_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameTransmitter interface + FT_DATA_TST : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_TST : out std_logic; + FT_START_OF_PACKET_TST : out std_logic; + FT_BSM_INIT_TST : out std_logic_vector(3 downto 0); + FT_BSM_MAC_TST : out std_logic_vector(3 downto 0); + FT_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- MAC interface + MAC_HADDR_TST : out std_logic_vector(7 downto 0); + MAC_HDATA_TST : out std_logic_vector(7 downto 0); + MAC_HCS_TST : out std_logic; + MAC_HWRITE_TST : out std_logic; + MAC_HREAD_TST : out std_logic; + MAC_HREADY_TST : out std_logic; + MAC_HDATA_EN_TST : out std_logic; + MAC_FIFOAVAIL_TST : out std_logic; + MAC_FIFOEOF_TST : out std_logic; + MAC_FIFOEMPTY_TST : out std_logic; + MAC_TX_READ_TST : out std_logic; + MAC_TX_DONE_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- pcs and serdes + PCS_AN_LP_ABILITY_TST : out std_logic_vector(15 downto 0); + PCS_AN_COMPLETE_TST : out std_logic; + PCS_AN_PAGE_RX_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + end package trb_net16_hub_func; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 607a92b..e93afe5 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -443,7 +443,7 @@ begin variable tmpF0,tmpF1, tmpF2, tmpF3 : std_logic; begin if rising_edge(CLK) then - if reset_i = '1' or locked = '0' then + if reset_i = '1' or (locked = '0' and last_locked = '1') then REPLY_combined_trm_F0(j) <= '0'; REPLY_combined_trm_F1(j) <= '0'; REPLY_combined_trm_F2(j) <= '0'; @@ -480,8 +480,8 @@ begin STAT_ALL_ERRORBITS(i*32+31 downto i*32+16) <= reply_data_in_i(i*16+15 downto i*16); elsif reading_trmF2(i) = '1' then STAT_ALL_ERRORBITS(i*32+15 downto i*32+0) <= reply_data_in_i(i*16+15 downto i*16); - elsif locked = '1' and last_locked = '0' then - STAT_ALL_ERRORBITS(i*32+31 downto i*32) <= (others => '0'); +-- elsif locked = '1' and last_locked = '0' then +-- STAT_ALL_ERRORBITS(i*32+31 downto i*32) <= (others => '0'); end if; end loop; end if; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 752a80c..a7afe41 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1012,6 +1012,7 @@ package trb_net_components is port( CLOCK : in std_logic; RESET : in std_logic; + RESET_IPU : in std_logic; --To Endpoint --Timing Trigger (registered)