From: Jan Michel <j.michel@gsi.de>
Date: Fri, 11 Aug 2017 14:25:55 +0000 (+0200)
Subject: Sync media interface uses RXI clock on receiver side.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d42ff3e207c3eb95c8ce85d75685504315f37d08;p=trbnet.git

Sync media interface uses RXI clock on receiver side.
---

diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd
index 5249f00..6d6100e 100644
--- a/media_interfaces/med_ecp3_sfp_sync_4.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd
@@ -120,7 +120,7 @@ SD_TXDIS_OUT <= (others => RESET);
       hdoutp_ch0           => hdoutp(0),
       hdoutn_ch0           => hdoutn(0),
       txiclk_ch0           => clk_200_ref, --clk_tx_full(0),
-      rxiclk_ch0           => clk_200_ref,
+      rxiclk_ch0           => clk_rx_full(0), --clk_200_ref,
       rx_full_clk_ch0      => clk_rx_full(0),
       rx_half_clk_ch0      => clk_rx_half(0),
       tx_full_clk_ch0      => clk_tx_full(0),
@@ -152,7 +152,7 @@ SD_TXDIS_OUT <= (others => RESET);
       hdoutp_ch1           => hdoutp(1),
       hdoutn_ch1           => hdoutn(1),
       txiclk_ch1           => clk_200_ref, --clk_tx_full(1),
-      rxiclk_ch1           => clk_200_ref,
+      rxiclk_ch1           => clk_rx_full(1), --clk_200_ref,
       rx_full_clk_ch1      => clk_rx_full(1),
       rx_half_clk_ch1      => clk_rx_half(1),
       tx_full_clk_ch1      => clk_tx_full(1),
@@ -184,7 +184,7 @@ SD_TXDIS_OUT <= (others => RESET);
       hdoutp_ch2           => hdoutp(2),
       hdoutn_ch2           => hdoutn(2),
       txiclk_ch2           => clk_200_ref, --clk_tx_full(2),
-      rxiclk_ch2           => clk_200_ref,
+      rxiclk_ch2           => clk_rx_full(2), --clk_200_ref,
       rx_full_clk_ch2      => clk_rx_full(2),
       rx_half_clk_ch2      => clk_rx_half(2),
       tx_full_clk_ch2      => clk_tx_full(2),
@@ -216,7 +216,7 @@ SD_TXDIS_OUT <= (others => RESET);
       hdoutp_ch3           => hdoutp(3),
       hdoutn_ch3           => hdoutn(3),
       txiclk_ch3           => clk_200_ref, --clk_tx_full(3),
-      rxiclk_ch3           => clk_200_ref, --clk_tx_full(3),
+      rxiclk_ch3           => clk_rx_full(3), --clk_200_ref, --clk_tx_full(3),
       rx_full_clk_ch3      => clk_rx_full(3),
       rx_half_clk_ch3      => clk_rx_half(3),
       tx_full_clk_ch3      => clk_tx_full(3),
@@ -276,7 +276,7 @@ gen_control : for i in 0 to 3 generate
         )
       port map(
         CLK_SYS     => SYSCLK,
-        CLK_RXI     => clk_200_ref,
+        CLK_RXI     => clk_rx_full(i), --clk_200_ref,
         CLK_RXHALF  => clk_rx_half(i),
         CLK_TXI     => clk_200_ref, --clk_tx_full(i),
         CLK_REF     => CLK_INTERNAL_FULL,
diff --git a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd
index 6cad1dc..e2c807f 100644
--- a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd
@@ -121,7 +121,7 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE);   --slave on
       hdoutp_ch0           => hdoutp(0),
       hdoutn_ch0           => hdoutn(0),
       txiclk_ch0           => clk_200_ref, --clk_tx_full(0),
-      rxiclk_ch0           => clk_200_ref,
+      rxiclk_ch0           => clk_rx_full(0), --clk_200_ref,
       rx_full_clk_ch0      => clk_rx_full(0),
       rx_half_clk_ch0      => clk_rx_half(0),
       tx_full_clk_ch0      => clk_tx_full(0),
@@ -153,7 +153,7 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE);   --slave on
       hdoutp_ch1           => hdoutp(1),
       hdoutn_ch1           => hdoutn(1),
       txiclk_ch1           => clk_200_ref, --clk_tx_full(1),
-      rxiclk_ch1           => clk_200_ref,
+      rxiclk_ch1           => clk_rx_full(1), --clk_200_ref,
       rx_full_clk_ch1      => clk_rx_full(1),
       rx_half_clk_ch1      => clk_rx_half(1),
       tx_full_clk_ch1      => clk_tx_full(1),
@@ -185,7 +185,7 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE);   --slave on
       hdoutp_ch2           => hdoutp(2),
       hdoutn_ch2           => hdoutn(2),
       txiclk_ch2           => clk_200_ref, --clk_tx_full(2),
-      rxiclk_ch2           => clk_200_ref,
+      rxiclk_ch2           => clk_rx_full(2), --clk_200_ref,
       rx_full_clk_ch2      => clk_rx_full(2),
       rx_half_clk_ch2      => clk_rx_half(2),
       tx_full_clk_ch2      => clk_tx_full(2),
@@ -217,7 +217,7 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE);   --slave on
       hdoutp_ch3           => hdoutp(3),
       hdoutn_ch3           => hdoutn(3),
       txiclk_ch3           => clk_200_ref, --clk_tx_full(3),
-      rx_full_clk_ch3      => clk_rx_full(3),
+      rx_full_clk_ch3      => clk_rx_full(3), --clk_rx_full(3),
       rx_half_clk_ch3      => clk_rx_half(3),
       tx_full_clk_ch3      => clk_tx_full(3),
       tx_half_clk_ch3      => clk_tx_half(3),
@@ -276,7 +276,7 @@ gen_control : for i in 0 to 3 generate
         )
       port map(
         CLK_SYS     => SYSCLK,
-        CLK_RXI     => clk_rxi(i),
+        CLK_RXI     => clk_rx_full(i), --clk_rxi(i),
         CLK_RXHALF  => clk_rx_half(i),
         CLK_TXI     => clk_200_ref, --clk_tx_full(i),
         CLK_REF     => CLK_INTERNAL_FULL,