From: Jan Michel Date: Tue, 8 Dec 2015 18:30:07 +0000 (+0100) Subject: Adding a new debugging interface via UART, included in trb3sc template. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d4611e62d5b6da7018a069f617e67caf736bdcef;p=trb3sc.git Adding a new debugging interface via UART, included in trb3sc template. --- diff --git a/code/debuguart.vhd b/code/debuguart.vhd new file mode 100644 index 0000000..9428fc2 --- /dev/null +++ b/code/debuguart.vhd @@ -0,0 +1,230 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.config.all; + + +entity debuguart is + port ( + CLK : in std_logic; + RESET : in std_logic; + + RX_IN : in std_logic; + TX_OUT : out std_logic; + + DEBUG_ACTIVE : out std_logic; + + BUS_DEBUG_TX : in CTRLBUS_TX; + BUS_DEBUG_RX : out CTRLBUS_RX; + + STATUS : out std_logic_vector(31 downto 0) + + ); +end entity; + + +architecture arch of debuguart is + +constant clk_div : integer := (CLOCK_FREQUENCY*1000000)/115200; + +signal tx_data, rx_data, tx_fifo_out : std_logic_vector(7 downto 0); +signal rx_ready, tx_ready, tx_send, tx_start : std_logic; + +signal tx_fifo_read, tx_fifo_write : std_logic; +signal tx_fifo_empty, tx_fifo_full : std_logic; +signal next2_tx_start, next_tx_start : std_logic; + +type FSM_STATE is (IDLE, START, DO_COMMAND, WAIT_ANSWER, SEND, FINISH); +signal state : FSM_STATE; +signal command : std_logic; +signal bytecount : integer range 0 to 15; +signal addr_data : std_logic_vector(47 downto 0); +signal timer : unsigned(4 downto 0); +signal timeout : unsigned(26 downto 0); + + +begin + + + +THE_RX : entity work.uart_rec + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + RX => RX_IN, + DATA_OUT => rx_data, + DATA_WAITING => rx_ready, + DEBUG => open + ); + +THE_TX : entity work.uart_trans + port map( + CLK_DIV => clk_div, + CLK => CLK, + RST => RESET, + DATA_IN => tx_fifo_out(7 downto 0), + SEND => tx_start, + READY => tx_ready, + TX => TX_OUT, + DEBUG => open + ); + + + +THE_TX_FIFO : entity work.fifo_9x2k_oreg + port map( + Clock => CLK, + Data(7 downto 0) => tx_data, + Data(8) => '0', + WrEn => tx_send, + RdEn => tx_fifo_read, + Reset => RESET, + Q(7 downto 0) => tx_fifo_out, + Empty => tx_fifo_empty, + Full => tx_fifo_full + ); + +PROC_SEND : process begin + wait until rising_edge(CLK); + tx_fifo_read <= '0'; + next_tx_start <= '0'; + next2_tx_start <= next_tx_start; + tx_start <= next2_tx_start; + + if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_start = '0' and next2_tx_start = '0' then + next_tx_start <= '1'; + tx_fifo_read <= '1'; + end if; + +end process; + + + +PROC_CTRL : process + variable tmp : unsigned(7 downto 0); +begin + wait until rising_edge(CLK); + timeout <= timeout + 1; + tx_send <= '0'; + BUS_DEBUG_RX.write <= '0'; + BUS_DEBUG_RX.read <= '0'; + + case state is + when IDLE => + command <= '0'; + bytecount <= 11; + timeout <= (others => '0'); + DEBUG_ACTIVE <= '0'; + if rx_ready = '1' then + if rx_data = x"52" then + command <= '1'; + state <= START; + elsif rx_data = x"57" then + command <= '0'; + state <= START; + end if; + end if; + + when START => + if rx_ready = '1' then + if rx_data > x"40" then + tmp := unsigned(rx_data) + x"09"; + else + tmp := unsigned(rx_data); + end if; + addr_data(bytecount*4+3 downto bytecount*4) <= std_logic_vector(tmp(3 downto 0)); + if (bytecount = 0 and command = '0') or (bytecount = 8 and command = '1') then + state <= DO_COMMAND; + else + bytecount <= bytecount - 1; + end if; + end if; + + when DO_COMMAND => + DEBUG_ACTIVE <= '1'; + BUS_DEBUG_RX.data <= addr_data(31 downto 0); + BUS_DEBUG_RX.addr <= addr_data(47 downto 32); + BUS_DEBUG_RX.write <= not command; + BUS_DEBUG_RX.read <= command; + state <= WAIT_ANSWER; + timer <= (others => '0'); + + when WAIT_ANSWER => + timer <= timer + 1; + if BUS_DEBUG_TX.ack = '1' or BUS_DEBUG_TX.wack = '1' or BUS_DEBUG_TX.rack = '1' then + tx_data <= x"41"; + tx_send <= '1'; + if command = '1' then + state <= SEND; + addr_data(31 downto 0) <= BUS_DEBUG_TX.data; + bytecount <= 11; + else + state <= FINISH; + end if; + elsif BUS_DEBUG_TX.nack = '1' then + tx_data <= x"4E"; + tx_send <= '1'; + state <= FINISH; + elsif BUS_DEBUG_TX.unknown = '1' then + tx_data <= x"55"; + tx_send <= '1'; + state <= FINISH; + elsif timer = "11111" then + tx_data <= x"54"; + tx_send <= '1'; + state <= FINISH; + end if; + + when SEND => + DEBUG_ACTIVE <= '0'; + + tmp := x"0" & unsigned(addr_data(bytecount*4+3 downto bytecount*4)); + if tmp > x"09" then + tmp := tmp + x"41" - x"0a"; + else + tmp := tmp + x"30"; + end if; + + tx_data <= std_logic_vector(tmp); + tx_send <= '1'; + + if bytecount = 0 then + state <= FINISH; + else + bytecount <= bytecount - 1; + end if; + + when FINISH => + tx_data <= x"0a"; + tx_send <= '1'; + state <= IDLE; + end case; + + if timeout(timeout'left) = '1' or RESET = '1' then + state <= IDLE; + end if; + +end process; + + +STATUS(7 downto 0) <= rx_data; +STATUS(15 downto 8)<= tx_data; +STATUS(19 downto 16) <= std_logic_vector(to_unsigned(bytecount,4)); +STATUS(20) <= command; +STATUS(21) <= rx_ready; +STATUS(22) <= tx_send; +STATUS(23) <= tx_fifo_empty; +STATUS(24) <= RX_IN; +STATUS(31 downto 25) <= std_logic_vector(timeout(26 downto 20)); + +end architecture; + + + + + + \ No newline at end of file diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd index b0bdb24..4fff257 100644 --- a/code/trb3sc_tools.vhd +++ b/code/trb3sc_tools.vhd @@ -63,18 +63,21 @@ end entity; architecture trb3sc_tools_arch of trb3sc_tools is -signal busflash_rx, busspi_rx, busadc_rx, bussed_rx, busuart_rx, busflashset_rx, busmon_rx, bustrig_rx : CTRLBUS_RX; -signal busflash_tx, busspi_tx, busadc_tx, bussed_tx, busuart_tx, busflashset_tx, busmon_tx, bustrig_tx : CTRLBUS_TX; +signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, busspi_rx, busadc_rx, bussed_rx, busuart_rx, busflashset_rx, busmon_rx, bustrig_rx : CTRLBUS_RX; +signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, busspi_tx, busadc_tx, bussed_tx, busuart_tx, busflashset_tx, busmon_tx, bustrig_tx : CTRLBUS_TX; signal spi_sdi, spi_sdo, spi_sck : std_logic; signal spi_cs : std_logic_vector(15 downto 0); signal lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst : std_logic; signal uart_rx, uart_tx : std_logic; -signal flashset_active : std_logic; +signal flashset_active, debug_active : std_logic; signal flash_cs_i, flash_clk_i, flash_out_i : std_logic; signal flash_cs_s, flash_clk_s, flash_out_s : std_logic; +signal debug_rx, debug_tx : std_logic; +signal debug_status : std_logic_vector(31 downto 0); + begin --------------------------------------------------------------------------- @@ -151,8 +154,8 @@ THE_FLASH_REGS : entity work.load_settings IS_ACTIVE => flashset_active, - BUS_MASTER_TX => BUS_MASTER_OUT, - BUS_MASTER_RX => BUS_MASTER_IN, + BUS_MASTER_TX => bus_flash_rx_out, + BUS_MASTER_RX => bus_flash_tx_in, SPI_MOSI => flash_out_s, SPI_MISO => FLASH_IN, @@ -161,11 +164,17 @@ THE_FLASH_REGS : entity work.load_settings ); - BUS_MASTER_ACTIVE <= flashset_active; + BUS_MASTER_ACTIVE <= flashset_active or debug_active; FLASH_CS <= flash_cs_i when flashset_active = '0' else flash_cs_s; FLASH_CLK <= flash_clk_i when flashset_active = '0' else flash_clk_s; FLASH_OUT <= flash_out_i when flashset_active = '0' else flash_out_s; - + + bus_flash_tx_in <= BUS_MASTER_IN; + bus_debug_tx_in <= BUS_MASTER_IN; + + BUS_MASTER_OUT <= bus_debug_rx_out when debug_active = '1' else + bus_flash_rx_out; + --------------------------------------------------------------------------- -- SED Detection @@ -262,6 +271,35 @@ end generate; ); end generate; +--------------------------------------------------------------------------- +-- Debug Connection +--------------------------------------------------------------------------- +gen_debug : if INCLUDE_DEBUG_INTERFACE = 1 generate + THE_DEBUG : entity work.debuguart + port map( + CLK => CLK, + RESET => RESET, + + RX_IN => debug_rx, + TX_OUT => debug_tx, + + DEBUG_ACTIVE => debug_active, + + BUS_DEBUG_TX => bus_debug_tx_in, + BUS_DEBUG_RX => bus_debug_rx_out, + + STATUS => debug_status + + ); +end generate; +gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate + bus_debug_rx_out.write <= '0'; + bus_debug_rx_out.read <= '0'; + bus_debug_rx_out.timeout <= '0'; + bus_debug_rx_out.addr <= (others => '0'); + bus_debug_rx_out.data <= (others => '0'); + debug_tx <= 'Z'; +end generate; --------------------------------------------------------------------------- -- Trigger logic @@ -333,8 +371,8 @@ end generate; -- 6 SPI CS -- 7 lcd_dc -- 8 lcd_rst --- 9 --- 10 +-- 9 Debug RX +-- 10 Debug TX -- 11 3.3V -- 12 3.3V -- 13 GND @@ -358,9 +396,10 @@ end generate; HEADER_IO(7) <= lcd_dc; HEADER_IO(8) <= lcd_rst; -HEADER_IO(9) <= 'Z'; -HEADER_IO(10) <= 'Z'; +debug_rx <= HEADER_IO(9); +HEADER_IO(10) <= debug_tx; +DEBUG_OUT <= debug_status; end architecture; \ No newline at end of file diff --git a/scripts/nodes_frankfurt.txt b/scripts/nodes_frankfurt.txt index e69de29..80ee426 100644 --- a/scripts/nodes_frankfurt.txt +++ b/scripts/nodes_frankfurt.txt @@ -0,0 +1,13 @@ +// nodes file for parallel place&route + +[jspc29] +SYSTEM = linux +CORENUM = 2 +ENV = /d/jspc29/lattice/36_settings.sh +WORKDIR = /d/jspc22/trb/git/trb3sc/tdctemplate/workdir + +[jspc57] +SYSTEM = linux +CORENUM = 6 +ENV = /d/jspc29/lattice/36_settings.sh +WORKDIR = /d/jspc22/trb/git/trb3sc/tdctemplate/workdir diff --git a/template/config.vhd b/template/config.vhd index baa4db7..1859932 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -28,6 +28,7 @@ package config is constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index 2c7e60a..1ae35c2 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -108,6 +108,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index f5252b1..ba4b793 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -118,6 +118,7 @@ architecture trb3sc_arch of trb3sc_basic is signal time_counter : unsigned(31 downto 0) := (others => '0'); signal led : std_logic_vector(1 downto 0); signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); --Media Interface signal med2int : med2int_array_t(0 to 0); @@ -276,7 +277,10 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 BUS_RX => ctrlbus_rx, BUS_TX => ctrlbus_tx, - + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + ONEWIRE_INOUT => TEMPSENS, --Timing registers TIMERS_OUT => timer @@ -286,7 +290,6 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record -- Bus Handler --------------------------------------------------------------------------- - handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( @@ -299,7 +302,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record CLK => clk_sys, RESET => reset_i, - REGIO_RX => handlerbus_rx, + REGIO_RX => ctrlbus_rx, REGIO_TX => ctrlbus_tx, BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED @@ -354,7 +357,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record BUS_MASTER_IN => ctrlbus_tx, BUS_MASTER_OUT => bus_master_out, BUS_MASTER_ACTIVE => bus_master_active, - DEBUG_OUT => open + DEBUG_OUT => debug_tools ); --------------------------------------------------------------------------- @@ -412,7 +415,6 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record end if; end process; - -- TEST_LINE <= med_stat_debug(15 downto 0); end architecture;