From: Jan Michel Date: Wed, 31 May 2017 16:49:12 +0000 (+0200) Subject: Change reset to include clear on reset. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d4b9252d894eb5d77f104bebf787ee4e9bf2a26f;p=dirich.git Change reset to include clear on reset. Change PLL LOL settings for Serdes --- diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 6f4d296..1c4f4cd 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -36,7 +36,7 @@ signal clock_100, clock_120, clock_200, clock_240, clock_200_raw: std_logic; signal sys_clk_i : std_logic; signal timer : unsigned(24 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; -signal reset_i : std_logic; +signal reset_i, reset_rising, last_reset_i : std_logic; signal debug_reset_handler : std_logic_vector(15 downto 0); signal pll_lock : std_logic; @@ -79,6 +79,8 @@ process begin if timer(24) = '1' then timer <= timer; + elsif reset_rising = '1' then + timer <= 0; elsif pll_lock = '1' then timer <= timer + 1; end if; @@ -107,6 +109,8 @@ THE_RESET_HANDLER : trb_net_reset_handler RESET_OUT <= reset_i; +last_reset_i <= reset_i when rising_edge(CLOCK_IN); +reset_rising <= reset_i and not last_reset_i; --------------------------------------------------------------------------- -- Slow clock for DCDC converters @@ -123,4 +127,4 @@ BUS_TX.nack <= '0'; -end architecture; \ No newline at end of file +end architecture; diff --git a/cores/serdes_sync_0.vhd b/cores/serdes_sync_0.vhd index d1fe058..afcffb8 100644 --- a/cores/serdes_sync_0.vhd +++ b/cores/serdes_sync_0.vhd @@ -88,50 +88,50 @@ architecture v1 of serdes_sync_0 is pwait_tx_rdy: integer := 3000; pport_rx_rdy: string := "ENABLED"; pwait_rx_rdy: integer := 3000); - port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(116) - rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(117) - rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(118) - rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(119) - rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(121) - rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(122) - rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(123) - rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(124) - rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(126) - rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(127) - rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(128) - rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(129) - rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(130) - rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) - rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) - ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(136) - rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) - rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) - ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) - rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(141) - rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(116) + rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(117) + rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(118) + rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(119) + rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(121) + rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(122) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(123) + rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(124) + rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(126) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(127) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(128) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(129) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(130) + rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(136) + rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(141) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) ); - end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/rsl_core_syn.v(72) + end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/rsl_core_syn.v(72) component serdes_sync_0sll_core is generic (PPROTOCOL: string := "G8B10B"; - PLOL_SETTING: integer := 1; + PLOL_SETTING: integer := 3; PDYN_RATE_CTRL: string := "DISABLED"; - PDIFF_VAL_LOCK: integer := 19; - PDIFF_VAL_UNLOCK: integer := 131; + PDIFF_VAL_LOCK: integer := 262; + PDIFF_VAL_UNLOCK: integer := 393; PPCLK_TC: integer := 65536; PDIFF_DIV11_VAL_LOCK: integer := 0; PDIFF_DIV11_VAL_UNLOCK: integer := 0; PPCLK_DIV11_TC: integer := 0); - port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(73) - sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(74) - sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(75) - sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(76) - sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(77) - sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(78) - slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(81) + port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(73) + sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(74) + sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(75) + sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(76) + sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(77) + sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(78) + slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(81) ); - end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(57) + end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.9_x64/ispfpga/sa5p00/data/sll_core_template.v(57) signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9, n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17, n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c, @@ -156,7 +156,7 @@ begin pll_lol <= pll_lol_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b10",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", @@ -180,9 +180,9 @@ begin CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0", CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0", CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00", - CH0_REQ_EN=>"0b0",CH0_RTERM_RX=>"0d11",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b0", + CH0_REQ_EN=>"0b0",CH0_RTERM_RX=>"0d11",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1", CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000", - CH0_RLOS_SEL=>"0b0",CH0_RX_LOS_LVL=>"0b000",CH0_RX_LOS_CEQ=>"0b11", + CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b010",CH0_RX_LOS_CEQ=>"0b11", CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0", CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH0_CDR_MAX_RATE=>"2", CH0_TXAMPLITUDE=>"0d800",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED", @@ -201,8 +201,8 @@ begin D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d10", - D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01", - D_RG_EN=>"0b1",D_RG_SET=>"0b00") + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b11", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") port map (CH0_HDINP=>hdinp,CH1_HDINP=>n106,CH0_HDINN=>hdinn,CH1_HDINN=>n106, D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47, CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n106,CH0_FF_RXI_CLK=>rx_pclk_c,