From: Ludwig Maier Date: Tue, 19 Aug 2014 15:57:59 +0000 (+0200) Subject: nxyter: keep status, working so far X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d4c69f0830422d885c6d0acc4c1d48490023f01a;p=trb3.git nxyter: keep status, working so far --- diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index 13b473d..5c23013 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -48,6 +48,12 @@ entity adc_ad9228 is ADC0_LOCKED_OUT : out std_logic; ADC1_LOCKED_OUT : out std_logic; + ADC0_SLOPPY_FRAME : in std_logic; + ADC1_SLOPPY_FRAME : in std_logic; + + ADC0_ERROR_OUT : out std_logic; + ADC1_ERROR_OUT : out std_logic; + DEBUG_IN : in std_logic_vector(3 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -64,19 +70,26 @@ architecture Behavioral of adc_ad9228 is signal q_1_f : std_logic_vector(19 downto 0); signal q_1 : std_logic_vector(19 downto 0); - -- Data Types --- type adc_data_s is array(0 to 4) of std_logic_vector(13 downto 0); - type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); + -- ADC Data Handler + signal adc0_error_status : std_logic_vector(2 downto 0); + signal adc1_error_status : std_logic_vector(2 downto 0); + signal adc0_error_status_sl : std_logic_vector(2 downto 0); + signal adc1_error_status_sl : std_logic_vector(2 downto 0); + -- Data Types + type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); + -- Output signal adc0_data_clk_o : std_logic; signal adc0_data_o : adc_data_t; signal adc0_locked_o : std_logic; - + signal adc0_error_o : std_logic; + signal adc1_data_clk_o : std_logic; signal adc1_data_o : adc_data_t; signal adc1_locked_o : std_logic; - + signal adc1_error_o : std_logic; + -- RESET Handler type R_STATES is (R_IDLE, R_WAIT_CLKDIV, @@ -203,18 +216,20 @@ begin DEBUG_ENABLE => DEBUG_ENABLE ) port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_ADC0, - DDR_DATA_CLK => DDR_DATA_CLK, - DDR_DATA_IN => q_0, - DATA_A_OUT => adc0_data_o(0), - DATA_B_OUT => adc0_data_o(1), - DATA_C_OUT => adc0_data_o(2), - DATA_D_OUT => adc0_data_o(3), - DATA_CLK_OUT => adc0_data_clk_o, - FRAME_LOCKED_OUT => adc0_locked_o, - ERROR_STATUS_OUT => open, --ERROR_STATUS_OUT, - DEBUG_OUT => open + CLK_IN => CLK_IN, + RESET_IN => RESET_ADC0, + DDR_DATA_CLK => DDR_DATA_CLK, + DDR_DATA_IN => q_0, + DATA_A_OUT => adc0_data_o(0), + DATA_B_OUT => adc0_data_o(1), + DATA_C_OUT => adc0_data_o(2), + DATA_D_OUT => adc0_data_o(3), + DATA_CLK_OUT => adc0_data_clk_o, + SLOPPY_FRAME_IN => ADC0_SLOPPY_FRAME, + FRAME_LOCKED_OUT => adc0_locked_o, + ERROR_STATUS_OUT => adc0_error_status, + ERROR_STATUS_SL_OUT => adc0_error_status_sl, + DEBUG_OUT => open ); adc_ad9228_data_handler_2: entity work.adc_ad9228_data_handler @@ -222,20 +237,48 @@ begin DEBUG_ENABLE => DEBUG_ENABLE ) port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_ADC1, - DDR_DATA_CLK => DDR_DATA_CLK, - DDR_DATA_IN => q_1, - DATA_A_OUT => adc1_data_o(0), - DATA_B_OUT => adc1_data_o(1), - DATA_C_OUT => adc1_data_o(2), - DATA_D_OUT => adc1_data_o(3), - DATA_CLK_OUT => adc1_data_clk_o, - FRAME_LOCKED_OUT => adc1_locked_o, - ERROR_STATUS_OUT => open, --ERROR_STATUS_OUT, - DEBUG_OUT => open + CLK_IN => CLK_IN, + RESET_IN => RESET_ADC1, + DDR_DATA_CLK => DDR_DATA_CLK, + DDR_DATA_IN => q_1, + DATA_A_OUT => adc1_data_o(0), + DATA_B_OUT => adc1_data_o(1), + DATA_C_OUT => adc1_data_o(2), + DATA_D_OUT => adc1_data_o(3), + DATA_CLK_OUT => adc1_data_clk_o, + SLOPPY_FRAME_IN => ADC1_SLOPPY_FRAME, + FRAME_LOCKED_OUT => adc1_locked_o, + ERROR_STATUS_OUT => open, --ERROR_STATUS_OUT, + ERROR_STATUS_SL_OUT => open, --ERROR_STATUS_OUT, + DEBUG_OUT => open ); + ----------------------------------------------------------------------------- + -- Error Status Handler + ----------------------------------------------------------------------------- + PROC_ERROR_STATUS: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + adc0_error_o <= '0'; + adc1_error_o <= '0'; + else + adc0_error_o <= '0'; + adc1_error_o <= '0'; + + if (adc0_error_status /= "000" or + (ADC0_SLOPPY_FRAME = '1' and adc0_error_status_sl /= "000")) then + adc0_error_o <= '1'; + end if; + + if (adc1_error_status /= "000" or + (ADC1_SLOPPY_FRAME = '1' and adc1_error_status_sl /= "000")) then + adc1_error_o <= '1'; + end if; + end if; + end if; + end process PROC_ERROR_STATUS; + ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- @@ -342,4 +385,7 @@ begin ADC0_LOCKED_OUT <= adc0_locked_o; ADC1_LOCKED_OUT <= adc1_locked_o; + ADC0_ERROR_OUT <= adc0_error_o; + ADC1_ERROR_OUT <= adc1_error_o; + end Behavioral; diff --git a/nxyter/source/adc_ad9228_data_handler.vhd b/nxyter/source/adc_ad9228_data_handler.vhd index 815a2e5..a50d9a9 100644 --- a/nxyter/source/adc_ad9228_data_handler.vhd +++ b/nxyter/source/adc_ad9228_data_handler.vhd @@ -23,9 +23,13 @@ entity adc_ad9228_data_handler is DATA_D_OUT : out std_logic_vector(11 downto 0); DATA_CLK_OUT : out std_logic; + SLOPPY_FRAME_IN : in std_logic; FRAME_LOCKED_OUT : out std_logic; ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); - + ERROR_STATUS_SL_OUT : out std_logic_vector(2 downto 0); + -- 2: resync + -- 1: BITSHIFTED, fatal + -- 0: UNDEF, fatal DEBUG_OUT : out std_logic_vector(15 downto 0) ); end adc_ad9228_data_handler; @@ -37,67 +41,88 @@ architecture Behavioral of adc_ad9228_data_handler is type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); type BYTE_STATUS is (B_UNDEF, - B_BITSHIFTED, B_ALIGNED, - B_SHIFTED + B_BYTESHIFTED, + B_BITSHIFTED ); - signal adc_data_shift : adc_data_s; + signal adc_data_shift : adc_data_s; - signal adc_data_m : adc_data_t; - signal adc_data_clk_m : std_logic; + signal adc_data_c_m : adc_data_t; + signal adc_data_clk_c_m : std_logic; + signal adc_byte_status_c : BYTE_STATUS; + signal adc_byte_status_last_c : BYTE_STATUS; + signal adc_frame_clk_ok_c : std_logic; + signal adc_frame_clk_ok_hist_c : std_logic_vector(15 downto 0); + signal adc_frame_locked_c : std_logic; + signal error_status_c : std_logic_vector(2 downto 0); - signal adc_byte_status : BYTE_STATUS; - signal adc_byte_status_last : BYTE_STATUS; - - signal adc_frame_clk_ok : std_logic; - signal adc_frame_clk_ok_hist : std_logic_vector(15 downto 0); - signal adc_frame_locked : std_logic; - signal error_status : std_logic_vector(2 downto 0); + signal adc_data_sl_m : adc_data_t; + signal adc_data_clk_sl_m : std_logic; + signal adc_byte_status_sl : BYTE_STATUS; + signal adc_byte_status_last_sl : BYTE_STATUS; + signal adc_frame_clk_ok_sl : std_logic; + signal adc_frame_clk_ok_hist_sl : std_logic_vector(15 downto 0); + signal adc_frame_locked_sl : std_logic; + signal error_status_sl : std_logic_vector(2 downto 0); + + -- Sloppy Multiplexer + signal adc_data_m : adc_data_t; + signal adc_data_clk_m : std_logic; + signal adc_byte_status : BYTE_STATUS; + signal adc_frame_clk_ok : std_logic; + signal adc_frame_locked : std_logic; -- Clock Transfer - signal adc_fifo_empty : std_logic; - signal adc_fifo_full : std_logic; - signal adc_write_enable : std_logic; - signal adc_read_enable : std_logic; - signal adc_read_enable_t : std_logic; - signal adc_read_enable_tt : std_logic; - signal adc_locked_ff : std_logic; - signal adc_locked_f : std_logic; - signal adc_locked_o : std_logic; - signal adc_error_status_ff : std_logic_vector(2 downto 0); - signal adc_error_status_f : std_logic_vector(2 downto 0); - signal adc_error_status_o : std_logic_vector(2 downto 0); - - signal adc_data : adc_data_t; + signal adc_fifo_empty : std_logic; + signal adc_fifo_full : std_logic; + signal adc_write_enable : std_logic; + signal adc_read_enable : std_logic; + signal adc_read_enable_t : std_logic; + signal adc_read_enable_tt : std_logic; + signal adc_locked_ff : std_logic; + signal adc_locked_f : std_logic; + signal adc_locked_o : std_logic; + signal adc_error_status_c_ff : std_logic_vector(2 downto 0); + signal adc_error_status_c_f : std_logic_vector(2 downto 0); + signal adc_error_status_c_o : std_logic_vector(2 downto 0); + signal adc_error_status_sl_ff : std_logic_vector(2 downto 0); + signal adc_error_status_sl_f : std_logic_vector(2 downto 0); + signal adc_error_status_sl_o : std_logic_vector(2 downto 0); + + signal adc_data : adc_data_t; -- Output - signal adc_data_clk_o : std_logic; - signal adc_data_o : adc_data_t; + signal adc_data_clk_o : std_logic; + signal adc_data_o : adc_data_t; -- RESET Handler - signal RESET_DDR_DATA_CLK_F : std_logic; - signal RESET_DDR_DATA_CLK : std_logic; + signal RESET_DDR_DATA_CLK_F : std_logic; + signal RESET_DDR_DATA_CLK : std_logic; -- Attributes attribute syn_keep : boolean; - attribute syn_keep of RESET_DDR_DATA_CLK_F : signal is true; - attribute syn_keep of RESET_DDR_DATA_CLK : signal is true; + attribute syn_keep of RESET_DDR_DATA_CLK_F : signal is true; + attribute syn_keep of RESET_DDR_DATA_CLK : signal is true; - attribute syn_keep of adc_locked_ff : signal is true; - attribute syn_keep of adc_locked_f : signal is true; + attribute syn_keep of adc_locked_ff : signal is true; + attribute syn_keep of adc_locked_f : signal is true; - attribute syn_keep of adc_error_status_ff : signal is true; - attribute syn_keep of adc_error_status_f : signal is true; + attribute syn_keep of adc_error_status_c_ff : signal is true; + attribute syn_keep of adc_error_status_c_f : signal is true; + attribute syn_keep of adc_error_status_sl_ff : signal is true; + attribute syn_keep of adc_error_status_sl_f : signal is true; attribute syn_preserve : boolean; - attribute syn_preserve of RESET_DDR_DATA_CLK_F : signal is true; - attribute syn_preserve of RESET_DDR_DATA_CLK : signal is true; + attribute syn_preserve of RESET_DDR_DATA_CLK_F : signal is true; + attribute syn_preserve of RESET_DDR_DATA_CLK : signal is true; - attribute syn_preserve of adc_locked_ff : signal is true; - attribute syn_preserve of adc_locked_f : signal is true; + attribute syn_preserve of adc_locked_ff : signal is true; + attribute syn_preserve of adc_locked_f : signal is true; - attribute syn_preserve of adc_error_status_ff : signal is true; - attribute syn_preserve of adc_error_status_f : signal is true; + attribute syn_preserve of adc_error_status_c_ff : signal is true; + attribute syn_preserve of adc_error_status_c_f : signal is true; + attribute syn_preserve of adc_error_status_sl_ff : signal is true; + attribute syn_preserve of adc_error_status_sl_f : signal is true; begin @@ -131,6 +156,7 @@ begin ----------------------------------------------------------------------------- PROC_LOCK_TO_ADC_FRAME: process(DDR_DATA_CLK) + variable sloppy_ctr : unsigned(3 downto 0); begin if (rising_edge(DDR_DATA_CLK)) then if (RESET_DDR_DATA_CLK = '1') then @@ -139,16 +165,25 @@ begin end loop; for I in 0 to 3 loop - adc_data_m(I) <= (others => '0'); + adc_data_sl_m(I) <= (others => '0'); + adc_data_c_m(I) <= (others => '0'); end loop; - adc_data_clk_m <= '0'; + adc_data_clk_sl_m <= '0'; + adc_data_clk_c_m <= '0'; - adc_byte_status <= B_UNDEF; - adc_byte_status_last <= B_UNDEF; - adc_frame_clk_ok <= '0'; - adc_frame_clk_ok_hist <= (others => '0'); - adc_frame_locked <= '0'; - error_status <= (others => '0'); + adc_byte_status_c <= B_UNDEF; + adc_byte_status_last_c <= B_UNDEF; + adc_frame_clk_ok_c <= '0'; + adc_frame_clk_ok_hist_c <= (others => '0'); + adc_frame_locked_c <= '0'; + error_status_c <= (others => '0'); + + adc_byte_status_sl <= B_UNDEF; + adc_byte_status_last_sl <= B_UNDEF; + adc_frame_clk_ok_sl <= '0'; + adc_frame_clk_ok_hist_sl <= (others => '0'); + adc_frame_locked_sl <= '0'; + error_status_sl <= (others => '0'); else -- Store new incoming Data in Shift Registers for I in 0 to 4 loop @@ -159,38 +194,40 @@ begin adc_data_shift(I)(13 downto 4) <= adc_data_shift(I)(9 downto 0); end loop; + ----------------------------------------------------------------------- -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock + ----------------------------------------------------------------------- case adc_data_shift(4)(11 downto 0) is when "111111000000" => -- Input Data is correct and new Frame is available for I in 0 to 3 loop - adc_data_m(I) <= adc_data_shift(I)(11 downto 0); + adc_data_c_m(I) <= adc_data_shift(I)(11 downto 0); end loop; - adc_data_clk_m <= '1'; - adc_frame_clk_ok <= '1'; - adc_byte_status <= B_ALIGNED; + adc_data_clk_c_m <= '1'; + adc_frame_clk_ok_c <= '1'; + adc_byte_status_c <= B_ALIGNED; when "111100000011" => -- Input Data is correct and new Frame is available, -- but byte shifted by one for I in 0 to 3 loop - adc_data_m(I) <= adc_data_shift(I)(13 downto 2); + adc_data_c_m(I) <= adc_data_shift(I)(13 downto 2); end loop; - adc_data_clk_m <= '1'; - adc_frame_clk_ok <= '1'; - adc_byte_status <= B_SHIFTED; + adc_data_clk_c_m <= '1'; + adc_frame_clk_ok_c <= '1'; + adc_byte_status_c <= B_BYTESHIFTED; when "110000001111" | "000011111100" => -- Input Data is correct - adc_data_clk_m <= '0'; - adc_frame_clk_ok <= '1'; - adc_byte_status <= B_ALIGNED; + adc_data_clk_c_m <= '0'; + adc_frame_clk_ok_c <= '1'; + adc_byte_status_c <= B_ALIGNED; when "000000111111" | "001111110000" => -- Input Data is correct - adc_data_clk_m <= '0'; - adc_frame_clk_ok <= '1'; - adc_byte_status <= B_SHIFTED; + adc_data_clk_c_m <= '0'; + adc_frame_clk_ok_c <= '1'; + adc_byte_status_c <= B_BYTESHIFTED; when "000001111110" | "000111111000" | @@ -198,54 +235,163 @@ begin "111110000001" | "111000000111" | "100000011111" => - adc_data_clk_m <= '0'; - adc_frame_clk_ok <= '0'; - adc_byte_status <= B_BITSHIFTED; - + adc_data_clk_c_m <= '0'; + adc_frame_clk_ok_c <= '0'; + adc_byte_status_c <= B_BITSHIFTED; + when others => -- Input Data is invalid, Fatal Error of DDR Data, needs reset. - adc_data_clk_m <= '0'; - adc_frame_clk_ok <= '0'; - adc_byte_status <= B_UNDEF; + adc_data_clk_c_m <= '0'; + adc_frame_clk_ok_c <= '0'; + adc_byte_status_c <= B_UNDEF; end case; -- Determin ADC Frame Lock Status - adc_frame_clk_ok_hist(0) <= adc_frame_clk_ok; - adc_frame_clk_ok_hist(15 downto 1) <= - adc_frame_clk_ok_hist(14 downto 0); + adc_frame_clk_ok_hist_c(0) <= adc_frame_clk_ok_c; + adc_frame_clk_ok_hist_c(15 downto 1) <= + adc_frame_clk_ok_hist_c(14 downto 0); - if (adc_frame_clk_ok_hist = x"ffff") then - adc_frame_locked <= '1'; + if (adc_frame_clk_ok_hist_c = x"ffff") then + adc_frame_locked_c <= '1'; else - adc_frame_locked <= '0'; + adc_frame_locked_c <= '0'; end if; -- Error Status - adc_byte_status_last <= adc_byte_status; - if (adc_byte_status /= adc_byte_status_last) then - error_status(2) <= '1'; + adc_byte_status_last_c <= adc_byte_status_c; + if (adc_byte_status_c /= adc_byte_status_last_c) then + error_status_c(2) <= '1'; else - error_status(2) <= '0'; + error_status_c(2) <= '0'; end if; if (adc_byte_status = B_BITSHIFTED) then - error_status(1) <= '1'; + error_status_c(1) <= '1'; else - error_status(1) <= '0'; + error_status_c(1) <= '0'; end if; if (adc_byte_status = B_UNDEF) then - error_status(0) <= '1'; + error_status_c(0) <= '1'; else - error_status(0) <= '0'; + error_status_c(0) <= '0'; end if; - end if; + ----------------------------------------------------------------------- + -- Sloppy Frame Handler + ----------------------------------------------------------------------- + if (adc_data_shift(4)(6 downto 5) = "10") then + -- Input Data is correct and new Frame is available + for I in 0 to 3 loop + adc_data_sl_m(I) <= adc_data_shift(I)(11 downto 0); + end loop; + adc_data_clk_sl_m <= '1'; + adc_frame_clk_ok_sl <= '1'; + adc_byte_status_sl <= B_ALIGNED; + elsif (adc_data_shift(4)(8 downto 7) = "10") then + -- Input Data is correct and new Frame is available, + -- but byte shifted by one + for I in 0 to 3 loop + adc_data_sl_m(I) <= adc_data_shift(I)(13 downto 2); + end loop; + adc_data_clk_sl_m <= '1'; + adc_frame_clk_ok_sl <= '1'; + adc_byte_status_sl <= B_BYTESHIFTED; + + elsif ((adc_data_shift(4)(10 downto 9) = "10") or + (adc_data_shift(4)(2 downto 1) = "10")) then + -- Input Data is correct + adc_data_clk_sl_m <= '0'; + adc_frame_clk_ok_sl <= '1'; + adc_byte_status_sl <= B_ALIGNED; + + elsif (((adc_data_shift(4)(11) = '0') and + (adc_data_shift(4)(0) = '1')) or + (adc_data_shift(4)(4 downto 2) = "10")) then + -- Input Data is correct + adc_data_clk_sl_m <= '0'; + adc_frame_clk_ok_sl <= '1'; + adc_byte_status_sl <= B_BYTESHIFTED; + + elsif ((adc_data_shift(4)( 1 downto 0) = "10") or + (adc_data_shift(4)( 3 downto 2) = "10") or + (adc_data_shift(4)( 5 downto 4) = "10") or + (adc_data_shift(4)( 7 downto 6) = "10") or + (adc_data_shift(4)( 9 downto 8) = "10") or + (adc_data_shift(4)(11 downto 10) = "10")) then + adc_data_clk_sl_m <= '0'; + adc_frame_clk_ok_sl <= '0'; + adc_byte_status_sl <= B_BITSHIFTED; + else + -- Input Data is invalid, Fatal Error of DDR Data, needs reset. + adc_data_clk_sl_m <= '0'; + adc_frame_clk_ok_sl <= '0'; + adc_byte_status_sl <= B_UNDEF; + end if; + + -- Determin ADC Frame Lock Status + adc_frame_clk_ok_hist_sl(0) <= adc_frame_clk_ok_sl; + adc_frame_clk_ok_hist_sl(15 downto 1) <= + adc_frame_clk_ok_hist_sl(14 downto 0); + + if (adc_frame_clk_ok_hist_sl = x"ffff") then + adc_frame_locked_sl <= '1'; + else + sloppy_ctr := (others => '0'); + for I in 0 to 15 loop + if (adc_frame_clk_ok_hist_sl(I) = '1') then + sloppy_ctr := sloppy_ctr + 1; + end if; + end loop; -- I + if (sloppy_ctr < 13) then + adc_frame_locked_sl <= '0'; + else + adc_frame_locked_sl <= '1'; + end if; + end if; + + -- Error Status + adc_byte_status_last_sl <= adc_byte_status_sl; + if (adc_byte_status_sl /= adc_byte_status_last_sl) then + error_status_sl(2) <= '1'; + else + error_status_sl(2) <= '0'; + end if; + + if (adc_byte_status_sl = B_BITSHIFTED) then + error_status_sl(1) <= '1'; + else + error_status_sl(1) <= '0'; + end if; + + if (adc_byte_status = B_UNDEF) then + error_status_sl(0) <= '1'; + else + error_status_sl(0) <= '0'; + end if; + + end if; + end if; end process PROC_LOCK_TO_ADC_FRAME; + PROC_SLOPPY_MULTIPLEXER: process(SLOPPY_FRAME_IN) + begin + if (SLOPPY_FRAME_IN = '0') then + adc_data_m <= adc_data_c_m; + adc_data_clk_m <= adc_data_clk_c_m; + adc_frame_clk_ok <= adc_frame_clk_ok_c; + adc_frame_locked <= adc_frame_locked_c; + else + adc_data_m <= adc_data_sl_m; + adc_data_clk_m <= adc_data_clk_sl_m; + adc_frame_clk_ok <= adc_frame_clk_ok_sl; + adc_frame_locked <= adc_frame_locked_sl; + end if; + end process PROC_SLOPPY_MULTIPLEXER; + ----------------------------------------------------------------------------- -- Domain Tansfer of Data to CLK_IN ----------------------------------------------------------------------------- @@ -303,24 +449,29 @@ begin ----------------------------------------------------------------------------- -- Domain Transfer of Control Signals ----------------------------------------------------------------------------- - adc_locked_ff <= adc_frame_locked when rising_edge(CLK_IN); - adc_locked_f <= adc_locked_ff when rising_edge(CLK_IN); - adc_locked_o <= adc_locked_f when rising_edge(CLK_IN); - - adc_error_status_ff <= error_status when rising_edge(CLK_IN); - adc_error_status_f <= adc_error_status_ff when rising_edge(CLK_IN); - adc_error_status_o <= adc_error_status_f when rising_edge(CLK_IN); + adc_locked_ff <= adc_frame_locked when rising_edge(CLK_IN); + adc_locked_f <= adc_locked_ff when rising_edge(CLK_IN); + adc_locked_o <= adc_locked_f when rising_edge(CLK_IN); + + adc_error_status_c_ff <= error_status_c when rising_edge(CLK_IN); + adc_error_status_c_f <= adc_error_status_c_ff when rising_edge(CLK_IN); + adc_error_status_c_o <= adc_error_status_c_f when rising_edge(CLK_IN); + + adc_error_status_sl_ff <= error_status_sl when rising_edge(CLK_IN); + adc_error_status_sl_f <= adc_error_status_sl_ff when rising_edge(CLK_IN); + adc_error_status_sl_o <= adc_error_status_sl_f when rising_edge(CLK_IN); ----------------------------------------------------------------------------- -- Output ----------------------------------------------------------------------------- - DATA_A_OUT <= adc_data_o(0); - DATA_B_OUT <= adc_data_o(1); - DATA_C_OUT <= adc_data_o(2); - DATA_D_OUT <= adc_data_o(3); - DATA_CLK_OUT <= adc_data_clk_o; - - FRAME_LOCKED_OUT <= adc_locked_o; - ERROR_STATUS_OUT <= adc_error_status_o; + DATA_A_OUT <= adc_data_o(0); + DATA_B_OUT <= adc_data_o(1); + DATA_C_OUT <= adc_data_o(2); + DATA_D_OUT <= adc_data_o(3); + DATA_CLK_OUT <= adc_data_clk_o; + + FRAME_LOCKED_OUT <= adc_locked_o; + ERROR_STATUS_OUT <= adc_error_status_c_o; + ERROR_STATUS_SL_OUT <= adc_error_status_sl_o; end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 231091f..0bf37d5 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -138,9 +138,12 @@ architecture Behavioral of nx_data_receiver is signal adc_data_s : std_logic_vector(11 downto 0); signal adc_data_s_clk : std_logic; - signal adc_notlock_ctr : unsigned(11 downto 0); + signal adc_sloppy_frame : std_logic; signal ADC_DEBUG : std_logic_vector(15 downto 0); + signal adc_error : std_logic; + signal adc_error_p : std_logic; + -- Merge Data Streams signal merge_handler_reset : std_logic; signal merge_status : std_logic_vector(1 downto 0); @@ -176,6 +179,7 @@ architecture Behavioral of nx_data_receiver is signal error_o : std_logic; signal error_status_bits : std_logic_vector(15 downto 0); signal adc_notlock_counter : unsigned(27 downto 0); + signal adc_error_counter : unsigned(27 downto 0); signal nx_online : std_logic; signal nx_online_shift : std_logic_vector(1 downto 0); signal reset_after_offline : std_logic; @@ -230,7 +234,6 @@ architecture Behavioral of nx_data_receiver is signal nx_frame_word_delay_r : unsigned(1 downto 0); signal adc_dt_error_ctr_r : unsigned(11 downto 0); signal timestamp_dt_error_ctr_r : unsigned(11 downto 0); - signal adc_notlock_ctr_r : unsigned(11 downto 0); signal merge_error_ctr_r : unsigned(11 downto 0); signal nx_frame_synced_rr : std_logic; signal nx_frame_synced_r : std_logic; @@ -891,6 +894,12 @@ begin ADC0_LOCKED_OUT => adc_locked, ADC1_LOCKED_OUT => open, + ADC0_SLOPPY_FRAME => adc_sloppy_frame, + ADC1_SLOPPY_FRAME => '0', + + ADC0_ERROR_OUT => adc_error, + ADC1_ERROR_OUT => open, + DEBUG_IN => adc_debug_type_r, DEBUG_OUT => ADC_DEBUG ); @@ -1062,6 +1071,14 @@ begin LEVEL_IN => not adc_locked, PULSE_OUT => adc_notlocked_p ); + + level_to_pulse_ADC_ERROR: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => adc_error, + PULSE_OUT => adc_error_p + ); -- Counters PROC_RESYNC_COUNTER: process(CLK_IN) @@ -1534,6 +1551,7 @@ begin error_status_bits <= (others => '0'); error_o <= '0'; adc_notlock_counter <= (others => '0'); + adc_error_counter <= (others => '0'); else error_status_bits(0) <= not nx_online; error_status_bits(1) <= frame_rate_error; @@ -1575,6 +1593,10 @@ begin adc_notlock_counter <= adc_notlock_counter + 1; end if; + if (adc_error_p = '1') then + adc_error_counter <= adc_error_counter + 1; + end if; + end if; end if; end process PROC_ERROR_STATUS; @@ -1619,13 +1641,11 @@ begin nx_frame_synced_r <= '0'; adc_dt_error_ctr_r <= (others => '0'); timestamp_dt_error_ctr_r <= (others => '0'); - adc_notlock_ctr_r <= (others => '0'); merge_error_ctr_r <= (others => '0'); else nx_frame_synced_r <= nx_frame_synced_rr; adc_dt_error_ctr_r <= adc_dt_error_ctr; timestamp_dt_error_ctr_r <= timestamp_dt_error_ctr; - adc_notlock_ctr_r <= adc_notlock_ctr; merge_error_ctr_r <= merge_error_ctr; end if; end if; @@ -1653,6 +1673,7 @@ begin adc_debug_type_r <= (others => '0'); debug_mode <= (others => '0'); disable_adc_r <= '0'; + adc_sloppy_frame <= '0'; else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -1690,6 +1711,7 @@ begin when x"0004" => slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate); slv_data_out_o(30 downto 28) <= (others => '0'); + slv_data_out_o(30) <= adc_sloppy_frame; slv_data_out_o(31) <= disable_adc_r; slv_ack_o <= '1'; @@ -1727,13 +1749,13 @@ begin std_logic_vector(adc_reset_ctr); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - - when x"000a" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(adc_notlock_ctr_r); - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; + when x"000a" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(adc_notlock_counter); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + when x"000b" => slv_data_out_o(11 downto 0) <= std_logic_vector(merge_error_ctr_r); @@ -1772,10 +1794,10 @@ begin when x"0011" => slv_data_out_o(27 downto 0) <= - std_logic_vector(adc_notlock_counter); - slv_data_out_o(31 downto 28) <= (others => '0'); + std_logic_vector(adc_error_counter); + slv_data_out_o(31 downto 15) <= (others => '0'); slv_ack_o <= '1'; - + when x"001d" => slv_data_out_o(1 downto 0) <= johnson_counter_sync_r; slv_data_out_o(31 downto 2) <= (others => '0'); @@ -1803,6 +1825,7 @@ begin when x"0004" => disable_adc_r <= SLV_DATA_IN(31); + adc_sloppy_frame <= SLV_DATA_IN(30); slv_ack_o <= '1'; when x"0006" => diff --git a/nxyter/source/nxyter.pdf b/nxyter/source/nxyter.pdf index 04fdedc..ebc6d71 100644 Binary files a/nxyter/source/nxyter.pdf and b/nxyter/source/nxyter.pdf differ diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 817a242..ba05230 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -247,6 +247,10 @@ component adc_ad9228 ADC1_DATA_CLK_OUT : out std_logic; ADC0_LOCKED_OUT : out std_logic; ADC1_LOCKED_OUT : out std_logic; + ADC0_SLOPPY_FRAME : in std_logic; + ADC1_SLOPPY_FRAME : in std_logic; + ADC0_ERROR_OUT : out std_logic; + ADC1_ERROR_OUT : out std_logic; DEBUG_IN : in std_logic_vector(3 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 08fa058..8545a38 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -99,7 +99,8 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/parity_error_b*" MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_CLKDIV*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_ADC0*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_data_handler_*/adc_frame_locked*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_data_handler_*/error_status*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_data_handler_*/error_status_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sloppy_frame*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index bb2671e..f43a374 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -2,7 +2,7 @@ -i 2 -l 5 -n 40 --t 40 +-t 1 -s 1 -c 1 -e 2