From: Jan Michel <j.michel@gsi.de>
Date: Wed, 26 Jul 2017 16:26:22 +0000 (+0200)
Subject: Update ADC AddOn design
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d60c619fe30bebe4b94b95fc00ef265e774ed1f7;p=trb3sc.git

Update ADC AddOn design
---

diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj
index 6138d95..c89cf14 100644
--- a/adcaddon/trb3sc_adc.prj
+++ b/adcaddon/trb3sc_adc.prj
@@ -191,4 +191,4 @@ add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_handler.vhd"
 add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_slowcontrol_data_buffer.vhd"
 
 add_file -vhdl -lib "work" "trb3sc_adc.vhd"
-add_file -constraint "trb3sc_adc.sdc"
+#add_file -constraint "trb3sc_adc.sdc"
diff --git a/adcaddon/trb3sc_adc.vhd b/adcaddon/trb3sc_adc.vhd
index a17289f..a5e3c1c 100644
--- a/adcaddon/trb3sc_adc.vhd
+++ b/adcaddon/trb3sc_adc.vhd
@@ -338,6 +338,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
 ---------------------------------------------------------------------------
 gen_reallogic : if USE_DUMMY_READOUT = 0 generate
   THE_ADC : entity work.adc_handler
+    generic map(
+      IS_TRB3 = 0
+      )
     port map(
       CLK        => clk_sys,
       CLK_ADCRAW => CLK_CORE_PCLK, --clk_full_osc,