From: Tobias Weber <toweber86@gmail.com>
Date: Thu, 19 Jul 2018 10:03:41 +0000 (+0200)
Subject: output and input pipeline stages for data simulation.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d7737b2878f5e12725405ba41e68a40b8baf98b5;p=trb3.git

output and input pipeline stages for data simulation.
---

diff --git a/mupix/Mupix8/sources/Simulation/DataOutput.vhd b/mupix/Mupix8/sources/Simulation/DataOutput.vhd
index bf996f8..c9e7f9b 100644
--- a/mupix/Mupix8/sources/Simulation/DataOutput.vhd
+++ b/mupix/Mupix8/sources/Simulation/DataOutput.vhd
@@ -20,32 +20,50 @@ architecture rtl of DataOutput is
 
   signal cnt5 : integer range 0 to 4 := 4;
 
+  signal datain_i   : std_logic_vector(9 downto 0) := (others => '0');
+  signal empty_i    : std_logic                    := '0';
+  signal data_out_i : std_logic_vector(1 downto 0);
+
   type output_fsm_type is (idle, readfifo, sending);
   signal output_state : output_fsm_type := idle;
 
 begin  -- architecture rtl
 
+  -- purpose: register input signals to state machine
+  input_register : process (clk) is
+  begin  -- process input_register
+    if rising_edge(clk) then            -- rising clock edge
+      if reset = '1' then               -- synchronous reset (active high)
+        datain_i <= (others => '0');
+        empty_i  <= '0';
+      else
+        datain_i <= datain;
+        empty_i  <= empty;
+      end if;
+    end if;
+  end process input_register;
+
   output_proc : process (clk) is
   begin  -- process output_proc
     if rising_edge(clk) then            -- rising clock edge
       if reset = '1' then
         output_state <= idle;
         cnt5         <= 0;
-        dataout      <= (others => '0');
+        data_out_i   <= (others => '0');
       else
-        dataout <= (others => '0');
-        rden    <= '0';
+        data_out_i <= (others => '0');
+        rden       <= '0';
         case output_state is
           when idle =>
             cnt5 <= 0;
-            if empty = '0' then
+            if empty_i = '0' then
               output_state <= readfifo;
               rden         <= '1';
             end if;
           when readfifo =>
             output_state <= sending;
           when sending =>
-            dataout <= datain((cnt5 + 1)*2 - 1 downto cnt5*2);
+            data_out_i <= datain_i((cnt5 + 1)*2 - 1 downto cnt5*2);
             -- counter
             if cnt5 < 4 then
               cnt5 <= cnt5 + 1;
@@ -58,7 +76,7 @@ begin  -- architecture rtl
                 rden <= '1';
               end if;
             elsif cnt5 = 4 then
-              if empty = '0' then
+              if empty_i = '0' then
                 output_state <= sending;
               else
                 output_state <= idle;
@@ -69,4 +87,15 @@ begin  -- architecture rtl
     end if;
   end process output_proc;
 
+  data_output_pipe : process (clk) is
+  begin  -- process data_output_pipe
+    if rising_edge(clk) then            -- rising clock edge
+      if reset = '1' then               -- synchronous reset (active high)
+        dataout <= (others => '0');
+      else
+        dataout <= data_out_i;
+      end if;
+    end if;
+  end process data_output_pipe;
+
 end architecture rtl;
diff --git a/mupix/Mupix8/sources/Simulation/LinkSimulation.vhd b/mupix/Mupix8/sources/Simulation/LinkSimulation.vhd
index 893a058..ff0bc3c 100644
--- a/mupix/Mupix8/sources/Simulation/LinkSimulation.vhd
+++ b/mupix/Mupix8/sources/Simulation/LinkSimulation.vhd
@@ -130,22 +130,11 @@ begin  -- architecture rtl
       rden    => fifo_rden_i,
       dataout => data_out_i);
 
-  data_output_pipe : process (sim_clk_i) is
-  begin  -- process data_output_pipe
-    if rising_edge(sim_clk_i) then      -- rising clock edge
-      if reset_reg = '1' then               -- synchronous reset (active high)
-        data_out_reg <= (others => '0');
-      else
-        data_out_reg <= data_out_i;
-      end if;
-    end if;
-  end process data_output_pipe;
-
   simlink_oddr : ODDRXD1
     port map (
       SCLK => sim_clk_i,
-      DA   => data_out_reg(0),
-      DB   => data_out_reg(1),
+      DA   => data_out_i(0),
+      DB   => data_out_i(1),
       Q    => data_out);
 
   dataclk <= data_clk_i;
diff --git a/mupix/Mupix8/sources/Simulation/Mupix8StateMachine.vhd b/mupix/Mupix8/sources/Simulation/Mupix8StateMachine.vhd
index 4ad1edd..ced8b0e 100644
--- a/mupix/Mupix8/sources/Simulation/Mupix8StateMachine.vhd
+++ b/mupix/Mupix8/sources/Simulation/Mupix8StateMachine.vhd
@@ -50,6 +50,9 @@ architecture rtl of MupixStateMachine is
   signal word_cnt_i     : unsigned(4 downto 0)  := (others => '0');
   signal slowdown_cnt_i : unsigned(15 downto 0) := (others => '0');
 
+  signal wr_en_i    : std_logic                    := '0';
+  signal data_out_i : std_logic_vector(9 downto 0) := (others => '0');
+
 begin  -- architecture rtl
 
   -- 8b10b encoding of data
@@ -76,9 +79,9 @@ begin  -- architecture rtl
   begin  -- process encoder_falling_to_rise
     if rising_edge(clk) then            -- rising clock edge
       if reset = '1' then               -- synchronous reset (active high)
-        data_out <= (others => '0');
+        data_out_i <= (others => '0');
       else
-        data_out <= data_encoded_falling;
+        data_out_i <= data_encoded_falling;
       end if;
     end if;
   end process encoder_falling_to_rise;
@@ -91,12 +94,12 @@ begin  -- architecture rtl
     if rising_edge(clk) then
       if reset = '1' then
         wait_after_reset  := 0;
-        wr_en             <= '0';
+        wr_en_i             <= '0';
         start_i           <= '0';
         wait_before_start := 0;
       else
         if wait_after_reset = 3 then
-          wr_en <= '1';
+          wr_en_i <= '1';
         else
           wait_after_reset := wait_after_reset + 1;
         end if;
@@ -260,4 +263,17 @@ begin  -- architecture rtl
     end if;
   end process mupix_proc;
 
+  data_output_pipe : process (clk) is
+  begin  -- process data_output_pipe
+    if rising_edge(clk) then            -- rising clock edge
+      if reset = '1' then               -- synchronous reset (active high)
+        wr_en    <= '0';
+        data_out <= (others => '0');
+      else
+        wr_en    <= wr_en_i;
+        data_out <= data_out_i;
+      end if;
+    end if;
+  end process data_output_pipe;
+
 end architecture rtl;