From: Jan Michel Date: Tue, 2 Jun 2015 14:45:34 +0000 (+0200) Subject: some more initial files for TRB3sc X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d8b7103dfbac820e1986a0d98fff665e1473b115;p=trb3sc.git some more initial files for TRB3sc --- diff --git a/.gitignore b/.gitignore index 20067ab..79b2dbc 100644 --- a/.gitignore +++ b/.gitignore @@ -29,3 +29,4 @@ work *stacktrace.txt *edn licbug.txt +old diff --git a/cores/pll_in240_out200.ipx b/cores/pll_in240_out200.ipx new file mode 100644 index 0000000..db362ae --- /dev/null +++ b/cores/pll_in240_out200.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/cores/pll_in240_out200.lpc b/cores/pll_in240_out200.lpc new file mode 100644 index 0000000..6bc1647 --- /dev/null +++ b/cores/pll_in240_out200.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_in240_out200 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/28/2015 +Time=17:37:56 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=240 +Div=6 +ClkOPBp=0 +Post=4 +U_OFrq=200 +OP_Tol=0.0 +OFrq=200.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=5 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=100 +OK_Tol=0.0 +KFrq=100.000000 +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=1.753251 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=1 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw diff --git a/cores/pll_in240_out200.vhd b/cores/pll_in240_out200.vhd new file mode 100644 index 0000000..f765bca --- /dev/null +++ b/cores/pll_in240_out200.vhd @@ -0,0 +1,102 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw + +-- Thu May 28 17:37:56 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in240_out200 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in240_out200 : entity is true; +end pll_in240_out200; + +architecture Structure of pll_in240_out200 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 5, CLKI_DIV=> 6, + FIN=> "240.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in240_out200 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/pinout/trb3sc_basic.lpf b/pinout/trb3sc_basic.lpf index 5a474ab..26524ff 100644 --- a/pinout/trb3sc_basic.lpf +++ b/pinout/trb3sc_basic.lpf @@ -1,6 +1,31 @@ COMMERCIAL ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_CORE_PCLK 200 MHz; #actually 240! +FREQUENCY PORT CLK_CORE_PLL_LEFT 240 MHz; +FREQUENCY PORT CLK_CORE_PLL_RIGHT 240 MHz; + +FREQUENCY PORT CLK_SUPPL_PCLK 125 MHz; +FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125 MHz; +FREQUENCY PORT CLK_SUPPL_PLL_RIGHT 125 MHz; + +FREQUENCY PORT CLK_EXT_PCLK 200 MHz; +FREQUENCY PORT CLK_EXT_PLL_LEFT 200 MHz; +FREQUENCY PORT CLK_EXT_PLL_RIGHT 200 MHz; + + +#If these signals do not exist, somebody messed around with the design... +MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns; +GSR_NET NET "GSR_N"; ################################################################# # Clock I/O @@ -47,7 +72,7 @@ LOCATE COMP "BACK_GPIO_13" SITE "H25"; LOCATE COMP "BACK_GPIO_14" SITE "A31"; LOCATE COMP "BACK_GPIO_15" SITE "B31"; DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; -IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; LOCATE COMP "BACK_LVDS_0" SITE "V2"; LOCATE COMP "BACK_LVDS_1" SITE "T4"; @@ -154,7 +179,7 @@ IOBUF GROUP "BACK_3V3_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; LOCATE COMP "DQLL0_0" SITE "AA2"; #was "DQLL0_0_P" 1 LOCATE COMP "DQLL0_1" SITE "AB2"; #was "DQLL0_1_P" 5 LOCATE COMP "DQLL0_2" SITE "AA4"; #was "DQLL0_2_P" 9 -LOCATE COMP "DQSLL0" SITE "AA10" #was "DQSLL0_T" 13 +LOCATE COMP "DQSLL0" SITE "AA10"; #was "DQSLL0_T" 13 LOCATE COMP "DQLL0_3" SITE "AA5"; #was "DQLL0_3_P" 17 LOCATE COMP "DQLL0_4" SITE "Y7"; #was "DQLL0_4_P" 21 LOCATE COMP "DQLL2_0" SITE "AC5"; #was "DQLL2_0_P" 25 @@ -182,23 +207,23 @@ LOCATE COMP "DQSUR0" SITE "M26"; #was "DQSUR0_T" 113 LOCATE COMP "DQUR0_2" SITE "L34"; #was "DQUR0_2_P" 117 LOCATE COMP "DQUR0_3" SITE "K29"; #was "DQUR0_3_P" 121 LOCATE COMP "DQUR0_4" SITE "K34"; #was "DQUR0_4_P" 125 -LOCATE COMP "DQLR0_0" SITE "AB34" #was "DQLR0_0_P" 129 -LOCATE COMP "DQLR0_1" SITE "AA25" #was "DQLR0_1_P" 133 -LOCATE COMP "DQLR0_2" SITE "AC34" #was "DQLR0_2_P" 137 -LOCATE COMP "DQSLR0" SITE "AB30" #was "DQSLR0_T" 141 -LOCATE COMP "DQLR0_3" SITE "AA31" #was "DQLR0_3_P" 145 -LOCATE COMP "DQLR0_4" SITE "AA28" #was "DQLR0_4_P" 149 +LOCATE COMP "DQLR0_0" SITE "AB34"; #was "DQLR0_0_P" 129 +LOCATE COMP "DQLR0_1" SITE "AA25"; #was "DQLR0_1_P" 133 +LOCATE COMP "DQLR0_2" SITE "AC34"; #was "DQLR0_2_P" 137 +LOCATE COMP "DQSLR0" SITE "AB30"; #was "DQSLR0_T" 141 +LOCATE COMP "DQLR0_3" SITE "AA31"; #was "DQLR0_3_P" 145 +LOCATE COMP "DQLR0_4" SITE "AA28"; #was "DQLR0_4_P" 149 -LOCATE COMP "DQLR1_0" SITE "AD31" #was "DQLR1_0_P" 169 -LOCATE COMP "DQLR1_1" SITE "AB32" #was "DQLR1_1_P" 173 -LOCATE COMP "DQLR1_2" SITE "AE34" #was "DQLR1_2_P" 177 -LOCATE COMP "DQSLR1" SITE "AB26" #was "DQSLR1_T" 181 -LOCATE COMP "DQLR1_3" SITE "AD33" #was "DQLR1_3_P" 185 -LOCATE COMP "DQLR1_4" SITE "AF34" #was "DQLR1_4_P" 189 +LOCATE COMP "DQLR1_0" SITE "AD31"; #was "DQLR1_0_P" 169 +LOCATE COMP "DQLR1_1" SITE "AB32"; #was "DQLR1_1_P" 173 +LOCATE COMP "DQLR1_2" SITE "AE34"; #was "DQLR1_2_P" 177 +LOCATE COMP "DQSLR1" SITE "AB26"; #was "DQSLR1_T" 181 +LOCATE COMP "DQLR1_3" SITE "AD33"; #was "DQLR1_3_P" 185 +LOCATE COMP "DQLR1_4" SITE "AF34"; #was "DQLR1_4_P" 189 LOCATE COMP "DQLL3_0" SITE "AE4"; #was "DQLL3_0_P" 2 -LOCATE COMP "DQLL3_1" SITE "AB10" #was "DQLL3_1_P" 6 +LOCATE COMP "DQLL3_1" SITE "AB10"; #was "DQLL3_1_P" 6 LOCATE COMP "DQLL3_2" SITE "AE2"; #was "DQLL3_2_P" 10 LOCATE COMP "DQSLL3" SITE "AJ1"; #was "DQSLL3_T" 14 LOCATE COMP "DQLL3_3" SITE "AD4"; #was "DQLL3_3_P" 18 @@ -353,21 +378,21 @@ IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 ; ################################################################# # Many LED ################################################################# -LOCATE COMP "LED_CLOCK_GREEN" SITE "C25"; -LOCATE COMP "LED_CLOCK_RED" SITE "D25"; +LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; +LOCATE COMP "LED_RJ_RED_0" SITE "D25"; LOCATE COMP "LED_GREEN" SITE "D24"; LOCATE COMP "LED_ORANGE" SITE "E24"; LOCATE COMP "LED_RED" SITE "K23"; -LOCATE COMP "LED_TRIGGER_GREEN" SITE "G26"; -LOCATE COMP "LED_TRIGGER_RED" SITE "G25"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; +LOCATE COMP "LED_RJ_RED_1" SITE "G25"; LOCATE COMP "LED_YELLOW" SITE "K24"; -IOBUF PORT "LED_CLOCK_GREEN" IO_TYPE=LVCMOS25 ; -IOBUF PORT "LED_CLOCK_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ; IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ; IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ; IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ; -IOBUF PORT "LED_TRIGGER_GREEN" IO_TYPE=LVCMOS25 ; -IOBUF PORT "LED_TRIGGER_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ; IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ; LOCATE COMP "LED_SFP_GREEN_0" SITE "B4"; @@ -424,7 +449,7 @@ LOCATE COMP "PCSSW_4" SITE "G13"; LOCATE COMP "PCSSW_5" SITE "H14"; LOCATE COMP "PCSSW_6" SITE "A13"; LOCATE COMP "PCSSW_7" SITE "B13"; -DEFINE PORT GROUP "PCSSW" "PCSSW*" ; +DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ; IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; @@ -450,8 +475,8 @@ LOCATE COMP "RJ_IO_4" SITE "R34"; #LOCATE COMP "RJ_IO_2_N" SITE "R30"; #LOCATE COMP "RJ_IO_3_N" SITE "R25"; #LOCATE COMP "RJ_IO_4_N" SITE "R33"; -IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; -IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25 ; IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; IOBUF PORT "RJ_IO_4" IO_TYPE=LVDS25E ; @@ -479,7 +504,7 @@ IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; -IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; ################################################################# diff --git a/pinout/trb3sc_basic.vhd b/pinout/trb3sc_basic.vhd deleted file mode 100644 index 938b304..0000000 --- a/pinout/trb3sc_basic.vhd +++ /dev/null @@ -1,128 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; - - - -entity trb3sc is - port( - CLK_SUPPL_PCLK : in std_logic; - CLK_SUPPL_PLL_LEFT : in std_logic; - CLK_SUPPL_PLL_RIGHT : in std_logic; - CLK_CORE_PCLK : in std_logic; - CLK_CORE_PLL_LEFT : in std_logic; - CLK_CORE_PLL_RIGHT : in std_logic; - CLK_EXT_PCLK : in std_logic; - CLK_EXT_PLL_LEFT : in std_logic; - CLK_EXT_PLL_RIGHT : in std_logic; - - TRIG_PLL : in std_logic; - TRIG_LEFT : in std_logic; - TRIG_RIGHT : in std_logic; - - --Backplane - BACK_GPIO : inout std_logic_vector(15 downto 0); - BACK_LVDS : inout std_logic_vector( 1 downto 0); - BACK_3V3 : inout std_logic_vector( 3 downto 0); - - --AddOn Connector - --to be added - - --KEL Connector - KEL : inout std_logic_vector(40 downto 1); - - --Additional IO - HDR_IO : inout std_logic_vector( 9 downto 0); - RJ_IO : inout std_logic_vector( 3 downto 0); - SPARE_IN : in std_logic_vector( 1 downto 0); - - --LED - LED_CLOCK_GREEN : out std_logic; - LED_CLOCK_RED : out std_logic; - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_RJIO_GREEN : out std_logic; - LED_RJIO_RED : out std_logic; - LED_YELLOW : out std_logic; - LED_WHITE : out std_logic_vector( 1 downto 0); - LED_SFP_GREEN : out std_logic_vector( 1 downto 0); - LED_SFP_RED : out std_logic_vector( 1 downto 0); - - --SFP - SFP_LOS : in std_logic_vector( 1 downto 0); - SFP_MOD0 : in std_logic_vector( 1 downto 0); - SFP_MOD1 : inout std_logic_vector( 1 downto 0); - SFP_MOD2 : inout std_logic_vector( 1 downto 0); - SFP_TX_DIS : out std_logic_vector( 1 downto 0); - --Serdes switch - PCSSW_ENSMB : out std_logic; - PCSSW_EQ : out std_logic_vector( 3 downto 0); - PCSSW_PE : out std_logic_vector( 3 downto 0); - PCSSW : out std_logic_vector( 7 downto 0); - - --ADC - ADC_CLK : out std_logic; - ADC_CS : out std_logic; - ADC_DIN : out std_logic; - ADC_DOUT : in std_logic; - - --Flash, 1-wire, Reload - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_IN : out std_logic; - FLASH_OUT : in std_logic; - PROGRAMN : out std_logic; - ENPIRION_CLOCK : out std_logic; - TEMPSENS : inout std_logic; - - --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) - ); - - - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_CLOCK_GREEN : signal is false; - attribute syn_useioff of LED_CLOCK_RED : signal is false; - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_RJIO_GREEN : signal is false; - attribute syn_useioff of LED_RJIO_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of LED_WHITE : signal is false; - attribute syn_useioff of LED_SFP_GREEN : signal is false; - attribute syn_useioff of LED_SFP_RED : signal is false; - - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - attribute syn_useioff of TRIG_LEFT : signal is false; - attribute syn_useioff of TRIG_RIGHT : signal is false; - - attribute syn_useioff of SFP_LOS : signal is false; - attribute syn_useioff of SFP_MOD0 : signal is false; - attribute syn_useioff of SFP_MOD1 : signal is false; - attribute syn_useioff of SFP_MOD2 : signal is false; - attribute syn_useioff of SFP_TX_DIS : signal is false; - - --important signals _with_ IO-FF - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - - -end entity; - -architecture trb3sc_arch of trb3sc_arch is - - - -end architecture; diff --git a/pinout/trb3scraw.lpf b/pinout/trb3scraw.lpf new file mode 100644 index 0000000..779eb93 --- /dev/null +++ b/pinout/trb3scraw.lpf @@ -0,0 +1,528 @@ + +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +LOCATE COMP "2V_IO_PCSA" SITE "AF18"; +LOCATE COMP "2V_IO_PCSA" SITE "AF19"; +LOCATE COMP "2V_IO_PCSA" SITE "AF20"; +LOCATE COMP "2V_IO_PCSA" SITE "AF21"; +LOCATE COMP "2V_IO_PCSA" SITE "AG18"; +LOCATE COMP "2V_IO_PCSA" SITE "AG19"; +LOCATE COMP "2V_IO_PCSA" SITE "AG20"; +LOCATE COMP "2V_IO_PCSA" SITE "AG21"; +LOCATE COMP "2V_IO_PCSB" SITE "AF14"; +LOCATE COMP "2V_IO_PCSB" SITE "AF15"; +LOCATE COMP "2V_IO_PCSB" SITE "AF16"; +LOCATE COMP "2V_IO_PCSB" SITE "AF17"; +LOCATE COMP "2V_IO_PCSB" SITE "AG14"; +LOCATE COMP "2V_IO_PCSB" SITE "AG15"; +LOCATE COMP "2V_IO_PCSB" SITE "AG16"; +LOCATE COMP "2V_IO_PCSB" SITE "AG17"; +LOCATE COMP "2V_IO_PCSC" SITE "AE20"; +LOCATE COMP "2V_IO_PCSC" SITE "AE21"; +LOCATE COMP "2V_IO_PCSC" SITE "AF22"; +LOCATE COMP "2V_IO_PCSC" SITE "AF23"; +LOCATE COMP "2V_IO_PCSC" SITE "AF24"; +LOCATE COMP "2V_IO_PCSC" SITE "AG22"; +LOCATE COMP "2V_IO_PCSC" SITE "AG23"; +LOCATE COMP "2V_IO_PCSC" SITE "AG24"; +LOCATE COMP "2V_IO_PCSD" SITE "AE14"; +LOCATE COMP "2V_IO_PCSD" SITE "AE15"; +LOCATE COMP "2V_IO_PCSD" SITE "AF11"; +LOCATE COMP "2V_IO_PCSD" SITE "AF12"; +LOCATE COMP "2V_IO_PCSD" SITE "AF13"; +LOCATE COMP "2V_IO_PCSD" SITE "AG11"; +LOCATE COMP "2V_IO_PCSD" SITE "AG12"; +LOCATE COMP "2V_IO_PCSD" SITE "AG13"; +LOCATE COMP "BACK_GPIO_0" SITE "C26"; +LOCATE COMP "BACK_GPIO_1" SITE "D26"; +LOCATE COMP "BACK_GPIO_10" SITE "A29"; +LOCATE COMP "BACK_GPIO_11" SITE "A30"; +LOCATE COMP "BACK_GPIO_12" SITE "H26"; +LOCATE COMP "BACK_GPIO_13" SITE "H25"; +LOCATE COMP "BACK_GPIO_14" SITE "A31"; +LOCATE COMP "BACK_GPIO_15" SITE "B31"; +LOCATE COMP "BACK_GPIO_2" SITE "B27"; +LOCATE COMP "BACK_GPIO_3" SITE "C27"; +LOCATE COMP "BACK_GPIO_4" SITE "D27"; +LOCATE COMP "BACK_GPIO_5" SITE "E27"; +LOCATE COMP "BACK_GPIO_6" SITE "B28"; +LOCATE COMP "BACK_GPIO_7" SITE "A28"; +LOCATE COMP "BACK_GPIO_8" SITE "A26"; +LOCATE COMP "BACK_GPIO_9" SITE "A27"; +LOCATE COMP "BACK_LVDS0_N" SITE "V1"; +LOCATE COMP "BACK_LVDS0_P" SITE "V2"; +LOCATE COMP "BACK_LVDS1_N" SITE "T3"; +LOCATE COMP "BACK_LVDS1_P" SITE "T4"; +LOCATE COMP "CCLK" SITE "C34"; +LOCATE COMP "CFG0" SITE "B33"; +LOCATE COMP "CFG1" SITE "F30"; +LOCATE COMP "CFG2" SITE "D32"; +LOCATE COMP "CORE_CLOCK0_N" SITE "U8"; +LOCATE COMP "CORE_CLOCK0_P" SITE "U9"; +LOCATE COMP "CORE_CLOCK1_N" SITE "U7"; +LOCATE COMP "CORE_CLOCK1_P" SITE "U6"; +LOCATE COMP "CORE_CLOCK2_N" SITE "V33"; +LOCATE COMP "CORE_CLOCK2_P" SITE "V34"; +LOCATE COMP "DONE" SITE "G31"; +LOCATE COMP "DQLL0_0_N" SITE "AA1"; +LOCATE COMP "DQLL0_0_P" SITE "AA2"; +LOCATE COMP "DQLL0_1_N" SITE "AB1"; +LOCATE COMP "DQLL0_1_P" SITE "AB2"; +LOCATE COMP "DQLL0_2_N" SITE "AA3"; +LOCATE COMP "DQLL0_2_P" SITE "AA4"; +LOCATE COMP "DQLL0_3_N" SITE "AB5"; +LOCATE COMP "DQLL0_3_P" SITE "AA5"; +LOCATE COMP "DQLL0_4_N" SITE "AA7"; +LOCATE COMP "DQLL0_4_P" SITE "Y7"; +LOCATE COMP "DQLL1_0_N" SITE "Y1"; +LOCATE COMP "DQLL1_0_P" SITE "Y2"; +LOCATE COMP "DQLL1_1_N" SITE "W3"; +LOCATE COMP "DQLL1_1_P" SITE "W4"; +LOCATE COMP "DQLL1_2_N" SITE "W1"; +LOCATE COMP "DQLL1_2_P" SITE "W2"; +LOCATE COMP "DQLL1_3_N" SITE "W9"; +LOCATE COMP "DQLL1_3_P" SITE "W8"; +LOCATE COMP "DQLL1_4_N" SITE "AA8"; +LOCATE COMP "DQLL1_4_P" SITE "Y8"; +LOCATE COMP "DQLL2_0_N" SITE "AC4"; +LOCATE COMP "DQLL2_0_P" SITE "AC5"; +LOCATE COMP "DQLL2_1_N" SITE "AC1"; +LOCATE COMP "DQLL2_1_P" SITE "AC2"; +LOCATE COMP "DQLL2_2_N" SITE "AB3"; +LOCATE COMP "DQLL2_2_P" SITE "AB4"; +LOCATE COMP "DQLL2_3_N" SITE "AB8"; +LOCATE COMP "DQLL2_3_P" SITE "AA9"; +LOCATE COMP "DQLL2_4_N" SITE "AB6"; +LOCATE COMP "DQLL2_4_P" SITE "AB7"; +LOCATE COMP "DQLL3_0_N" SITE "AE3"; +LOCATE COMP "DQLL3_0_P" SITE "AE4"; +LOCATE COMP "DQLL3_1_N" SITE "AC10"; +LOCATE COMP "DQLL3_1_P" SITE "AB10"; +LOCATE COMP "DQLL3_2_N" SITE "AE1"; +LOCATE COMP "DQLL3_2_P" SITE "AE2"; +LOCATE COMP "DQLL3_3_N" SITE "AD3"; +LOCATE COMP "DQLL3_3_P" SITE "AD4"; +LOCATE COMP "DQLL3_4_N" SITE "AC8"; +LOCATE COMP "DQLL3_4_P" SITE "AC9"; +LOCATE COMP "DQLR0_0_N" SITE "AB33"; +LOCATE COMP "DQLR0_0_P" SITE "AB34"; +LOCATE COMP "DQLR0_1_N" SITE "AA26"; +LOCATE COMP "DQLR0_1_P" SITE "AA25"; +LOCATE COMP "DQLR0_2_N" SITE "AC33"; +LOCATE COMP "DQLR0_2_P" SITE "AC34"; +LOCATE COMP "DQLR0_3_N" SITE "AA30"; +LOCATE COMP "DQLR0_3_P" SITE "AA31"; +LOCATE COMP "DQLR0_4_N" SITE "AA27"; +LOCATE COMP "DQLR0_4_P" SITE "AA28"; +LOCATE COMP "DQLR1_0_N" SITE "AD30"; +LOCATE COMP "DQLR1_0_P" SITE "AD31"; +LOCATE COMP "DQLR1_1_N" SITE "AB31"; +LOCATE COMP "DQLR1_1_P" SITE "AB32"; +LOCATE COMP "DQLR1_2_N" SITE "AE33"; +LOCATE COMP "DQLR1_2_P" SITE "AE34"; +LOCATE COMP "DQLR1_3_N" SITE "AD34"; +LOCATE COMP "DQLR1_3_P" SITE "AD33"; +LOCATE COMP "DQLR1_4_N" SITE "AG34"; +LOCATE COMP "DQLR1_4_P" SITE "AF34"; +LOCATE COMP "DQLR2_0_N" SITE "W29"; +LOCATE COMP "DQLR2_0_P" SITE "W30"; +LOCATE COMP "DQLR2_1_N" SITE "W26"; +LOCATE COMP "DQLR2_1_P" SITE "W27"; +LOCATE COMP "DQLR2_2_N" SITE "W33"; +LOCATE COMP "DQLR2_2_P" SITE "W34"; +LOCATE COMP "DQLR2_3_N" SITE "Y33"; +LOCATE COMP "DQLR2_3_P" SITE "Y34"; +LOCATE COMP "DQLR2_4_N" SITE "Y25"; +LOCATE COMP "DQLR2_4_P" SITE "Y26"; +LOCATE COMP "DQSLL0_C" SITE "AB9"; +LOCATE COMP "DQSLL0_T" SITE "AA10"; +LOCATE COMP "DQSLL1_C" SITE "Y6"; +LOCATE COMP "DQSLL1_T" SITE "W6"; +LOCATE COMP "DQSLL2_C" SITE "AE5"; +LOCATE COMP "DQSLL2_T" SITE "AD5"; +LOCATE COMP "DQSLL3_C" SITE "AK1"; +LOCATE COMP "DQSLL3_T" SITE "AJ1"; +LOCATE COMP "DQSLR0_C" SITE "AC30"; +LOCATE COMP "DQSLR0_T" SITE "AB30"; +LOCATE COMP "DQSLR1_C" SITE "AB25"; +LOCATE COMP "DQSLR1_T" SITE "AB26"; +LOCATE COMP "DQSLR2_C" SITE "AA29"; +LOCATE COMP "DQSLR2_T" SITE "Y30"; +LOCATE COMP "DQSUL0_C" SITE "M9"; +LOCATE COMP "DQSUL0_T" SITE "N9"; +LOCATE COMP "DQSUL1_C" SITE "L9"; +LOCATE COMP "DQSUL1_T" SITE "L10"; +LOCATE COMP "DQSUL2_C" SITE "H3"; +LOCATE COMP "DQSUL2_T" SITE "G3"; +LOCATE COMP "DQSUL3_C" SITE "N10"; +LOCATE COMP "DQSUL3_T" SITE "M10"; +LOCATE COMP "DQSUR0_C" SITE "M27"; +LOCATE COMP "DQSUR0_T" SITE "M26"; +LOCATE COMP "DQSUR1_C" SITE "N28"; +LOCATE COMP "DQSUR1_T" SITE "N27"; +LOCATE COMP "DQSUR2_C" SITE "U30"; +LOCATE COMP "DQSUR2_T" SITE "T30"; +LOCATE COMP "DQUL0_0_N" SITE "L4"; +LOCATE COMP "DQUL0_0_P" SITE "L5"; +LOCATE COMP "DQUL0_1_N" SITE "M3"; +LOCATE COMP "DQUL0_1_P" SITE "M4"; +LOCATE COMP "DQUL0_2_N" SITE "K5"; +LOCATE COMP "DQUL0_2_P" SITE "K6"; +LOCATE COMP "DQUL0_3_N" SITE "M1"; +LOCATE COMP "DQUL0_3_P" SITE "M2"; +LOCATE COMP "DQUL0_4_N" SITE "L6"; +LOCATE COMP "DQUL0_4_P" SITE "M7"; +LOCATE COMP "DQUL1_0_N" SITE "L1"; +LOCATE COMP "DQUL1_0_P" SITE "L2"; +LOCATE COMP "DQUL1_1_N" SITE "K1"; +LOCATE COMP "DQUL1_1_P" SITE "K2"; +LOCATE COMP "DQUL1_2_N" SITE "K3"; +LOCATE COMP "DQUL1_2_P" SITE "K4"; +LOCATE COMP "DQUL1_3_N" SITE "L7"; +LOCATE COMP "DQUL1_3_P" SITE "M8"; +LOCATE COMP "DQUL1_4_N" SITE "J6"; +LOCATE COMP "DQUL1_4_P" SITE "K7"; +LOCATE COMP "DQUL2_0_N" SITE "F1"; +LOCATE COMP "DQUL2_0_P" SITE "F2"; +LOCATE COMP "DQUL2_1_N" SITE "E3"; +LOCATE COMP "DQUL2_1_P" SITE "F3"; +LOCATE COMP "DQUL2_2_N" SITE "G1"; +LOCATE COMP "DQUL2_2_P" SITE "G2"; +LOCATE COMP "DQUL2_3_N" SITE "J1"; +LOCATE COMP "DQUL2_3_P" SITE "H1"; +LOCATE COMP "DQUL2_4_N" SITE "H2"; +LOCATE COMP "DQUL2_4_P" SITE "J3"; +LOCATE COMP "DQUL3_0_N" SITE "N3"; +LOCATE COMP "DQUL3_0_P" SITE "N4"; +LOCATE COMP "DQUL3_1_N" SITE "N1"; +LOCATE COMP "DQUL3_1_P" SITE "N2"; +LOCATE COMP "DQUL3_2_N" SITE "N5"; +LOCATE COMP "DQUL3_2_P" SITE "M5"; +LOCATE COMP "DQUL3_3_N" SITE "P4"; +LOCATE COMP "DQUL3_3_P" SITE "P5"; +LOCATE COMP "DQUL3_4_N" SITE "P8"; +LOCATE COMP "DQUL3_4_P" SITE "N8"; +LOCATE COMP "DQUR0_0_N" SITE "M25"; +LOCATE COMP "DQUR0_0_P" SITE "L26"; +LOCATE COMP "DQUR0_1_N" SITE "L31"; +LOCATE COMP "DQUR0_1_P" SITE "L32"; +LOCATE COMP "DQUR0_2_N" SITE "L33"; +LOCATE COMP "DQUR0_2_P" SITE "L34"; +LOCATE COMP "DQUR0_3_N" SITE "K30"; +LOCATE COMP "DQUR0_3_P" SITE "K29"; +LOCATE COMP "DQUR0_4_N" SITE "K33"; +LOCATE COMP "DQUR0_4_P" SITE "K34"; +LOCATE COMP "DQUR1_0_N" SITE "N29"; +LOCATE COMP "DQUR1_0_P" SITE "N30"; +LOCATE COMP "DQUR1_1_N" SITE "P26"; +LOCATE COMP "DQUR1_1_P" SITE "N26"; +LOCATE COMP "DQUR1_2_N" SITE "N31"; +LOCATE COMP "DQUR1_2_P" SITE "N32"; +LOCATE COMP "DQUR1_3_N" SITE "N33"; +LOCATE COMP "DQUR1_3_P" SITE "N34"; +LOCATE COMP "DQUR1_4_N" SITE "P27"; +LOCATE COMP "DQUR1_4_P" SITE "P28"; +LOCATE COMP "DQUR2_0_N" SITE "T31"; +LOCATE COMP "DQUR2_0_P" SITE "T32"; +LOCATE COMP "DQUR2_1_N" SITE "T27"; +LOCATE COMP "DQUR2_1_P" SITE "T26"; +LOCATE COMP "DQUR2_2_N" SITE "U31"; +LOCATE COMP "DQUR2_2_P" SITE "U32"; +LOCATE COMP "DQUR2_3_N" SITE "T33"; +LOCATE COMP "DQUR2_3_P" SITE "T34"; +LOCATE COMP "DQUR2_4_N" SITE "U27"; +LOCATE COMP "DQUR2_4_P" SITE "U26"; +LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; +LOCATE COMP "EXT_CLOCK0_N" SITE "V28"; +LOCATE COMP "EXT_CLOCK0_P" SITE "U28"; +LOCATE COMP "EXT_CLOCK1_N" SITE "R29"; +LOCATE COMP "EXT_CLOCK1_P" SITE "P30"; +LOCATE COMP "EXT_CLOCK2_N" SITE "N6"; +LOCATE COMP "EXT_CLOCK2_P" SITE "N7"; +LOCATE COMP "EXT_TRIG0_N" SITE "AK34"; +LOCATE COMP "EXT_TRIG0_P" SITE "AJ34"; +LOCATE COMP "EXT_TRIG1_N" SITE "P33"; +LOCATE COMP "EXT_TRIG1_P" SITE "P34"; +LOCATE COMP "EXT_TRIG2_N" SITE "T5"; +LOCATE COMP "EXT_TRIG2_P" SITE "T6"; +LOCATE COMP "HDR_IO_0_N" SITE "AN28"; +LOCATE COMP "HDR_IO_0_P" SITE "AP28"; +LOCATE COMP "HDR_IO_1_N" SITE "AN27"; +LOCATE COMP "HDR_IO_1_P" SITE "AP27"; +LOCATE COMP "HDR_IO_2_N" SITE "AL27"; +LOCATE COMP "HDR_IO_2_P" SITE "AM27"; +LOCATE COMP "HDR_IO_3_N" SITE "AG26"; +LOCATE COMP "HDR_IO_3_P" SITE "AH26"; +LOCATE COMP "HDR_IO_4_N" SITE "AL28"; +LOCATE COMP "HDR_IO_4_P" SITE "AM28"; +LOCATE COMP "INITN" SITE "C33"; +LOCATE COMP "JTAG_TCK" SITE "D1"; +LOCATE COMP "JTAG_TDI" SITE "E1"; +LOCATE COMP "JTAG_TDO" SITE "C1"; +LOCATE COMP "JTAG_TMS" SITE "D2"; +LOCATE COMP "KEL10_N" SITE "AK3"; +LOCATE COMP "KEL10_P" SITE "AL3"; +LOCATE COMP "KEL11_N" SITE "AD8"; +LOCATE COMP "KEL11_P" SITE "AD9"; +LOCATE COMP "KEL12_N" SITE "AK4"; +LOCATE COMP "KEL12_P" SITE "AJ4"; +LOCATE COMP "KEL13_N" SITE "V3"; +LOCATE COMP "KEL13_P" SITE "V4"; +LOCATE COMP "KEL14_N" SITE "W5"; +LOCATE COMP "KEL14_P" SITE "V5"; +LOCATE COMP "KEL15_N" SITE "T8"; +LOCATE COMP "KEL15_P" SITE "T9"; +LOCATE COMP "KEL16_N" SITE "T1"; +LOCATE COMP "KEL16_P" SITE "T2"; +LOCATE COMP "KEL17_N" SITE "P6"; +LOCATE COMP "KEL17_P" SITE "P7"; +LOCATE COMP "KEL18_N" SITE "T7"; +LOCATE COMP "KEL18_P" SITE "R8"; +LOCATE COMP "KEL19_N" SITE "R1"; +LOCATE COMP "KEL19_P" SITE "R2"; +LOCATE COMP "KEL1_N" SITE "AP6"; +LOCATE COMP "KEL1_P" SITE "AP5"; +LOCATE COMP "KEL20_N" SITE "P10"; +LOCATE COMP "KEL20_P" SITE "P9"; +LOCATE COMP "KEL21_N" SITE "AP30"; +LOCATE COMP "KEL21_P" SITE "AP29"; +LOCATE COMP "KEL22_N" SITE "AP32"; +LOCATE COMP "KEL22_P" SITE "AP33"; +LOCATE COMP "KEL23_N" SITE "AN33"; +LOCATE COMP "KEL23_P" SITE "AN34"; +LOCATE COMP "KEL24_N" SITE "AN31"; +LOCATE COMP "KEL24_P" SITE "AP31"; +LOCATE COMP "KEL25_N" SITE "AM32"; +LOCATE COMP "KEL25_P" SITE "AN32"; +LOCATE COMP "KEL26_N" SITE "AN29"; +LOCATE COMP "KEL26_P" SITE "AM29"; +LOCATE COMP "KEL27_N" SITE "AM31"; +LOCATE COMP "KEL27_P" SITE "AL31"; +LOCATE COMP "KEL28_N" SITE "AM30"; +LOCATE COMP "KEL28_P" SITE "AL30"; +LOCATE COMP "KEL29_N" SITE "AL33"; +LOCATE COMP "KEL29_P" SITE "AL34"; +LOCATE COMP "KEL2_N" SITE "AP3"; +LOCATE COMP "KEL2_P" SITE "AP2"; +LOCATE COMP "KEL30_N" SITE "AK31"; +LOCATE COMP "KEL30_P" SITE "AJ31"; +LOCATE COMP "KEL31_N" SITE "AJ33"; +LOCATE COMP "KEL31_P" SITE "AH33"; +LOCATE COMP "KEL32_N" SITE "AK32"; +LOCATE COMP "KEL32_P" SITE "AL32"; +LOCATE COMP "KEL33_N" SITE "AF31"; +LOCATE COMP "KEL33_P" SITE "AF32"; +LOCATE COMP "KEL34_N" SITE "AE31"; +LOCATE COMP "KEL34_P" SITE "AE32"; +LOCATE COMP "KEL35_N" SITE "AE29"; +LOCATE COMP "KEL35_P" SITE "AE30"; +LOCATE COMP "KEL36_N" SITE "AD25"; +LOCATE COMP "KEL36_P" SITE "AD26"; +LOCATE COMP "KEL37_N" SITE "L30"; +LOCATE COMP "KEL37_P" SITE "M29"; +LOCATE COMP "KEL38_N" SITE "AB27"; +LOCATE COMP "KEL38_P" SITE "AC28"; +LOCATE COMP "KEL39_N" SITE "M33"; +LOCATE COMP "KEL39_P" SITE "M34"; +LOCATE COMP "KEL3_N" SITE "AN2"; +LOCATE COMP "KEL3_P" SITE "AN1"; +LOCATE COMP "KEL40_N" SITE "M28"; +LOCATE COMP "KEL40_P" SITE "L28"; +LOCATE COMP "KEL4_N" SITE "AM3"; +LOCATE COMP "KEL4_P" SITE "AN3"; +LOCATE COMP "KEL5_N" SITE "AM5"; +LOCATE COMP "KEL5_P" SITE "AL5"; +LOCATE COMP "KEL6_N" SITE "AN6"; +LOCATE COMP "KEL6_P" SITE "AM6"; +LOCATE COMP "KEL7_N" SITE "AM4"; +LOCATE COMP "KEL7_P" SITE "AL4"; +LOCATE COMP "KEL8_N" SITE "AJ6"; +LOCATE COMP "KEL8_P" SITE "AJ5"; +LOCATE COMP "KEL9_N" SITE "AJ3"; +LOCATE COMP "KEL9_P" SITE "AJ2"; +LOCATE COMP "LED_CLOCK_GREEN" SITE "C25"; +LOCATE COMP "LED_CLOCK_RED" SITE "D25"; +LOCATE COMP "LED_GREEN" SITE "D24"; +LOCATE COMP "LED_ORANGE" SITE "E24"; +LOCATE COMP "LED_RED" SITE "K23"; +LOCATE COMP "LED_TRIGGER_GREEN" SITE "G26"; +LOCATE COMP "LED_TRIGGER_RED" SITE "G25"; +LOCATE COMP "LED_WHITE1" SITE "A32"; +LOCATE COMP "LED_WHITE2" SITE "A33"; +LOCATE COMP "LED_YELLOW" SITE "K24"; +LOCATE COMP "N274462516" SITE "AH20"; +LOCATE COMP "N274462534" SITE "AH16"; +LOCATE COMP "N274474116" SITE "AH23"; +LOCATE COMP "N3196153" SITE "E32"; +LOCATE COMP "N3197996" SITE "W23"; +LOCATE COMP "N3531518" SITE "AH12"; +LOCATE COMP "N3531520" SITE "AH13"; +LOCATE COMP "N3536039" SITE "V29"; +LOCATE COMP "N3536145" SITE "W28"; +LOCATE COMP "N3537093" SITE "V7"; +LOCATE COMP "N3537111" SITE "W7"; +LOCATE COMP "N3565399" SITE "A14"; +LOCATE COMP "N3565411" SITE "B14"; +LOCATE COMP "N3565423" SITE "G16"; +LOCATE COMP "N3565435" SITE "G17"; +LOCATE COMP "N3672771" SITE "T10"; +LOCATE COMP "N3672771" SITE "T11"; +LOCATE COMP "N3672771" SITE "T24"; +LOCATE COMP "N3672771" SITE "T25"; +LOCATE COMP "N3672771" SITE "W10"; +LOCATE COMP "N3672771" SITE "W11"; +LOCATE COMP "N3672771" SITE "W24"; +LOCATE COMP "N3672771" SITE "W25"; +LOCATE COMP "N3713842" SITE "AH15"; +LOCATE COMP "N3713846" SITE "AH19"; +LOCATE COMP "N3713850" SITE "AH22"; +LOCATE COMP "N4076646" SITE "R9"; +LOCATE COMP "N4076650" SITE "R10"; +LOCATE COMP "N4076829" SITE "T29"; +LOCATE COMP "N4076833" SITE "T28"; +LOCATE COMP "PCSA_IN0_N" SITE "AK21"; +LOCATE COMP "PCSA_IN0_P" SITE "AL21"; +LOCATE COMP "PCSA_IN1_N" SITE "AK20"; +LOCATE COMP "PCSA_IN1_P" SITE "AL20"; +LOCATE COMP "PCSA_IN2_N" SITE "AK19"; +LOCATE COMP "PCSA_IN2_P" SITE "AL19"; +LOCATE COMP "PCSA_IN3_N" SITE "AK18"; +LOCATE COMP "PCSA_IN3_P" SITE "AL18"; +LOCATE COMP "PCSA_OUT0_N" SITE "AN21"; +LOCATE COMP "PCSA_OUT0_P" SITE "AP21"; +LOCATE COMP "PCSA_OUT1_N" SITE "AN20"; +LOCATE COMP "PCSA_OUT1_P" SITE "AP20"; +LOCATE COMP "PCSA_OUT2_N" SITE "AN19"; +LOCATE COMP "PCSA_OUT2_P" SITE "AP19"; +LOCATE COMP "PCSA_OUT3_N" SITE "AN18"; +LOCATE COMP "PCSA_OUT3_P" SITE "AP18"; +LOCATE COMP "PCSB_IN0_N" SITE "AK17"; +LOCATE COMP "PCSB_IN0_P" SITE "AL17"; +LOCATE COMP "PCSB_IN1_N" SITE "AK16"; +LOCATE COMP "PCSB_IN1_P" SITE "AL16"; +LOCATE COMP "PCSB_IN2_N" SITE "AK15"; +LOCATE COMP "PCSB_IN2_P" SITE "AL15"; +LOCATE COMP "PCSB_IN3_SWITCH_N" SITE "AK14"; +LOCATE COMP "PCSB_IN3_SWITCH_P" SITE "AL14"; +LOCATE COMP "PCSB_OUT0_N" SITE "AN17"; +LOCATE COMP "PCSB_OUT0_P" SITE "AP17"; +LOCATE COMP "PCSB_OUT1_N" SITE "AN16"; +LOCATE COMP "PCSB_OUT1_P" SITE "AP16"; +LOCATE COMP "PCSB_OUT2_N" SITE "AN15"; +LOCATE COMP "PCSB_OUT2_P" SITE "AP15"; +LOCATE COMP "PCSB_OUT3_SWITCH_N" SITE "AN14"; +LOCATE COMP "PCSB_OUT3_SWITCH_P" SITE "AP14"; +LOCATE COMP "PCSC_IN0_N" SITE "AK25"; +LOCATE COMP "PCSC_IN0_P" SITE "AL25"; +LOCATE COMP "PCSC_IN1_N" SITE "AK24"; +LOCATE COMP "PCSC_IN1_P" SITE "AL24"; +LOCATE COMP "PCSC_IN2_N" SITE "AK23"; +LOCATE COMP "PCSC_IN2_P" SITE "AL23"; +LOCATE COMP "PCSC_IN3_N" SITE "AK22"; +LOCATE COMP "PCSC_IN3_P" SITE "AL22"; +LOCATE COMP "PCSC_OUT0_N" SITE "AN25"; +LOCATE COMP "PCSC_OUT0_P" SITE "AP25"; +LOCATE COMP "PCSC_OUT1_N" SITE "AN24"; +LOCATE COMP "PCSC_OUT1_P" SITE "AP24"; +LOCATE COMP "PCSC_OUT2_N" SITE "AN23"; +LOCATE COMP "PCSC_OUT2_P" SITE "AP23"; +LOCATE COMP "PCSC_OUT3_N" SITE "AN22"; +LOCATE COMP "PCSC_OUT3_P" SITE "AP22"; +LOCATE COMP "PCSD_IN0_N" SITE "AK13"; +LOCATE COMP "PCSD_IN0_P" SITE "AL13"; +LOCATE COMP "PCSD_IN1_SWITCH_N" SITE "AK12"; +LOCATE COMP "PCSD_IN1_SWITCH_P" SITE "AL12"; +LOCATE COMP "PCSD_IN2_N" SITE "AK11"; +LOCATE COMP "PCSD_IN2_P" SITE "AL11"; +LOCATE COMP "PCSD_IN3_N" SITE "AK10"; +LOCATE COMP "PCSD_IN3_P" SITE "AL10"; +LOCATE COMP "PCSD_LED_GREEN0" SITE "B4"; +LOCATE COMP "PCSD_LED_GREEN1" SITE "A6"; +LOCATE COMP "PCSD_LED_RED0" SITE "A3"; +LOCATE COMP "PCSD_LED_RED1" SITE "A8"; +LOCATE COMP "PCSD_LOS0" SITE "B6"; +LOCATE COMP "PCSD_LOS1" SITE "C9"; +LOCATE COMP "PCSD_MOD0_0" SITE "A5"; +LOCATE COMP "PCSD_MOD0_1" SITE "K11"; +LOCATE COMP "PCSD_MOD1_0" SITE "B7"; +LOCATE COMP "PCSD_MOD1_1" SITE "J11"; +LOCATE COMP "PCSD_MOD2_0" SITE "A7"; +LOCATE COMP "PCSD_MOD2_1" SITE "D9"; +LOCATE COMP "PCSD_OUT0_N" SITE "AN13"; +LOCATE COMP "PCSD_OUT0_P" SITE "AP13"; +LOCATE COMP "PCSD_OUT1_SWITCH_N" SITE "AN12"; +LOCATE COMP "PCSD_OUT1_SWITCH_P" SITE "AP12"; +LOCATE COMP "PCSD_OUT2_N" SITE "AN11"; +LOCATE COMP "PCSD_OUT2_P" SITE "AP11"; +LOCATE COMP "PCSD_OUT3_N" SITE "AP10"; +LOCATE COMP "PCSD_OUT3_P" SITE "AN10"; +LOCATE COMP "PCSD_RATE_SEL0" SITE "A4"; +LOCATE COMP "PCSD_RATE_SEL1" SITE "C8"; +LOCATE COMP "PCSD_TX_DIS0" SITE "D6"; +LOCATE COMP "PCSD_TX_DIS1" SITE "A9"; +LOCATE COMP "PCSD_TX_FAULT0" SITE "C5"; +LOCATE COMP "PCSD_TX_FAULT1" SITE "B8"; +LOCATE COMP "PCSSW_ENSMB" SITE "B3"; +LOCATE COMP "PCSSW_EQ0" SITE "B1"; +LOCATE COMP "PCSSW_EQ1" SITE "B2"; +LOCATE COMP "PCSSW_EQ2" SITE "E4"; +LOCATE COMP "PCSSW_EQ3" SITE "D4"; +LOCATE COMP "PCSSW_PE0" SITE "C3"; +LOCATE COMP "PCSSW_PE1" SITE "C4"; +LOCATE COMP "PCSSW_PE2" SITE "D3"; +LOCATE COMP "PCSSW_PE3" SITE "C2"; +LOCATE COMP "PCSSW_S10" SITE "E13"; +LOCATE COMP "PCSSW_S11" SITE "F13"; +LOCATE COMP "PCSSW_S20" SITE "G13"; +LOCATE COMP "PCSSW_S21" SITE "H14"; +LOCATE COMP "PCSSW_S30" SITE "A13"; +LOCATE COMP "PCSSW_S31" SITE "B13"; +LOCATE COMP "PCSSW_SCA" SITE "D5"; +LOCATE COMP "PCSSW_SCL" SITE "A2"; +LOCATE COMP "PROGN" SITE "B34"; +LOCATE COMP "PROGRAMN" SITE "C31"; +LOCATE COMP "RJ_IO_1_N" SITE "R27"; +LOCATE COMP "RJ_IO_1_P" SITE "R28"; +LOCATE COMP "RJ_IO_2_N" SITE "R30"; +LOCATE COMP "RJ_IO_2_P" SITE "R31"; +LOCATE COMP "RJ_IO_3_N" SITE "R25"; +LOCATE COMP "RJ_IO_3_P" SITE "R26"; +LOCATE COMP "RJ_IO_4_N" SITE "R33"; +LOCATE COMP "RJ_IO_4_P" SITE "R34"; +LOCATE COMP "SPARE_IN0_N" SITE "K32"; +LOCATE COMP "SPARE_IN0_P" SITE "K31"; +LOCATE COMP "SPARE_IN1_N" SITE "R3"; +LOCATE COMP "SPARE_IN1_P" SITE "R4"; +LOCATE COMP "SPI_CLK" SITE "F34"; +LOCATE COMP "SPI_CS" SITE "D34"; +LOCATE COMP "SPI_IN" SITE "F33"; +LOCATE COMP "SPI_OUT" SITE "F32"; +LOCATE COMP "SUPPL_CLOCK1_N" SITE "Y27"; +LOCATE COMP "SUPPL_CLOCK1_P" SITE "Y28"; +LOCATE COMP "SUPPL_CLOCK2_N" SITE "Y10"; +LOCATE COMP "SUPPL_CLOCK2_P" SITE "Y9"; +LOCATE COMP "SUPPL_CLOCK3_N" SITE "V8"; +LOCATE COMP "SUPPL_CLOCK3_P" SITE "V9"; +LOCATE COMP "TEMP_OWB" SITE "J13"; +LOCATE COMP "TEST_LINE0" SITE "A19"; +LOCATE COMP "TEST_LINE1" SITE "B19"; +LOCATE COMP "TEST_LINE10" SITE "G20"; +LOCATE COMP "TEST_LINE11" SITE "G21"; +LOCATE COMP "TEST_LINE12" SITE "C20"; +LOCATE COMP "TEST_LINE13" SITE "D20"; +LOCATE COMP "TEST_LINE14" SITE "F21"; +LOCATE COMP "TEST_LINE15" SITE "F22"; +LOCATE COMP "TEST_LINE2" SITE "K20"; +LOCATE COMP "TEST_LINE3" SITE "L19"; +LOCATE COMP "TEST_LINE4" SITE "C19"; +LOCATE COMP "TEST_LINE5" SITE "D19"; +LOCATE COMP "TEST_LINE6" SITE "J19"; +LOCATE COMP "TEST_LINE7" SITE "K19"; +LOCATE COMP "TEST_LINE8" SITE "A20"; +LOCATE COMP "TEST_LINE9" SITE "B20"; +LOCATE COMP "V3_3_GPIO_0" SITE "E11"; +LOCATE COMP "V3_3_GPIO_1" SITE "F12"; +LOCATE COMP "V3_3_GPIO_2" SITE "F10"; +LOCATE COMP "V3_3_GPIO_3" SITE "E10"; diff --git a/scripts/compile.pl b/scripts/compile.pl new file mode 100755 index 0000000..0846c0f --- /dev/null +++ b/scripts/compile.pl @@ -0,0 +1,343 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; +use Getopt::Long; +use Term::ANSIColor qw(:constants); + +my %config = do "config_compile.pl"; + + +my $TOPNAME = $config{TOPNAME}; +my $lattice_path = $config{lattice_path}; +my $synplify_path = $config{synplify_path}; +my $lm_license_file_for_synplify = $config{lm_license_file_for_synplify}; +my $lm_license_file_for_par = $config{lm_license_file_for_par}; +my $synplify_command = $config{synplify_command}; + +my $synplify_locale_workaround = "en_US\@UTF-8"; +my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed + + + + + +################################################################################### +#Settings for this project + +################################################################################### + +################################################################################### +#Options for the script +my $help = ""; +my $isMultiPar = 0; # set it to zero for single par run on the local machine +my $nrNodes = 0; # set it to one for single par run on the local machine +my $all = 1; +my $syn = 0; +my $map = 0; +my $par = 0; +my $timing = 0; +my $bitgen = 0; + +my $result = GetOptions ( + "h|help" => \$help, + "m|mpar=i" => \$nrNodes, + "a|all" => \$all, + "s|syn" => \$syn, + "mp|map" => \$map, + "p|par" => \$par, + "t|timing" => \$timing, + "b|bitgen" => \$bitgen, + ); + +if($help) { + print "Usage: compile_priph_gsi.de \n\n"; + print "-h --help\tPrints the usage manual.\n"; + print "-a --all\tRun all compile script. By default the script is going to run the whole process.\n"; + print "-s --syn\tRun synthesis part of the compile script.\n"; + print "-mp --map\tRun map part of the compile script.\n"; + print "-p --par\tRun par part of the compile script.\n"; + print "-t --timing\tRun timing analysis part of the compile script.\n"; + print "-b --bitgen\tRun bit generation part of the compile script.\n"; + print "-m --mpar\tSwitch for multi par. \"-m \" (Default = off)\n"; + print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt)\n"; + print "\n"; + exit; +} + +if ($nrNodes!=0){ + $isMultiPar=1; +} +if ($syn!=0 || $map!=0 || $par!=0 || $timing!=0 || $bitgen!=0){ + $all=0; +} +################################################################################### + + +# source the standard lattice environment +$ENV{bindir}="$lattice_bin_path"; +open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or + die "Can't fork: $!"; +while (<$SOURCE>) { + if (/^(.*)=(.*)/) { + $ENV{$1} = ${2} ; + } +} +close $SOURCE; + + + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'LC_ALL'}="en_US\@UTF-8"; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA1156"; +my $SPEEDGRADE="8"; + +my $WORKDIR = "workdir"; +unless(-d $WORKDIR) { + mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; + system ("cd workdir; ../../../trb3/base/linkdesignfiles.sh; cd ..;"); +} + +system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); + +#create full lpf file +print GREEN, "Generating constraints file...\n\n", RESET; +system("cp ../pinout/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); +system("cat ../tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat ../tdc_release/tdc_constraints_script.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat ../tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + +#copy delay line to project folder +system("ln -s ../tdc_release/Adder_304.ngo $WORKDIR/"); + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; +my @a = (); +my $tpmap = $TOPNAME . "_map" ; + +chdir $WORKDIR; +if($syn==1 || $all==1){ + print GREEN, "Starting synthesis process...\n\n", RESET; + $c="$synplify_command -batch ../$TOPNAME.prj"; + $r=execute($c, "do_not_exit" ); + + $fh = new FileHandle("<$TOPNAME".".srr"); + @a = <$fh>; + $fh -> close; + + foreach (@a) + { + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | egrep --color \"\@E:\""; + system($c); + print RED, "ERROR in the log file $TOPNAME.srr Exiting...\n\n", RESET; + exit 129; + } + } +} + + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +if($map==1 || $all==1){ + print GREEN, "Starting mapping process...\n\n", RESET; + + $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; + execute($c); + + $c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; + execute($c); + + $c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; + execute($c); + + $c=qq|map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; + execute($c); + + $c=qq|htmlrpt -mrp $TOPNAME.mrp $TOPNAME|; + execute($c); + + $fh = new FileHandle("<$TOPNAME"."_mrp.html"); + @a = <$fh>; + $fh -> close; + my $i=1; + my $print=0; + foreach (@a) + { + if(/WARNING/|$print) + { + if((grep /WARNING - map: There are semantic errors in the preference file/, $_) & ($i == 1)) + { + last; + } + elsif(grep /WARNING - map: There are semantic errors in the preference file/, $_) + { + print YELLOW, "There are errors in the constraints file. Better have a look...\n\n", RESET; + #sleep(5); # ERROR -> sleep is effective before the print + last; + } + elsif ($i == 1) + { + print RED,"\n\n", RESET; + print RED,"#################################################\n", RESET; + print RED,"CONSTRAINTS ERRORS\n", RESET; + print RED,"#################################################\n\n", RESET; + } + $print=1; + if(grep /WARNING.*UGROUP/, $_) + { + print RED, $_, RESET; + } + elsif(grep /FC|hitBuf|ff_en/, $_) + { + print YELLOW, $_, RESET; + } + else + { + print $_; + } + $i++; + } + } +} + +if($par==1 || $all==1){ + print GREEN, "Starting placement process...\n\n", RESET; + + system("rm $TOPNAME.ncd"); + if ($isMultiPar) + { + $c=qq|LC_ALL=en_US.UTF-8; par -m ../nodelist.txt -n $nrNodes -f "../par.p2t" $tpmap.ncd $TOPNAME.dir $TOPNAME.prf;|; + execute($c); + + # find and copy the .ncd file which has met the timing constraints + $fh = new FileHandle("<$TOPNAME".".par"); + my @a = <$fh>; + my $isSuccess = 0; + $fh -> close; + my $i=1; + foreach (@a) + { + my @line = split(/\s+/, $_); + + if(@line && ($line[2] =~ m/^[0-9]+$/) && ($line[4] =~ m/^[0-9]+$/)) + { + if(($line[2] == 0) && ($line[4] == 0)) + { + print GREEN, "Copying $line[0].ncd file to workdir\n", RESET; + my $c="cp $TOPNAME.dir/$line[0].ncd $TOPNAME.ncd"; + system($c); + print "\n\n"; + $isSuccess = 1; + last; + } + } + } + + if (!$isSuccess){ + print RED, "\n\n", RESET; + print RED, "#################################################\n", RESET; + print RED, "# !!!PAR not succesfull!!! #\n", RESET; + print RED, "#################################################\n\n", RESET; + exit 129; + } + } + else + { + $c=qq|par -f "../par.p2t" $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + execute($c); + my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; + system($c); + } + my $c="cat $TOPNAME.par"; + system($c); + +} + + +if($timing==1 || $all==1){ + print GREEN, "Generating timing report...\n\n", RESET; + + # IOR IO Timing Report + $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + # TWR Timing Report + $c=qq|trce -c -v 65 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + $c=qq|trce -hld -c -v 65 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + my $c="cat $TOPNAME.par"; + system($c); +} + +if($bitgen==1 || $all==1){ + print GREEN, "Generating bit file...\n\n", RESET; + + $c=qq|ltxt2ptxt $TOPNAME.ncd|; + execute($c); + + $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; + execute($c); +} + +$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|; +execute($c); + +if($config{firefox_open}) { + $c=qq|firefox $TOPNAME.html|; + execute($c); + } + +chdir ".."; +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print GREEN, "\n\ncommand to execute: $c \n", RESET; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/scripts/nodes_frankfurt.txt b/scripts/nodes_frankfurt.txt new file mode 100644 index 0000000..e69de29 diff --git a/scripts/nodes_lxhadeb07.txt b/scripts/nodes_lxhadeb07.txt new file mode 100644 index 0000000..b25022f --- /dev/null +++ b/scripts/nodes_lxhadeb07.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + +[lxhadeb07] +SYSTEM = linux +CORENUM = 32 +ENV = /u/cugur/depc363/bin/diamond_setup_x64.sh +WORKDIR = /u/cugur/depc363/Projects/TDC_on_TRB3/trb3/wasa/workdir diff --git a/tdc_release b/tdc_release new file mode 120000 index 0000000..4f793e3 --- /dev/null +++ b/tdc_release @@ -0,0 +1 @@ +../tdc/releases/tdc_v2.1.3 \ No newline at end of file diff --git a/template/compile.pl b/template/compile.pl new file mode 120000 index 0000000..4456748 --- /dev/null +++ b/template/compile.pl @@ -0,0 +1 @@ +../scripts/compile.pl \ No newline at end of file diff --git a/template/config.vhd b/template/config.vhd new file mode 100644 index 0000000..cdd92bd --- /dev/null +++ b/template/config.vhd @@ -0,0 +1,84 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; --not implemented yet! + constant USE_EXTERNAL_CLOCK : integer := c_YES; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3CC"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60"; + + + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); +begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20 + t(7 downto 0) := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8)); + t(11 downto 8) := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type + t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1)); + t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1)); + t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; +end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; \ No newline at end of file diff --git a/template/config_compile.pl b/template/config_compile.pl new file mode 120000 index 0000000..52cd2ef --- /dev/null +++ b/template/config_compile.pl @@ -0,0 +1 @@ +config_compile_frankfurt.pl \ No newline at end of file diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl new file mode 100644 index 0000000..1b78812 --- /dev/null +++ b/template/config_compile_frankfurt.pl @@ -0,0 +1,12 @@ +TOPNAME => "trb3sc_basic", +lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.4_x64', +synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/', +synplify_command => "/d/jspc29/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + + +firefox_open => 0, + + diff --git a/template/nodelist.txt b/template/nodelist.txt new file mode 120000 index 0000000..072269e --- /dev/null +++ b/template/nodelist.txt @@ -0,0 +1 @@ +../scripts/nodes_frankfurt.txt \ No newline at end of file diff --git a/template/par.p2t b/template/par.p2t new file mode 100644 index 0000000..f72683d --- /dev/null +++ b/template/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 24 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/template/trb3sc_basic.lpf b/template/trb3sc_basic.lpf new file mode 100644 index 0000000..e69de29 diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj new file mode 100644 index 0000000..22be06a --- /dev/null +++ b/template/trb3sc_basic.prj @@ -0,0 +1,172 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_basic" +set_option -resource_sharing false + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_basic.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3/base/code/clock_switch.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" + + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + + + + +add_file -vhdl -lib work "./trb3sc_basic.vhd" + + + + diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd new file mode 100644 index 0000000..81addaf --- /dev/null +++ b/template/trb3sc_basic.vhd @@ -0,0 +1,480 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define.all; + + + + +entity trb3sc_basic is + port( + CLK_SUPPL_PCLK : in std_logic; + CLK_SUPPL_PLL_LEFT : in std_logic; + CLK_SUPPL_PLL_RIGHT : in std_logic; + CLK_CORE_PCLK : in std_logic; + CLK_CORE_PLL_LEFT : in std_logic; + CLK_CORE_PLL_RIGHT : in std_logic; + CLK_EXT_PCLK : in std_logic; + CLK_EXT_PLL_LEFT : in std_logic; + CLK_EXT_PLL_RIGHT : in std_logic; + + TRIG_PLL : in std_logic; + TRIG_LEFT : in std_logic; + TRIG_RIGHT : in std_logic; + + --Backplane + BACK_GPIO : inout std_logic_vector(15 downto 0); + BACK_LVDS : inout std_logic_vector( 1 downto 0); + BACK_3V3 : inout std_logic_vector( 3 downto 0); + + --AddOn Connector + --to be added + + --KEL Connector + KEL : inout std_logic_vector(40 downto 1); + + --Additional IO + HDR_IO : inout std_logic_vector( 9 downto 0); + RJ_IO : inout std_logic_vector( 3 downto 0); + SPARE_IN : in std_logic_vector( 1 downto 0); + + --LED + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_YELLOW : out std_logic; + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0); + SFP_MOD2 : inout std_logic_vector( 1 downto 0); + SFP_TX_DIS : out std_logic_vector( 1 downto 0); + + SERDES_TX : out std_logic_vector(27 downto 0); + SERDES_RX : in std_logic_vector(27 downto 0); + + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_RJ_GREEN : signal is false; + attribute syn_useioff of LED_RJ_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of LED_WHITE : signal is false; + attribute syn_useioff of LED_SFP_GREEN : signal is false; + attribute syn_useioff of LED_SFP_RED : signal is false; + + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of TRIG_LEFT : signal is false; + attribute syn_useioff of TRIG_RIGHT : signal is false; + + attribute syn_useioff of SFP_LOS : signal is false; + attribute syn_useioff of SFP_MOD0 : signal is false; + attribute syn_useioff of SFP_MOD1 : signal is false; + attribute syn_useioff of SFP_MOD2 : signal is false; + attribute syn_useioff of SFP_TX_DIS : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + + + --Serdes: Backplane + --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane + --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,-- + --SFP D0,B3(D1) D0: GbE, B3: TrbNet + + +end entity; + +architecture trb3sc_arch of trb3sc_basic is + + signal clk_sys, clk_osc : std_logic; + signal clk_200_i : std_logic; + + signal clk_half_osc, clk_half_rx : std_logic; + signal clk_full_osc, clk_full_rx : std_logic; + + signal pll_lock : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic_vector (1*1-1 downto 0); + signal med_read_out : std_logic_vector (1*1-1 downto 0); + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic_vector (1*1-1 downto 0); + signal med_read_in : std_logic_vector (1*1-1 downto 0); + + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_rx, bussci_rx, busflash_rx, bussed_rx, bustc_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, busflash_tx, bussed_tx, bustc_tx : CTRLBUS_TX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + +begin + +--------------------------------------------------------------------------- +-- Reset Handling +--------------------------------------------------------------------------- + + +GSR_N <= pll_lock; + +THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_full_osc, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_sys, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + +THE_CLOCK_SELECT: entity work.clock_switch + port map( + INT_CLK_IN => CLK_CORE_PCLK, + SYS_CLK_IN => clk_sys, + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + PLL_LOCK => pll_lock, + RESET_IN => reset_i, + RESET_OUT => open, + + CLOCK_SELECT => clock_select, + DEBUG_OUT => open + ); + +THE_CLOCK_SWITCH: DCS + port map( + SEL => clock_select, + CLK0 => CLK_CORE_PCLK, + CLK1 => CLK_EXT_PCLK, + DCSOUT => clk_osc + ); + + +THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => clk_osc, + RESET => '0', + CLKOP => clk_half_osc, + CLKOK => clk_full_osc, + LOCK => pll_lock + ); + + +clk_sys <= clk_half_osc; --clk_half_rx; + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + +THE_MEDIA_INTERFACE : med_ecp3_sfp_sync + generic map( + SERDES_NUM => 3, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MED_DATA_IN => med_data_out(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + CLK_RX_HALF_OUT => clk_half_rx, + CLK_RX_FULL_OUT => clk_full_rx, + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_RXD_P_IN => SERDES_RX(0), + SD_RXD_N_IN => SERDES_RX(1), + SD_TXD_P_OUT => SERDES_TX(0), + SD_TXD_N_OUT => SERDES_TX(1), + SD_REFCLK_P_IN => '0', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => SFP_MOD0(1), + SD_LOS_IN => SFP_LOS(1), + SD_TXDIS_OUT => SFP_TX_DIS(1), + --Control Interface + SCI_DATA_IN => bussci_RX.data(7 downto 0), + SCI_DATA_OUT => bussci_TX.data(7 downto 0), + SCI_ADDR => bussci_RX.addr(8 downto 0), + SCI_READ => bussci_RX.read, + SCI_WRITE => bussci_RX.write, + SCI_ACK => bussci_TX.ack, + SCI_NACK => bussci_TX.unknown, + -- Status and control port + STAT_OP => med_stat_op(15 downto 0), + CTRL_OP => med_ctrl_op(15 downto 0), + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 10, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**8, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MED_DATAREADY_OUT => med_dataready_out(0), + MED_DATA_OUT => med_data_out(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(2 downto 0), + MED_READ_IN => med_read_in(0), + MED_DATAREADY_IN => med_dataready_in(0), + MED_DATA_IN => med_data_in(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(2 downto 0), + MED_READ_OUT => med_read_out(0), + MED_STAT_OP_IN => med_stat_op(15 downto 0), + MED_CTRL_OP_OUT => med_ctrl_op(15 downto 0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIME_GLOBAL_OUT => open, --global time, microseconds + TIME_LOCAL_OUT => open, --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT => open, --local time, resetted with each trigger + TIME_TICKS_OUT => open --bit 1 ms-tick, 0 us-tick + + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d500", 2 => x"b000", 3 => x"d300", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 2, 2 => 9, 3 => 1, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => busflash_rx, --Flash + BUS_RX(1) => bussed_rx, --SED + BUS_RX(2) => bussci_rx, --SCI Serdes + BUS_RX(3) => bustc_rx, --Clock switch + BUS_TX(0) => busflash_tx, + BUS_TX(1) => bussed_tx, + BUS_TX(2) => bussci_tx, + BUS_TX(3) => bustc_tx, + + STAT_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- Flash & Reboot +--------------------------------------------------------------------------- + + THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload_record + port map( + CLK_IN => clk_sys, + RESET_IN => reset_i, + + BUS_RX => busflash_rx, + BUS_TX => busflash_tx, + + DO_REBOOT_IN => common_ctrl_reg(15), + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => FLASH_CS, + SPI_SCK_OUT => FLASH_CLK, + SPI_SDO_OUT => FLASH_IN, + SPI_SDI_IN => FLASH_OUT + ); + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck + port map( + CLK => clk_sys, + ERROR_OUT => sed_error_i, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx, + DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- Switches +--------------------------------------------------------------------------- + +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + HDR_IO <= (others => '0'); + RJ_IO <= "0000"; + + + BACK_GPIO <= (others => 'Z'); + BACK_LVDS <= (others => '0'); + BACK_3V3 <= (others => 'Z'); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= '0'; + LED_ORANGE <= '0'; + LED_RED <= not sed_error_i; + LED_YELLOW <= '0'; + + LED_RJ_GREEN <= '0' & not std_logic_vector(to_unsigned(USE_RXCLOCK,1)); --1 must be 0, + LED_RJ_RED <= not clock_select & std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + LED_WHITE <= time_counter(26) & time_counter(28); + LED_SFP_GREEN <= not med_stat_op(9) & '1'; --SFP Link Status + LED_SFP_RED <= not (med_stat_op(10) or med_stat_op(11)) & '1'; --SFP RX/TX + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + end process; + + +end architecture; + + + +