From: Jan Michel <j.michel@gsi.de>
Date: Mon, 2 May 2016 11:38:41 +0000 (+0200)
Subject: Update padiwa compile script, add input counters to repo
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d97a8748d95b3748c475462cbd6db5f49d9dc617;p=padiwa.git

Update padiwa compile script, add input counters to repo
---

diff --git a/.gitignore b/.gitignore
index 30702df..1cd8233 100644
--- a/.gitignore
+++ b/.gitignore
@@ -22,3 +22,6 @@ reportview.xml
 */project/
 */project2/
 design
+*.dir
+pad_pad*
+v123/panda_dirc_wasa/*
diff --git a/v123/compile_panda_dirc_wasa_frankfurt.pl b/v123/compile_panda_dirc_wasa_frankfurt.pl
index 3e1a6a4..eaa5280 100755
--- a/v123/compile_panda_dirc_wasa_frankfurt.pl
+++ b/v123/compile_panda_dirc_wasa_frankfurt.pl
@@ -9,9 +9,9 @@ use strict;
 ###################################################################################
 #Settings for this project
 my $TOPNAME                      = "panda_dirc_wasa";  #Name of top-level entity
-my $lattice_path                 = '/d/jspc29/lattice/diamond/3.0_x64';
-my $synplify_path                = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lattice_path                 = '/d/jspc29/lattice/diamond/3.7_x64';
+my $synplify_path                = '/d/jspc29/lattice/synplify/L-2016.03/';
+my $lm_license_file_for_synplify = "27020\@jspc29";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 ###################################################################################
 
@@ -101,41 +101,41 @@ foreach (@a)
 $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
 
 
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
 execute($c);
 
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
 execute($c);
 
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
 execute($c);
 
 my $tpmap = $TOPNAME . "_map" ;
 
-$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
 execute($c);
 
 system("rm $TOPNAME.ncd");
 
 #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
 #  $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/par -w -l 5 -i 6 -t 5 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
 execute($c);
 # IOR IO Timing Report
-# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-# execute($c);
+$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
 
 # TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
 # $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
 # execute($c);
 
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -jedec  $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|;
+$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -jedec  $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|;
 # $c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd"  "$TOPNAME.prf"|;
 execute($c);
 
diff --git a/v123/panda_dirc_wasa.ldf b/v123/panda_dirc_wasa.ldf
index 8859660..0b870b5 100644
--- a/v123/panda_dirc_wasa.ldf
+++ b/v123/panda_dirc_wasa.ldf
@@ -1,12 +1,12 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="1.3" title="panda_dirc_wasa" device="LCMXO2-4000HC-6FTG256C" default_implementation="panda_dirc_wasa">
+<BaliProject version="3.2" title="pad" device="LCMXO2-4000HC-6FTG256C" default_implementation="pad">
     <Options/>
-    <Implementation title="panda_dirc_wasa" dir="panda_dirc_wasa" description="panda_dirc_wasa" default_strategy="Strategy1">
+    <Implementation title="pad" dir="panda_dirc_wasa" description="panda_dirc_wasa" synthesis="synplify" default_strategy="Strategy1">
         <Options top="panda_dirc_wasa"/>
         <Source name="panda_dirc_wasa.vhd" type="VHDL" type_short="VHDL">
             <Options top_module="panda_dirc_wasa"/>
         </Source>
-        <Source name="../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
@@ -15,7 +15,7 @@
         <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="source/spi_slave.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../source/spi_slave.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
@@ -24,28 +24,37 @@
         <Source name="version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="cores/oddr16.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../cores/oddr16.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="source/pwm.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../source/pwm.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="cores/efb_define_def.v" type="Verilog" type_short="Verilog">
+        <Source name="../cores/efb_define_def.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="cores/UFM_WB_top.v" type="Verilog" type_short="Verilog">
+        <Source name="../cores/pll.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="cores/pll.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../cores/flashram.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="cores/flashram.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../cores/flash.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="cores/flash.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../cores/UFM_WB.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="../base/panda_dirc_wasa1.lpf" type="Logic Preference" type_short="LPF">
+        <Source name="../source/ffarray.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../cores/fifo_1kx8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../cores/pll_shifted_clocks.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="workdir/panda_dirc_wasa.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
     </Implementation>
diff --git a/v123/panda_dirc_wasa.vhd b/v123/panda_dirc_wasa.vhd
index e71cfbb..9405744 100644
--- a/v123/panda_dirc_wasa.vhd
+++ b/v123/panda_dirc_wasa.vhd
@@ -204,7 +204,7 @@ signal inp_status   : std_logic_vector(15 downto 0);
 signal led_status   : std_logic_vector(4  downto 0) := "10000";
 
 signal timer    : unsigned(18 downto 0) := (others => '0');
-signal last_inp : std_logic_vector(3 downto 0) := (others => '0');
+signal last_inp : std_logic_vector(15 downto 0) := (others => '0');
 signal leds     : std_logic_vector(3 downto 0) := (others => '0');
 signal last_leds: std_logic_vector(3 downto 0) := (others => '0');
 signal onewire_monitor : std_logic;
@@ -248,6 +248,9 @@ signal comp_setting_s   : std_logic_vector(15 downto 0);
 signal ffarr_data       : std_logic_vector(15 downto 0);
 signal ffarr_read       : std_logic;
 
+type counter_arr is array(0 to 15) of unsigned(23 downto 0);
+signal input_counter    : counter_arr;
+
 begin
 
 
@@ -551,7 +554,7 @@ flash_reset_n <= not onewire_reset;
 ---------------------------------------------------------------------------  
 THE_IO_REG_READ : process begin
   wait until rising_edge(clk_i);
-  if spi_channel_i(4) = '0' then
+  if spi_channel_i(7 downto 4) = x"0" then
     case spi_channel_i(3 downto 0) is
       when x"0" => spi_reg20_i <= input_enable;
       when x"1" => spi_reg20_i <= inp_status;
@@ -563,13 +566,17 @@ THE_IO_REG_READ : process begin
       when x"f" => spi_reg20_i <= ffarr_data; 
       when others => null;
     end case;
-  else
+  elsif spi_channel_i(7 downto 4) = x"1" then
     case spi_channel_i(3 downto 0) is
       when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));
       when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));
       when x"2" => spi_reg20_i <= x"000" & std_logic_vector(to_unsigned(PADIWA_FLAVOUR,4));
       when others => null;
     end case;
+  elsif spi_channel_i(7 downto 4) = x"2" then
+    spi_reg20_i <= std_logic_vector(input_counter(to_integer(unsigned(spi_channel_i(3 downto 0))))(15 downto 0));
+  elsif spi_channel_i(7 downto 4) = x"3" then
+    spi_reg20_i <= x"00" & std_logic_vector(input_counter(to_integer(unsigned(spi_channel_i(3 downto 0))))(23 downto 16));
   end if;
 end process;
 
@@ -590,7 +597,7 @@ THE_IO_REG_WRITE : process begin
 end process;
 
 inp_status <= INP_i when rising_edge(clk_i);
-last_inp <= inp_status(3 downto 0) when rising_edge(clk_i);
+last_inp <= inp_status when rising_edge(clk_i);
 
 temperature_i_s <= temperature_i when rising_edge(clk_26);
 comp_setting_s <= comp_setting when rising_edge(clk_26);
@@ -610,13 +617,22 @@ end generate;
 PROC_TIMER : process begin
   wait until rising_edge(clk_i);
   timer <= timer + 1;
-  leds <= (last_inp xor inp_status(3 downto 0)) or leds or last_leds;
+  leds <= (last_inp(3 downto 0) xor inp_status(3 downto 0)) or leds or last_leds;
   if timer = 0 then
     leds <= not inp_status(3 downto 0);
     last_leds <= x"0";
   end if;
 end process;
 
+gen_input_counter : for i in 0 to 15 generate
+  proc_cnt : process begin
+    wait until rising_edge(clk_i);
+    if (inp_status(i) /=  inp_invert(i)) and (last_inp(i) = inp_invert(i)) then
+      input_counter(i) <= input_counter(i) + 1;
+    end if;
+  end process;
+end generate;
+
 
 ---------------------------------------------------------------------------
 -- Rest of the I/O