From: hadeshyp Date: Thu, 22 Jul 2010 14:48:22 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~217 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d9fc66d9e26de45f82667ec836e8ccd8777a6804;p=trbnet.git *** empty log message *** --- diff --git a/special/adc_ltc2308_readout.vhd b/special/adc_ltc2308_readout.vhd index 7d51b12..da75d2c 100644 --- a/special/adc_ltc2308_readout.vhd +++ b/special/adc_ltc2308_readout.vhd @@ -223,7 +223,7 @@ begin current_channel <= "000"; input_data <= (others => '0'); timecounter <= (others => '0'); - status_overview <= (others => '0'); +-- status_overview <= (others => '0'); first_sequence_after_stop <= '1'; real_conv_reset <= '0'; conv_reset_clr <= '0'; @@ -238,6 +238,9 @@ begin ADC_SCK <= '0'; ram_write <= '0'; conv_single_clr <= '0'; + if conv_reset = '1' then + status_overview <= (others => '0'); + end if; if conv_enabled = '1' or conv_single = '1' then state <= SEND_DATA; ADC_CONVST <= '0'; --wake up device from nap, diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 0d4a94d..e919c2a 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -63,6 +63,7 @@ end entity; -- 15 - 0 : trigger number -- 23 - 16 : trigger code -- 27 - 24 : trigger type +-- 28 : suppress data -- Fifo has an internal output register. -- Output is valid two clock cycles after read @@ -120,6 +121,7 @@ architecture handler_data_arch of handler_data is signal lvl1_statusbits_i : std_logic_vector(31 downto 0); signal got_busy_release : std_logic_vector(DATA_INTERFACE_NUMBER downto 0); + signal data_buffer_write : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); signal data_counter : cnt16_DAT_t; signal buffer_state_bits : bits3_t; signal lvl1_state_bits : std_logic_vector(2 downto 0); @@ -173,13 +175,16 @@ begin end generate; - header_buffer_data_in <= x"00" & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; + header_buffer_data_in <= "0000000" & LVL1_TRG_INFO_IN(0) & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; --------------------------------------------------------------------------- -- Data Fifo(s) --------------------------------------------------------------------------- gen_fifos : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + + data_buffer_write(i) <= FEE_DATA_WRITE_IN(i) when current_buffer_state(i) = BUSY else '0'; + THE_DAT_FIFO : fifo_var_oreg generic map( FIFO_WIDTH => DATA_BUFFER_WIDTH+4, @@ -188,7 +193,7 @@ begin port map( Data => data_buffer_data_in(i*36+35 downto i*36), Clock => CLOCK, - WrEn => FEE_DATA_WRITE_IN(i), + WrEn => data_buffer_write(i), RdEn => IPU_DATA_READ_IN(i), Reset => RESET, AmFullThresh => std_logic_vector(to_unsigned(DATA_BUFFER_FULL_THRESH, DATA_BUFFER_DEPTH)), @@ -236,7 +241,7 @@ begin port map( Data => length_buffer_data_in(i*18+17 downto i*18), Clock => CLOCK, - WrEn => length_buffer_write(i), + WrEn => header_buffer_write, --length_buffer_write(i), RdEn => IPU_HDR_DATA_READ_IN, Reset => RESET, AmFullThresh => std_logic_vector(to_unsigned(HEADER_BUFFER_FULL_THRESH, HEADER_BUFFER_DEPTH)), diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd index 7955b74..8af3cfb 100644 --- a/special/handler_ipu.vhd +++ b/special/handler_ipu.vhd @@ -69,7 +69,7 @@ architecture handler_ipu_arch of handler_ipu is signal dat_fifo_read : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); signal dat_fifo_select, next_dat_fifo_select : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); signal dat_fifo_finished : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - signal dat_fifo_read_length : cnt10_DAT_t; + signal dat_fifo_read_length : cnt10_DAT_t := (others => (others => '0')); signal dat_fifo_valid_read, next_dat_fifo_valid_read : std_logic; signal ipu_dataready_i, next_ipu_dataready_i : std_logic; @@ -81,7 +81,7 @@ architecture handler_ipu_arch of handler_ipu is signal total_length, next_total_length : unsigned(15 downto 0); signal dat_fifo_number, next_dat_fifo_number : integer range 0 to DATA_INTERFACE_NUMBER-1; - + signal suppress_output, next_suppress_output : std_logic; begin @@ -107,6 +107,7 @@ begin dat_fifo_select <= next_dat_fifo_select; first_fifo_read <= next_first_fifo_read; dat_fifo_number <= next_dat_fifo_number; + suppress_output <= next_suppress_output; end if; end if; end process; @@ -115,7 +116,7 @@ begin THE_FSM : process(current_state, error_not_found, IPU_START_READOUT_IN, DAT_HDR_DATA_EMPTY_IN, DAT_HDR_DATA_IN, last_hdr_fifo_valid_read, ipu_dataready_i, IPU_READ_IN, error_missing, dat_fifo_valid_read, next_dat_fifo_number, - dat_fifo_finished, dat_fifo_number, DAT_DATA_IN) + dat_fifo_finished, dat_fifo_number, DAT_DATA_IN, suppress_output) begin next_state <= current_state; next_error_not_found <= error_not_found; @@ -127,6 +128,7 @@ begin next_ipu_finished_i <= '0'; next_first_fifo_read <= '0'; next_dat_fifo_number <= dat_fifo_number; + next_suppress_output <= suppress_output; case current_state is when IDLE => @@ -146,6 +148,7 @@ begin -- next_state <= GOT_LENGTH; if last_hdr_fifo_valid_read = '1' then next_state <= SEND_DHDR; + next_suppress_output <= DAT_HDR_DATA_IN(28); end if; -- when GOT_LENGTH => @@ -171,7 +174,7 @@ begin next_first_fifo_read <= not dat_fifo_finished(next_dat_fifo_number); end if; end if; - next_ipu_dataready_i <= dat_fifo_valid_read or (ipu_dataready_i and not IPU_READ_IN); + next_ipu_dataready_i <= (dat_fifo_valid_read or (ipu_dataready_i and not IPU_READ_IN)) and not suppress_output; next_ipu_data_i <= DAT_DATA_IN(dat_fifo_number*32+31 downto dat_fifo_number*32); when END_READOUT => @@ -200,7 +203,7 @@ begin gen_fifo_read : for i in 0 to DATA_INTERFACE_NUMBER-1 generate --Read signal for data fifos - dat_fifo_read(i) <= dat_fifo_select(i) and ((IPU_READ_IN and ipu_dataready_i) or first_fifo_read) and not dat_fifo_finished(i); + dat_fifo_read(i) <= dat_fifo_select(i) and ((IPU_READ_IN and (ipu_dataready_i or suppress_output)) or first_fifo_read) and not dat_fifo_finished(i); --Count words read from data fifos @@ -300,11 +303,9 @@ begin if current_state = IDLE then error_sync <= '0'; elsif dat_fifo_valid_read = '1' then - for i in 0 to DATA_INTERFACE_NUMBER-1 loop - if DAT_HDR_DATA_IN(3 downto 0) /= DAT_DATA_FLAGS_IN(dat_fifo_number*4+3 downto dat_fifo_number*4+0) then - error_sync <= '1'; - end if; - end loop; + if DAT_HDR_DATA_IN(3 downto 0) /= DAT_DATA_FLAGS_IN(dat_fifo_number*4+3 downto dat_fifo_number*4+0) then + error_sync <= '1'; + end if; end if; end if; end process; @@ -318,7 +319,7 @@ begin IPU_ERROR_PATTERN_OUT <= ipu_error_pattern_i; IPU_READOUT_FINISHED_OUT <= ipu_finished_i; - ipu_length_i <= std_logic_vector(total_length); + ipu_length_i <= std_logic_vector(total_length) when suppress_output = '0' else (others => '0'); DAT_HDR_DATA_READ_OUT <= hdr_fifo_read; DAT_DATA_READ_OUT <= dat_fifo_read; diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd index fdc5f7b..abfb5eb 100644 --- a/special/handler_lvl1.vhd +++ b/special/handler_lvl1.vhd @@ -218,7 +218,7 @@ begin if ( (RESET = '1') or (toc_rst = '1') ) then timeout_ctr <= (others => '0'); elsif( (toc_ce = '1') and (and_all(std_logic_vector(timeout_ctr)) = '0') ) then - timeout_ctr <= timeout_ctr + 1; + timeout_ctr <= timeout_ctr + to_unsigned(1,1); end if; end if; end process THE_TIMEOUT_CTR_PROC; @@ -267,7 +267,7 @@ begin NEXT_STATE <= IDLE; -- avoid latches next_toc_ce <= '0'; next_toc_rst <= '0'; - next_toc_save <= toc_save; + next_toc_save <= toc_save; next_trg_rel <= '0'; next_trg_rst <= '0'; next_val_trg <= '0'; @@ -331,7 +331,7 @@ begin NEXT_STATE <= LVL1FND; --WAITREL; end if; when BADTRG => bsm_x <= x"5"; - NEXT_STATE <= DONE; + NEXT_STATE <= DONE; next_trg_rel <= '1'; next_trg_rst <= '1'; when DONE => bsm_x <= x"7"; @@ -359,7 +359,7 @@ begin elsif( LVL1_INT_TRG_LOAD_IN = '1' ) then lvl1_int_trg_number <= unsigned(LVL1_INT_TRG_COUNTER_IN); elsif( lvl1_int_trg_ce = '1' ) then - lvl1_int_trg_number <= lvl1_int_trg_number + 1; + lvl1_int_trg_number <= lvl1_int_trg_number + to_unsigned(1,1); end if; end if; end process THE_INTERNAL_TRG_CTR_PROC; @@ -394,6 +394,7 @@ begin end if; end process COUNT_EDGES_AND_LENGTH_PROC; + --------------------------------------------------------------------------- -- Error bits --------------------------------------------------------------------------- diff --git a/testbenches/testbench_endpoint_hades_full_handler.vhd b/testbenches/testbench_endpoint_hades_full_handler.vhd index b3aa407..61194d3 100644 --- a/testbenches/testbench_endpoint_hades_full_handler.vhd +++ b/testbenches/testbench_endpoint_hades_full_handler.vhd @@ -187,7 +187,7 @@ proc_media_interface : process while 1 = 1 loop --send timing trigger - if timer = 20 or timer = 120 then + if timer = 20 or timer = 50 or timer = 150 then timing_trg <= '1'; event <= event + to_unsigned(1,1); wait for 50 ns; @@ -246,7 +246,7 @@ proc_media_interface : process -- lvl1 trigger if (timer >= 70 and timer < 75) or - (timer >= 140 and timer < 145) then + (timer >= 180 and timer < 185) then wait until falling_edge(clk); med_data_in <= x"0003"; med_packet_num_in <= c_H0; @@ -313,23 +313,23 @@ proc_write_data_1 : process while 1 = 1 loop wait until rising_edge(trg_valid_timing); wait for 100 ns; - wait until falling_edge(clk); - fee_data(31 downto 0) <= x"11110001"; - fee_data_write(0) <= '1'; - wait until falling_edge(clk); - fee_data_write(0) <= '0'; - wait until falling_edge(clk); - fee_data(31 downto 0) <= x"22220002"; - fee_data_write(0) <= '1'; - if event /= 0 then - wait until falling_edge(clk); - fee_data(31 downto 0) <= x"33330003"; - fee_data_write(0) <= '1'; - end if; - wait until falling_edge(clk); - fee_data_write(0) <= '0'; - wait until falling_edge(clk); - fee_trg_release(0) <= '1'; +-- wait until falling_edge(clk); +-- fee_data(31 downto 0) <= x"11110001"; +-- fee_data_write(0) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_write(0) <= '0'; +-- wait until falling_edge(clk); +-- fee_data(31 downto 0) <= x"22220002"; +-- fee_data_write(0) <= '1'; +-- if event /= 0 then +-- wait until falling_edge(clk); +-- fee_data(31 downto 0) <= x"33330003"; +-- fee_data_write(0) <= '1'; +-- end if; +-- wait until falling_edge(clk); +-- fee_data_write(0) <= '0'; +-- wait until falling_edge(clk); +-- fee_trg_release(0) <= '1'; wait until falling_edge(clk); fee_trg_release(0) <= '0'; fee_data_finished(0) <= '1'; @@ -343,26 +343,26 @@ proc_write_data_2 : process begin while 1 = 1 loop wait until rising_edge(trg_valid_timing); - wait for 300 ns; - wait until falling_edge(clk); - fee_data(63 downto 32) <= x"11110001"; - fee_data_write(1) <= '1'; - wait until falling_edge(clk); - fee_data_write(1) <= '0'; - wait until falling_edge(clk); - fee_data(63 downto 32) <= x"22220002"; - fee_data_write(1) <= '1'; - wait until falling_edge(clk); - fee_data(63 downto 32) <= x"33330003"; - fee_data_write(1) <= '1'; - wait until falling_edge(clk); - fee_data(63 downto 32) <= x"44440004"; - fee_data_write(1) <= '1'; - wait until falling_edge(clk); - fee_data_write(1) <= '0'; - wait for 200 ns; - wait until falling_edge(clk); - fee_trg_release(1) <= '1'; + wait for 700 ns; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"11110001"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_write(1) <= '0'; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"22220002"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"33330003"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"44440004"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_write(1) <= '0'; +-- wait for 200 ns; +-- wait until falling_edge(clk); +-- fee_trg_release(1) <= '1'; wait until falling_edge(clk); fee_trg_release(1) <= '0'; fee_data_finished(1) <= '1'; diff --git a/testbenches/testbench_endpoint_oep.vhd b/testbenches/testbench_endpoint_oep.vhd new file mode 100644 index 0000000..714ac03 --- /dev/null +++ b/testbenches/testbench_endpoint_oep.vhd @@ -0,0 +1,558 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.mdc_oepb_pack.all; + + +entity tb is + +end entity; + + +architecture tb_arch of tb is + constant NUMBER_OF_ADC : integer := 1; + + signal clk : std_logic := '1'; + signal reset : std_logic := '1'; + + signal med_data_in : std_logic_vector (16-1 downto 0) := (others => '0'); + signal med_packet_num_in : std_logic_vector (3-1 downto 0) := (others => '0'); + signal med_dataready_in : std_logic := '0'; + signal med_read_in : std_logic := '0'; + signal med_data_out : std_logic_vector (16-1 downto 0) := (others => '0'); + signal med_packet_num_out : std_logic_vector (3-1 downto 0) := (others => '0'); + signal med_dataready_out : std_logic := '0'; + signal med_read_out : std_logic := '0'; + signal med_stat_op : std_logic_vector (16-1 downto 0) := (others => '0'); + signal med_ctrl_op : std_logic_vector (16-1 downto 0) := (others => '0'); + signal med_stat_debug : std_logic_vector (64-1 downto 0) := (others => '0'); + + + --endpoint LVL1 trigger + signal trg_type : std_logic_vector (3 downto 0) := (others => '0'); + signal trg_valid_timing : std_logic := '0'; + signal trg_valid_notiming : std_logic := '0'; + signal trg_invalid : std_logic := '0'; + signal trg_data_valid : std_logic := '0'; + signal trg_number : std_logic_vector (15 downto 0) := (others => '0'); + signal trg_code : std_logic_vector (7 downto 0) := (others => '0'); + signal trg_information : std_logic_vector (23 downto 0) := (others => '0'); + signal trg_error_pattern : std_logic_vector (31 downto 0) := (others => '0'); + signal trg_release : std_logic := '0'; + signal trg_int_trg_number : std_logic_vector (15 downto 0) := (others => '0'); + + --FEE + signal fee_trg_release : std_logic_vector (NUMBER_OF_ADC-1 downto 0) := (others => '0'); + signal fee_trg_statusbits : std_logic_vector (NUMBER_OF_ADC*32-1 downto 0) := (others => '0'); + signal fee_data : std_logic_vector (NUMBER_OF_ADC*32-1 downto 0) := (others => '0'); + signal fee_data_write : std_logic_vector (NUMBER_OF_ADC-1 downto 0) := (others => '0'); + signal fee_data_finished : std_logic_vector (NUMBER_OF_ADC-1 downto 0) := (others => '0'); + signal fee_data_almost_full : std_logic_vector (NUMBER_OF_ADC-1 downto 0) := (others => '0'); + + signal timing_trg : std_logic := '0'; + + signal timer : unsigned(31 downto 0) := (others => '0'); + signal event : unsigned(15 downto 0) := (others => '0'); + signal readoutevent : unsigned(15 downto 0) := (others => '0'); + + + signal TAD : std_logic_vector(8 downto 0) := (others => 'Z'); + signal TAOD : std_logic := 'Z'; + signal TDST : std_logic := 'Z'; + signal RDYI : std_logic; + signal GDE : std_logic; + signal TRDYO : std_logic; + signal MODD : std_logic; + signal RES : std_logic; + signal TOK : std_logic; + signal WRM : std_logic; + signal TRSV : std_logic; + + signal COM_STOP_P : std_logic := '0'; + signal CMS : std_logic; + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + + signal common_ctrl_reg : std_logic_vector(95 downto 0); + signal ctrl_reg : std_logic_vector(63 downto 0); + signal token_back_i : std_logic; + + +begin + + ctrl_reg <= x"0000000000000010"; + + TRSV <= '0'; + + + UUT : trb_net16_endpoint_hades_full_handler + generic map( + DATA_INTERFACE_NUMBER => NUMBER_OF_ADC, + DATA_BUFFER_DEPTH => 9, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**8, + TRG_RELEASE_AFTER_DATA => c_YES, + TIMING_TRIGGER_RAW => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8 + ) + + port map( + -- Misc + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- Media direction port + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid, + LVL1_VALID_TIMING_TRG_OUT => trg_valid_timing, + LVL1_VALID_NOTIMING_TRG_OUT => trg_valid_notiming, + LVL1_INVALID_TRG_OUT => trg_invalid, + + LVL1_TRG_TYPE_OUT => trg_type, + LVL1_TRG_NUMBER_OUT => trg_number, + LVL1_TRG_CODE_OUT => trg_code, + LVL1_TRG_INFORMATION_OUT => trg_information, + LVL1_INT_TRG_NUMBER_OUT => trg_int_trg_number, + + --Response from FEE + FEE_TRG_RELEASE_IN => fee_trg_release, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits, + FEE_DATA_IN => fee_data, + FEE_DATA_WRITE_IN => fee_data_write, + FEE_DATA_FINISHED_IN => fee_data_finished, + FEE_DATA_ALMOST_FULL_OUT => fee_data_almost_full, + + --Slow Control Port + --common registers + REGIO_COMMON_STAT_REG_IN => (others => '0'), + REGIO_COMMON_CTRL_REG_OUT => open, + REGIO_COMMON_STAT_STROBE_OUT => open, + REGIO_COMMON_CTRL_STROBE_OUT => open, + --user defined registers + REGIO_STAT_REG_IN => (others => '0'), + REGIO_CTRL_REG_OUT => open, + REGIO_STAT_STROBE_OUT => open, + REGIO_CTRL_STROBE_OUT => open, + --internal data port + BUS_ADDR_OUT => open, + BUS_DATA_OUT => open, + BUS_READ_ENABLE_OUT => open, + BUS_WRITE_ENABLE_OUT => open, + BUS_TIMEOUT_OUT => open, + BUS_DATA_IN => (others => '0'), + BUS_DATAREADY_IN => '0', + BUS_WRITE_ACK_IN => '0', + BUS_NO_MORE_DATA_IN => '0', + BUS_UNKNOWN_ADDR_IN => '1', + --Onewire + ONEWIRE_INOUT => open, + ONEWIRE_MONITOR_IN => '0', + ONEWIRE_MONITOR_OUT => open, + --Config endpoint id, if not statically assigned + REGIO_VAR_ENDPOINT_ID => (others => '0'), + + --Timing registers + TIME_GLOBAL_OUT => open, + TIME_LOCAL_OUT => open, + TIME_SINCE_LAST_TRG_OUT => open, + TIME_TICKS_OUT => open, + + --Debugging & Status information + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open + ); + + + THE_MDC_CONTROL : mdc_control + port map( + CLK => CLK, + RESET => reset, + + A_ADD => TAD, + A_AOD => TAOD, + A_DST => TDST, + A_RDM => RDYI, + A_GDE => GDE, + A_RDO => TRDYO, + A_MOD => MODD, + A_RES => RES, + A_TOK => TOK, + A_WRM => WRM, + A_RESERVE => TRSV, + + TRIGGER_IN => COM_STOP_P, + TRIGGER_OUT => CMS, + TRIGGER_MONITOR_OUT => timing_trg, + + LVL1_TRG_DATA_VALID_IN => trg_data_valid, + LVL1_VALID_TIMING_TRG_IN => trg_valid_timing, + LVL1_VALID_NOTIMING_TRG_IN => trg_valid_notiming, + LVL1_INVALID_TRG_IN => trg_invalid, + LVL1_TRG_TYPE_IN => trg_type, + LVL1_TRG_NUMBER_IN => trg_number, + LVL1_TRG_INFORMATION_IN => trg_information, + LVL1_INT_TRG_NUMBER_IN => trg_int_trg_number, + LVL1_RELEASE_OUT => fee_trg_release(0), + LVL1_STATUSBITS_OUT => fee_trg_statusbits(31 downto 0), + + FEE_DATA_OUT => fee_data(31 downto 0), + FEE_DATA_WRITE_OUT => fee_data_write(0), + FEE_DATA_FINISHED_OUT => fee_data_finished(0), + + RAM_ADDRESS_IN => (others => '0'), + RAM_DATA_IN => (others => '0'), + RAM_DATA_OUT => open, + RAM_READ_ENABLE_IN => '0', + RAM_WRITE_ENABLE_IN => '0', + RAM_READY_OUT => open, + + STAT_ADDRESS_IN => (others => '0'), + STAT_DATA_OUT => open, + STAT_READ_ENABLE_IN => '0', + STAT_READY_OUT => open, + + RB_DATA_OUT => open, + RB_READ_ENABLE_IN => '0', + RB_READY_OUT => open, + RB_EMPTY_OUT => open, + + COMMON_STAT_REG_OUT => open, + COMMON_CTRL_REG_IN => common_ctrl_reg, + CTRL_REG_IN => ctrl_reg, + + DEBUG_OUT => open + ); + + + +proc_clk : process + begin + wait for 5 ns; + clk <= not clk; + end process; + +proc_reset : process + begin + reset <= '1'; + wait for 55 ns; + reset <= '0'; + wait; + end process; + + +--Begrun trigger + process + begin + common_ctrl_reg <= (95 => '1', others => '0'); + wait for 200 ns; + wait until rising_edge(CLK); + common_ctrl_reg(22) <= '1'; + wait until rising_edge(CLK); + common_ctrl_reg(22) <= '0'; + wait; + end process; + +--Token Back + process + begin + TRDYO <= '0'; + wait for 500 us; + TRDYO <= '1'; + wait for 50 ns; + TRDYO <= '0'; + wait for 340 us; + TRDYO <= '1'; + wait for 50 ns; + TRDYO <= '0'; + wait for 2500 us; + for i in 0 to 100 loop + wait until token_back_i = '1'; + TRDYO <= '1'; + wait for 50 ns; + TRDYO <= '0'; + end loop; + wait; + end process; + +-- Data I/O + process + begin + TAD <= (others => 'Z'); + TAOD <= 'Z'; + TDST <= 'Z'; + token_back_i <= '0'; + wait for 3000 us; + wait for 1 ns; + for j in 0 to 300 loop + wait until RDYI = '1'; + wait for 200 ns; + for i in 0 to 30 loop + TAD <= std_logic_vector(to_unsigned(i*2,9)); + TAOD <= '0'; + TDST <= '0'; + wait for 10 ns; + TDST <= '1'; + wait for 40 ns; + TDST <= '0'; + wait for 20 ns; + TAD <= std_logic_vector(to_unsigned(i*2+1,9)); + TAOD <= '1'; + TDST <= '0'; + wait for 10 ns; + TDST <= '1'; + wait for 40 ns; + TDST <= '0'; + wait for 20 ns; + end loop; + token_back_i <= '1'; + wait for 30 ns; + token_back_i <= '0'; + TAD <= (others => 'Z'); + TAOD <= 'Z'; + TDST <= 'Z'; + end loop; + wait; + end process; + + + +proc_media_interface : process + begin + med_stat_op <= (others => '0'); + event <= x"FFFF"; + readoutevent<= x"0000"; +wait for 4 ms; + wait for 59 ns; + med_read_in <= '1'; +-- first timing trigger + + + + while 1 = 1 loop + + --send timing trigger + if timer = 20 or timer = 7000 or timer = 14000 then + COM_STOP_P <= '1'; + event <= event + to_unsigned(1,1); + wait for 50 ns; + COM_STOP_P <= '0'; + end if; + + --ack in IPU channel + if (med_data_out = x"001A" or med_data_out = x"001B") and med_dataready_out = '1' and med_packet_num_out = c_H0 then + med_data_in <= x"001D"; + med_packet_num_in <= c_H0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0006"; + med_packet_num_in <= c_F1; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F2; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F3; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_dataready_in <= '0'; + end if; + + --ack in lvl1 channel + if (med_data_out = x"000A" or med_data_out = x"000B") and med_dataready_out = '1' and med_packet_num_out = c_H0 then + med_data_in <= x"000D"; + med_packet_num_in <= c_H0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0006"; + med_packet_num_in <= c_F1; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F2; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F3; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_dataready_in <= '0'; + end if; + + -- lvl1 trigger + if (timer >= 70 and timer < 75) or + (timer >= 7070 and timer < 7075) or + (timer >= 19070 and timer < 19075) then + wait until falling_edge(clk); + med_data_in <= x"0003"; + med_packet_num_in <= c_H0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"10CD"; + med_packet_num_in <= c_F1; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= std_logic_vector(event); + med_packet_num_in <= c_F2; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0001"; + med_packet_num_in <= c_F3; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_dataready_in <= '0'; + end if; + + + --ipu trigger + if (timer >= 320 and timer < 325) or + (timer >= 7520 and timer < 7525) then + med_data_in <= x"0013"; + med_packet_num_in <= c_H0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0000"; + med_packet_num_in <= c_F0; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"00CD"; + med_packet_num_in <= c_F1; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= std_logic_vector(readoutevent); + med_packet_num_in <= c_F2; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_data_in <= x"0001"; + med_packet_num_in <= c_F3; + med_dataready_in <= '1'; + wait until falling_edge(clk); + med_dataready_in <= '0'; + readoutevent <= readoutevent + to_unsigned(1,1); + end if; + + + wait until falling_edge(clk); + end loop; + + wait; + end process; + + +-- +-- proc_write_data_1 : process +-- begin +-- while 1 = 1 loop +-- wait until rising_edge(trg_valid_timing); +-- wait for 100 ns; +-- wait until falling_edge(clk); +-- fee_data(31 downto 0) <= x"11110001"; +-- fee_data_write(0) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_write(0) <= '0'; +-- wait until falling_edge(clk); +-- fee_data(31 downto 0) <= x"22220002"; +-- fee_data_write(0) <= '1'; +-- if event /= 0 then +-- wait until falling_edge(clk); +-- fee_data(31 downto 0) <= x"33330003"; +-- fee_data_write(0) <= '1'; +-- end if; +-- wait until falling_edge(clk); +-- fee_data_write(0) <= '0'; +-- wait until falling_edge(clk); +-- fee_trg_release(0) <= '1'; +-- wait until falling_edge(clk); +-- fee_trg_release(0) <= '0'; +-- fee_data_finished(0) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_finished(0) <= '0'; +-- end loop; +-- end process; +-- +-- +-- proc_write_data_2 : process +-- begin +-- while 1 = 1 loop +-- wait until rising_edge(trg_valid_timing); +-- wait for 700 ns; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"11110001"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_write(1) <= '0'; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"22220002"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"33330003"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data(63 downto 32) <= x"44440004"; +-- fee_data_write(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_write(1) <= '0'; +-- wait for 200 ns; +-- wait until falling_edge(clk); +-- fee_trg_release(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_trg_release(1) <= '0'; +-- fee_data_finished(1) <= '1'; +-- wait until falling_edge(clk); +-- fee_data_finished(1) <= '0'; +-- end loop; +-- end process; + + + +proc_timer : process(CLK) + begin + if rising_edge(CLK) then + timer <= timer + to_unsigned(1,1); + if timer = to_unsigned(400000,32) then + timer <= to_unsigned(0,32); + end if; + end if; + end process; + + +end architecture; \ No newline at end of file diff --git a/testbenches/testbench_mux.vhd b/testbenches/testbench_mux.vhd new file mode 100644 index 0000000..918730b --- /dev/null +++ b/testbenches/testbench_mux.vhd @@ -0,0 +1,461 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity tbmux is +end entity; + + +architecture arch of tbmux is + + component trb_net16_io_multiplexer is + port ( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + -- Internal direction port + INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + +component trb_net16_obuf is + generic ( + USE_ACKNOWLEDGE : integer range 0 to 1 := c_NO; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + DATA_COUNT_WIDTH : integer range 1 to 7 := 7; + -- max used buffer size is 2**DATA_COUNT_WIDTH. + SBUF_VERSION : integer range 0 to 5 := 5 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + -- Internal direction port + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + -- Status and control port + STAT_BUFFER : out std_logic_vector (31 downto 0); + CTRL_BUFFER : in std_logic_vector (31 downto 0); + CTRL_SETTINGS : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0); + TIMER_TICKS_IN : in std_logic_vector (1 downto 0) + ); +end component; + + signal CLK : std_logic := '1'; + signal RESET : std_logic := '1'; + + signal MED_DATAREADY_IN : STD_LOGIC; + signal MED_DATA_IN : STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + signal MED_PACKET_NUM_IN : STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + signal MED_READ_OUT : STD_LOGIC; + signal MED_DATAREADY_OUT : STD_LOGIC; + signal MED_DATA_OUT : STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + signal MED_PACKET_NUM_OUT : STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + signal MED_READ_IN : STD_LOGIC; + signal INT_DATA_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal INT_PACKET_NUM_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal INT_DATAREADY_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + signal INT_READ_IN : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + signal INT_DATAREADY_IN : STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + signal INT_DATA_IN : STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0); + signal INT_PACKET_NUM_IN : STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0); + signal INT_READ_OUT : STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + signal ctrl_data : std_logic_vector(15 downto 0); + signal ctrl_packet_num : std_logic_vector(2 downto 0); + signal ctrl_dataready : std_logic; + signal ctrl_read : std_logic; + + signal trg_data : std_logic_vector(15 downto 0); + signal trg_packet_num : std_logic_vector(2 downto 0); + signal trg_dataready : std_logic; + signal trg_read : std_logic; + +begin + + CLK <= not CLK after 5 ns; + RESET <= '0' after 100 ns; +-- +-- uut : trb_net16_io_multiplexer +-- port map( +-- CLK => CLK, +-- RESET => RESET, +-- CLK_EN => '1', +-- MED_DATAREADY_IN =>MED_DATAREADY_IN , +-- MED_DATA_IN =>MED_DATA_IN , +-- MED_PACKET_NUM_IN =>MED_PACKET_NUM_IN , +-- MED_READ_OUT =>MED_READ_OUT , +-- MED_DATAREADY_OUT =>MED_DATAREADY_OUT , +-- MED_DATA_OUT =>MED_DATA_OUT , +-- MED_PACKET_NUM_OUT =>MED_PACKET_NUM_OUT , +-- MED_READ_IN =>MED_READ_IN , +-- INT_DATA_OUT =>INT_DATA_OUT , +-- INT_PACKET_NUM_OUT =>INT_PACKET_NUM_OUT , +-- INT_DATAREADY_OUT =>INT_DATAREADY_OUT , +-- INT_READ_IN =>INT_READ_IN , +-- INT_DATAREADY_IN =>INT_DATAREADY_IN , +-- INT_DATA_IN =>INT_DATA_IN , +-- INT_PACKET_NUM_IN =>INT_PACKET_NUM_IN , +-- INT_READ_OUT =>INT_READ_OUT , +-- CTRL => (others => '0'), +-- STAT =>open +-- ); + + INT_READ_IN <= (others => '1'); + + + + obuf3 : trb_net16_obuf + generic map( + SBUF_VERSION => 5 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => '1', + -- Media direction port + MED_DATAREADY_OUT => INT_DATAREADY_IN(6), + MED_DATA_OUT => INT_DATA_IN(111 downto 96), + MED_PACKET_NUM_OUT => INT_PACKET_NUM_IN(20 downto 18), + MED_READ_IN => INT_READ_OUT(6), + -- Internal direction port + INT_DATAREADY_IN => ctrl_dataready, + INT_DATA_IN => ctrl_data, + INT_PACKET_NUM_IN => ctrl_packet_num, + INT_READ_OUT => ctrl_read, + -- Status and control port + STAT_BUFFER => open, + CTRL_BUFFER => (others => '0'), + CTRL_SETTINGS => (others => '0'), + STAT_DEBUG => open, + TIMER_TICKS_IN => "00" + ); + +-- obuf0 : trb_net16_obuf +-- generic map( +-- SBUF_VERSION => 5 +-- ) +-- port map( +-- CLK => CLK, +-- RESET => RESET, +-- CLK_EN => '1', +-- -- Media direction port +-- MED_DATAREADY_OUT => INT_DATAREADY_IN(0), +-- MED_DATA_OUT => INT_DATA_IN(15 downto 0), +-- MED_PACKET_NUM_OUT => INT_PACKET_NUM_IN(2 downto 0), +-- MED_READ_IN => INT_READ_OUT(0), +-- -- Internal direction port +-- INT_DATAREADY_IN => trg_dataready, +-- INT_DATA_IN => trg_data, +-- INT_PACKET_NUM_IN => trg_packet_num, +-- INT_READ_OUT => trg_read, +-- -- Status and control port +-- STAT_BUFFER => open, +-- CTRL_BUFFER => (others => '0'), +-- CTRL_SETTINGS => (others => '0'), +-- STAT_DEBUG => open, +-- TIMER_TICKS_IN => "00" +-- ); + + +-- INT_DATAREADY_IN(1) <= '0'; +-- INT_DATA_IN(31 downto 16) <= (others => '0'); +-- INT_PACKET_NUM_IN(5 downto 3) <= (others => '0'); +-- +-- INT_DATAREADY_IN(2) <= '0'; +-- INT_DATA_IN(47 downto 32) <= (others => '0'); +-- INT_PACKET_NUM_IN(8 downto 6) <= (others => '0'); +-- +-- INT_DATAREADY_IN(3) <= '0'; +-- INT_DATA_IN(63 downto 48) <= (others => '0'); +-- INT_PACKET_NUM_IN(11 downto 9) <= (others => '0'); +-- +-- INT_DATAREADY_IN(4) <= '0'; +-- INT_DATA_IN(79 downto 64) <= (others => '0'); +-- INT_PACKET_NUM_IN(14 downto 12) <= (others => '0'); +-- +-- INT_DATAREADY_IN(5) <= '0'; +-- INT_DATA_IN(95 downto 80) <= (others => '0'); +-- INT_PACKET_NUM_IN(17 downto 15) <= (others => '0'); +-- +-- INT_DATAREADY_IN(7) <= '0'; +-- INT_DATA_IN(127 downto 112) <= (others => '0'); +-- INT_PACKET_NUM_IN(23 downto 21) <= (others => '0'); + +-- +-- process +-- begin +-- trg_dataready <= '0'; +-- trg_data <= (others => '0'); +-- trg_packet_num <= (others => '0'); +-- wait for 400 ns; +-- wait until rising_edge(CLK); +-- trg_dataready <= '0'; +-- trg_data <= (others => '0'); +-- trg_packet_num <= (others => '0'); +-- wait until rising_edge(CLK); +-- wait until rising_edge(CLK); +-- wait until rising_edge(CLK); +-- wait until rising_edge(CLK); +-- for i in 0 to 20 loop +-- trg_dataready <= '1'; +-- trg_data <= x"0013"; +-- trg_packet_num <= c_H0; +-- wait for 1 ns; if trg_read = '0' then wait until trg_read = '1'; end if; +-- wait until rising_edge(CLK); +-- trg_dataready <= '1'; +-- trg_data <= x"1111"; +-- trg_packet_num <= c_F0; +-- wait for 1 ns; if trg_read = '0' then wait until trg_read = '1'; end if; +-- wait until rising_edge(CLK); +-- trg_dataready <= '1'; +-- trg_data <= x"2222"; +-- trg_packet_num <= c_F1; +-- wait for 1 ns; if trg_read = '0' then wait until trg_read = '1'; end if; +-- wait until rising_edge(CLK); +-- trg_dataready <= '1'; +-- trg_data <= x"3333"; +-- trg_packet_num <= c_F2; +-- wait for 1 ns; if trg_read = '0' then wait until trg_read = '1'; end if; +-- wait until rising_edge(CLK); +-- trg_dataready <= '1'; +-- trg_data <= x"4444"; +-- trg_packet_num <= c_F3; +-- wait for 1 ns; if trg_read = '0' then wait until trg_read = '1'; end if; +-- wait until rising_edge(CLK); +-- end loop; +-- trg_dataready <= '0'; +-- trg_data <= x"0000"; +-- trg_packet_num <= "000"; +-- wait; +-- end process; + + process + begin + INT_READ_OUT <= (others => '0'); + wait for 601 ns; + for i in 0 to 30 loop + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '0'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '0'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '0'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '0'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + INT_READ_OUT <= (others => '1'); wait until rising_edge(CLK); + end loop; + end process; + + process + begin + ctrl_dataready <= '0'; + ctrl_data <= (others => '0'); + ctrl_packet_num <= (others => '0'); + wait for 400 ns; + ctrl_dataready <= '1'; + ctrl_data <= x"0031"; + ctrl_packet_num <= c_H0; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"AAAA"; + ctrl_packet_num <= c_F0; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"BBBB"; + ctrl_packet_num <= c_F1; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '0'; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"CCCC"; + ctrl_packet_num <= c_F2; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"DDDD"; + ctrl_packet_num <= c_F3; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '0'; + wait until rising_edge(CLK); + --second packet + ctrl_dataready <= '1'; + ctrl_data <= x"0031"; + ctrl_packet_num <= c_H0; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"AAAA"; + ctrl_packet_num <= c_F0; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"BBBB"; + ctrl_packet_num <= c_F1; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '0'; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"CCCC"; + ctrl_packet_num <= c_F2; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"DDDD"; + ctrl_packet_num <= c_F3; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '0'; + wait until rising_edge(CLK); + wait until rising_edge(CLK); + for i in 0 to 20 loop + ctrl_dataready <= '1'; + ctrl_data <= x"0031"; + ctrl_packet_num <= c_H0; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"AAAA"; + ctrl_packet_num <= c_F0; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"BBBB"; + ctrl_packet_num <= c_F1; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"CCCC"; + ctrl_packet_num <= c_F2; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + ctrl_dataready <= '1'; + ctrl_data <= x"DDDD"; + ctrl_packet_num <= c_F3; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + end loop; + ctrl_dataready <= '1'; + ctrl_data <= x"0031"; + ctrl_packet_num <= c_H0; + wait for 1 ns; if ctrl_read = '0' then wait until ctrl_read = '1'; end if; + wait until rising_edge(CLK); + + ctrl_dataready <= '0'; + ctrl_data <= (others => '0'); + ctrl_packet_num <= (others => '0'); + wait; + end process; + + process + begin + + MED_DATAREADY_IN <= '0'; + MED_DATA_IN <= x"0000"; + MED_PACKET_NUM_IN <= "100"; + MED_READ_IN <= '1'; + + + wait for 100 ns; + wait until rising_edge(CLK); + MED_DATA_IN <= x"0031"; + MED_PACKET_NUM_IN <= c_H0; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"AAAA"; + MED_PACKET_NUM_IN <= c_F0; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"BBBB"; + MED_PACKET_NUM_IN <= c_F1; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"CCCC"; + MED_PACKET_NUM_IN <= c_F2; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"DDDD"; + MED_PACKET_NUM_IN <= c_F3; + MED_DATAREADY_IN <= '1'; + + wait until rising_edge(CLK); + MED_DATA_IN <= x"0013"; + MED_PACKET_NUM_IN <= c_H0; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"1111"; + MED_PACKET_NUM_IN <= c_F0; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"2222"; + MED_PACKET_NUM_IN <= c_F1; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"3333"; + MED_PACKET_NUM_IN <= c_F2; + MED_DATAREADY_IN <= '1'; + wait until rising_edge(CLK); + MED_DATA_IN <= x"4444"; + MED_PACKET_NUM_IN <= c_F3; + MED_DATAREADY_IN <= '1'; + + wait until rising_edge(CLK); + MED_DATA_IN <= (others => '0'); + MED_PACKET_NUM_IN <= c_H0; + MED_DATAREADY_IN <= '0'; + wait; + + + end process; + + +end architecture; + diff --git a/testbenches/testbench_sbuf5.vhd b/testbenches/testbench_sbuf5.vhd new file mode 100755 index 0000000..d46be35 --- /dev/null +++ b/testbenches/testbench_sbuf5.vhd @@ -0,0 +1,611 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net_sbuf5 + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CLK_EN : IN std_logic; + COMB_DATAREADY_IN : IN std_logic; + COMB_DATA_IN : IN std_logic_vector(18 downto 0); + SYN_READ_IN : IN std_logic; + COMB_next_READ_OUT : OUT std_logic; + SYN_DATAREADY_OUT : OUT std_logic; + SYN_DATA_OUT : OUT std_logic_vector(18 downto 0); + DEBUG : OUT std_logic_vector(7 downto 0); + DEBUG_BSM : OUT std_logic_vector(3 downto 0); + DEBUG_WCNT : OUT std_logic_vector(4 downto 0); + STAT_BUFFER : OUT std_logic + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CLK_EN : std_logic; + SIGNAL COMB_DATAREADY_IN : std_logic; + SIGNAL COMB_next_READ_OUT : std_logic; + SIGNAL COMB_DATA_IN : std_logic_vector(18 downto 0); + SIGNAL SYN_DATAREADY_OUT : std_logic; + SIGNAL SYN_DATA_OUT : std_logic_vector(18 downto 0); + SIGNAL SYN_READ_IN : std_logic; + SIGNAL STAT_BUFFER : std_logic; + SIGNAL DEBUG_BSM : std_logic_vector(3 downto 0); + SIGNAL DEBUG_WCNT : std_logic_vector(4 downto 0); + SIGNAL DEBUG : std_logic_vector(7 downto 0); + SIGNAL last_comb_next_read_out : std_logic; + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net_sbuf5 PORT MAP( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_next_READ_OUT => COMB_next_READ_OUT, + COMB_DATA_IN => COMB_DATA_IN, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => SYN_DATA_OUT, + SYN_READ_IN => SYN_READ_IN, + DEBUG => DEBUG, + DEBUG_BSM => DEBUG_BSM, + DEBUG_WCNT => DEBUG_WCNT, + STAT_BUFFER => STAT_BUFFER + ); + +-- Generate a free running 100MHz clock +THE_CLOCK_GEN: process +begin + clk <= '0'; wait for 5.0 ns; + clk <= '1'; wait for 5.0 ns; +end process THE_CLOCK_GEN; + +-- Generate a data input stream +--THE_DATA_IN_GEN: process +--variable packet_data : unsigned(15 downto 0) := x"0000"; +--variable packet_num : unsigned(3 downto 0) := x"0"; +--variable start_data : std_logic := '0'; +--variable end_data : std_logic := '0'; +--begin +-- wait until rising_edge(clk); +-- wait for 1.0 ns; +-- +-- comb_dataready_in <= '0'; +-- if ( reset = '1' ) then +-- start_data := '1'; +-- end_data := '0'; +-- elsif( (start_data = '1') and (end_data = '0') ) then +-- comb_data_in(15 downto 0) <= std_logic_vector(packet_data); +-- comb_dataready_in <= last_comb_next_read_out; +-- if( packet_num = x"0" ) then +-- comb_data_in(18 downto 16) <= b"111"; +-- else +-- comb_data_in(18 downto 16) <= b"000"; +-- end if; +-- if( COMB_next_READ_OUT = '1' ) then +-- packet_num := packet_num + 1; +-- packet_data := packet_data + 1; +-- if( packet_num = x"5") then +-- packet_num := x"0"; +-- end if; +-- if( packet_data = x"0096" ) then -- !!! +1 !!! +-- end_data := '1'; +-- end if; +-- end if; +-- end if; +--end process THE_DATA_IN_GEN; + +THE_SYNC_PROC: process( clk ) +begin + if( rising_edge(clk) ) then + last_comb_next_read_out <= COMB_next_READ_OUT; + end if; +end process THE_SYNC_PROC; + +-- The testbench itself +THE_TESTBENCH: process +begin + -- Setup signals + clk_en <= '1'; + reset <= '0'; + syn_read_in <= '0'; + comb_dataready_in <= '0'; + comb_data_in <= b"000_0000_0000_0000_0000"; + wait for 30 ns; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + reset <= '0'; + wait for 100 ns; + + -- Tests may start now + +-- Now we stream in, with some random breaks + wait until rising_edge(clk); + syn_read_in <= '0'; + + wait until rising_edge(clk); + comb_dataready_in <= '1'; + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"0000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"0001"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0004"; + wait until rising_edge(clk); + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"1000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"1001"; + syn_read_in <= '1'; + + comb_dataready_in <= '0'; + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"0000"; + wait until rising_edge(clk); + wait until rising_edge(clk); + comb_dataready_in <= '1'; + + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"1002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"1003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"1004"; + wait until rising_edge(clk); + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"2000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"2001"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"2002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"2003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"2004"; + wait until rising_edge(clk); + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"3000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"3001"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"3002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"3003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"3004"; + wait until rising_edge(clk); + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"4000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"4001"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"4002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"4003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"4004"; + wait until rising_edge(clk); + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"5000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"5001"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"5002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"5003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"5004"; + wait until rising_edge(clk); + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"6000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"6001"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"6002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"6003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"6004"; + wait until rising_edge(clk); + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"7000"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"7001"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"7002"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"7003"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"7004"; + wait until rising_edge(clk); + + + + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"8000"; + wait until rising_edge(clk); + + + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"8001"; + wait until rising_edge(clk); + + comb_data_in(15 downto 0) <= x"8002"; + wait until rising_edge(clk); + + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + + comb_data_in(15 downto 0) <= x"8003"; + wait until rising_edge(clk); + + comb_data_in(15 downto 0) <= x"8004"; + wait until rising_edge(clk); + + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + + + --Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"9000"; + wait until rising_edge(clk); + + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"9001"; + wait until rising_edge(clk); + + comb_dataready_in <= '0'; + + wait; + +------------------------------------------------------------------ +------------------------------------------------------------------ +------------------------------------------------------------------ + + -- First packet in stop&go mode, delayed syn_read_in + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"111_0000_0000_0000_0000"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_0001"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_0010"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_0011"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_0100"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + syn_read_in <= '1'; + + wait until falling_edge(syn_dataready_out); + wait until rising_edge(clk); + syn_read_in <= '0'; + wait until rising_edge(clk); + + wait for 55 ns; + + -- Second packet in alltogether mode, delayed syn_read_in + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"111_0000_0000_0000_0101"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0000_0110"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0000_0111"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0000_1000"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0000_1001"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + syn_read_in <= '1'; + + wait until falling_edge(syn_dataready_out); + wait until rising_edge(clk); + syn_read_in <= '0'; + wait until rising_edge(clk); + + wait for 55 ns; + + -- Third packet in stop&go mode, syn_read_in active + wait until rising_edge(clk); + syn_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"111_0000_0000_0000_1010"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_1011"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_1100"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_1101"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"000_0000_0000_0000_1110"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + + wait until falling_edge(syn_dataready_out); + wait until rising_edge(clk); + syn_read_in <= '0'; + wait until rising_edge(clk); + + wait for 55 ns; + + -- Fourth packet in alltogether mode, syn_read_in active + wait until rising_edge(clk); + syn_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"111_0000_0000_0000_1111"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_0001"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_0010"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_0011"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_0100"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + + wait until falling_edge(syn_dataready_out); + wait until rising_edge(clk); + syn_read_in <= '0'; + wait until rising_edge(clk); + + wait for 55 ns; + + -- Fifth and sixth packet in alltogether mode, syn_read_in active + wait until rising_edge(clk); + syn_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + wait until rising_edge(clk); + comb_dataready_in <= '1'; + comb_data_in <= b"111_0000_0000_0001_0101"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_0110"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_0111"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_1000"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_1001"; + wait until rising_edge(clk); + comb_data_in <= b"111_0000_0000_0000_1010"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_1011"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_1100"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_1101"; + wait until rising_edge(clk); + comb_data_in <= b"000_0000_0000_0001_1110"; + wait until rising_edge(clk); + comb_dataready_in <= '0'; + + wait until falling_edge(syn_dataready_out); + wait until rising_edge(clk); + syn_read_in <= '0'; + wait until rising_edge(clk); + + wait for 55 ns; + +-- Now we stream in, with some random breaks + wait until rising_edge(clk); + syn_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + wait until rising_edge(clk); + comb_dataready_in <= '1'; + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"001f"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"0020"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0021"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0022"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0023"; + wait until rising_edge(clk); + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"0024"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"0025"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0026"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0027"; + wait until rising_edge(clk); + + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"0000"; + comb_dataready_in <= '0'; +-- wait; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_dataready_in <= '1'; + + comb_data_in(15 downto 0) <= x"0028"; + wait until rising_edge(clk); + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"0029"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"002a"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"002b"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"002c"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"002d"; + wait until rising_edge(clk); + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"002e"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"002f"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0030"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0031"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0032"; + wait until rising_edge(clk); + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"0033"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"0034"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0035"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0036"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0037"; + wait until rising_edge(clk); + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"0038"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"0039"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"003a"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"003b"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"003c"; + wait until rising_edge(clk); + -- Packet + comb_data_in(18 downto 16) <= b"111"; + comb_data_in(15 downto 0) <= x"003d"; + wait until rising_edge(clk); + comb_data_in(18 downto 16) <= b"000"; + comb_data_in(15 downto 0) <= x"003e"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"003f"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0040"; + wait until rising_edge(clk); + comb_data_in(15 downto 0) <= x"0041"; + wait until rising_edge(clk); + + comb_dataready_in <= '0'; + + wait until falling_edge(syn_dataready_out); + wait until rising_edge(clk); + syn_read_in <= '0'; + wait until rising_edge(clk); + + wait for 55 ns; + + + wait; + + + -- Stay a while.... stay forever!!! + wait; + +end process THE_TESTBENCH; + + +END; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 1dd2fc2..efe22f2 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -27,6 +27,7 @@ entity trb_net16_endpoint_hades_full is APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers --standard values for output registers @@ -67,7 +68,7 @@ entity trb_net16_endpoint_hades_full is MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); -- LVL1 trigger APL - TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received or real timing trigger signal LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received @@ -143,7 +144,8 @@ entity trb_net16_endpoint_hades_full is CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end trb_net16_endpoint_hades_full; @@ -251,10 +253,37 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full signal buf_LVL1_VALID_TIMING_TRG_OUT : std_logic; signal buf_LVL1_VALID_NOTIMING_TRG_OUT : std_logic; signal buf_LVL1_INVALID_TRG_OUT : std_logic; + signal buf_LVL1_TRG_RELEASE_IN : std_logic; + signal buf_LVL1_TRG_DATA_VALID_OUT : std_logic; + + signal int_lvl1_delay : std_logic_vector(15 downto 0); + signal int_multiple_trg : std_logic; + signal int_trg_reset : std_logic; + signal reset_trg_logic : std_logic; + signal stat_lvl1_handler : std_logic_vector(63 downto 0); + signal trg_invert_i : std_logic; + + + signal last_TRG_TIMING_TRG_RECEIVED_IN : std_logic; + signal last_timingtrg_counter_write : std_logic; + signal last_timingtrg_counter_read : std_logic; + + signal reg_timing_trigger : std_logic; + signal trigger_timing_rising : std_logic; + signal last_reg_timing_trigger : std_logic; + + component edge_to_pulse is + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; begin - reset_no_link <= MED_STAT_OP_IN(14) or RESET; + reset_no_link <= MED_STAT_OP_IN(14) or RESET; + reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1); --MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15); MED_CTRL_OP_OUT(15 downto 0) <= (others => '0'); MED_STAT_OP <= MED_STAT_OP_IN; @@ -451,7 +480,7 @@ begin TRG_NUMBER_OUT => buf_LVL1_TRG_NUMBER_OUT, TRG_CODE_OUT => buf_LVL1_TRG_CODE_OUT, TRG_INFORMATION_OUT => buf_LVL1_TRG_INFORMATION_OUT, - TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, + TRG_RELEASE_IN => buf_LVL1_TRG_RELEASE_IN, TRG_ERROR_PATTERN_IN => buf_LVL1_ERROR_PATTERN_IN ); end generate; @@ -548,7 +577,7 @@ begin IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN, IDRAM_WR_IN => buf_IDRAM_WR_IN, MY_ADDRESS_OUT => MY_ADDRESS, - TRIGGER_MONITOR => TRG_TIMING_TRG_RECEIVED_IN, + TRIGGER_MONITOR => buf_LVL1_VALID_TIMING_TRG_OUT, GLOBAL_TIME => GLOBAL_TIME_OUT, LOCAL_TIME => LOCAL_TIME_OUT, TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT, @@ -746,17 +775,79 @@ begin proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num) begin buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN; - buf_COMMON_STAT_REG_IN(4) <= not trigger_number_match; - buf_COMMON_STAT_REG_IN(8) <= timing_trigger_missing; +-- buf_COMMON_STAT_REG_IN(4) <= not trigger_number_match; +-- buf_COMMON_STAT_REG_IN(8) <= timing_trigger_missing; if REGIO_USE_1WIRE_INTERFACE = c_YES then buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature; end if; buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num; + buf_COMMON_STAT_REG_IN(127 downto 64) <= stat_lvl1_handler; end process; ------------------------------------------------- -- Check LVL1 trigger number ------------------------------------------------- + +-- THE_LVL1_HANDLER : handler_lvl1 +-- generic map ( +-- TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW +-- ) +-- port map( +-- RESET => reset_trg_logic, +-- CLOCK => CLK, +-- --Timing Trigger +-- LVL1_TIMING_TRG_IN => TRG_TIMING_TRG_RECEIVED_IN, +-- LVL1_PSEUDO_TMG_TRG_IN => buf_REGIO_COMMON_CTRL_REG_OUT(16), +-- --LVL1_handler connection +-- LVL1_TRG_RECEIVED_IN => buf_LVL1_TRG_RECEIVED_OUT, +-- LVL1_TRG_TYPE_IN => buf_LVL1_TRG_TYPE_OUT, +-- LVL1_TRG_NUMBER_IN => buf_LVL1_TRG_NUMBER_OUT, +-- LVL1_TRG_CODE_IN => buf_LVL1_TRG_CODE_OUT, +-- LVL1_TRG_INFORMATION_IN => buf_LVL1_TRG_INFORMATION_OUT, +-- LVL1_ERROR_PATTERN_OUT => buf_LVL1_ERROR_PATTERN_IN, +-- LVL1_TRG_RELEASE_OUT => buf_LVL1_TRG_RELEASE_IN, +-- +-- LVL1_INT_TRG_NUMBER_OUT => int_trigger_num, +-- LVL1_INT_TRG_LOAD_IN => buf_COMMON_CTRL_REG_STROBE(1), +-- LVL1_INT_TRG_COUNTER_IN => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32), +-- +-- --FEE logic / Data Handler +-- LVL1_TRG_DATA_VALID_OUT => buf_LVL1_TRG_DATA_VALID_OUT, +-- LVL1_VALID_TIMING_TRG_OUT => buf_LVL1_VALID_TIMING_TRG_OUT, +-- LVL1_VALID_NOTIMING_TRG_OUT => buf_LVL1_VALID_NOTIMING_TRG_OUT, +-- LVL1_INVALID_TRG_OUT => buf_LVL1_INVALID_TRG_OUT, +-- LVL1_MULTIPLE_TRG_OUT => int_multiple_trg, +-- LVL1_DELAY_OUT => int_lvl1_delay, +-- +-- LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, +-- LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, +-- +-- --Stat/Control +-- STATUS_OUT => stat_lvl1_handler, +-- TRG_ENABLE_IN => buf_REGIO_COMMON_CTRL_REG_OUT(95), +-- TRG_INVERT_IN => buf_REGIO_COMMON_CTRL_REG_OUT(93), +-- --Debug +-- DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT +-- ); +-- + + + THE_CMS_SYNC : signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => RESET, + D_IN(0) => TRG_TIMING_TRG_RECEIVED_IN, + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => reg_timing_trigger + ); + + + + proc_internal_trigger_number : process(CLK) begin if rising_edge(CLK) then @@ -789,6 +880,9 @@ begin proc_detect_trigger_receive : process(CLK) begin if rising_edge(CLK) then + last_reg_timing_trigger <= reg_timing_trigger; + trigger_timing_rising <= reg_timing_trigger and not last_reg_timing_trigger; + last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT; LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT; LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT; @@ -797,7 +891,7 @@ begin got_timing_trigger <= '0'; got_timingless_trigger <= '0'; timing_trigger_missing <= '0'; - elsif TRG_TIMING_TRG_RECEIVED_IN = '1' then + elsif trigger_timing_rising = '1' then --TRG_TIMING_TRG_RECEIVED_IN got_timing_trigger <= '1'; elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then got_timingless_trigger <= '1'; @@ -815,7 +909,7 @@ begin buf_LVL1_ERROR_PATTERN_IN(17) <= (not got_timing_trigger and not got_timingless_trigger) or LVL1_ERROR_PATTERN_IN(17); end process; - buf_LVL1_VALID_TIMING_TRG_OUT <= TRG_TIMING_TRG_RECEIVED_IN; + buf_LVL1_VALID_TIMING_TRG_OUT <= trigger_timing_rising; --TRG_TIMING_TRG_RECEIVED_IN; buf_LVL1_VALID_NOTIMING_TRG_OUT <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7); buf_LVL1_INVALID_TRG_OUT <= '0'; @@ -837,8 +931,10 @@ begin ------------------------------------------------- -- Connect Outputs ------------------------------------------------- + buf_LVL1_TRG_RELEASE_IN <= LVL1_TRG_RELEASE_IN; --changed back + LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_RECEIVED_OUT; --changed back + --LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_DATA_VALID_OUT; --changed back - LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_RECEIVED_OUT; LVL1_TRG_VALID_TIMING_OUT <= buf_LVL1_VALID_TIMING_TRG_OUT; LVL1_TRG_VALID_NOTIMING_OUT <= buf_LVL1_VALID_NOTIMING_TRG_OUT; LVL1_TRG_INVALID_OUT <= buf_LVL1_INVALID_TRG_OUT; diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index e3818d6..27193f0 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -29,6 +29,7 @@ entity trb_net16_endpoint_hades_full_handler is REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; CLOCK_FREQUENCY : integer range 1 to 200 := 100; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; --Configure data handler DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; @@ -123,7 +124,8 @@ entity trb_net16_endpoint_hades_full_handler is CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end entity; @@ -229,6 +231,7 @@ begin REGIO_HARDWARE_VERSION => REGIO_HARDWARE_VERSION, REGIO_USE_1WIRE_INTERFACE => REGIO_USE_1WIRE_INTERFACE, REGIO_USE_VAR_ENDPOINT_ID => REGIO_USE_VAR_ENDPOINT_ID, + TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW, CLOCK_FREQUENCY => CLOCK_FREQUENCY ) port map( @@ -311,7 +314,8 @@ begin CTRL_MPLEX => (others => '0'), IOBUF_CTRL_GEN => (others => '0'), STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => DEBUG_LVL1_HANDLER_OUT ); --------------------------------------------------------------------------- diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 0240528..507755b 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -925,7 +925,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; NUM_CTRL_REGS => 4, INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_0000307F_00000000" & + x"00000000_00000000_000050FF_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", USED_CTRL_REGS => (others => '1'), USED_CTRL_BITMASK => (others => '1'), @@ -1092,10 +1092,10 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_WRITE_ENABLE_OUT(6) => lsm_write, BUS_TIMEOUT_OUT(6) => open, BUS_DATA_IN(223 downto 192) => lsm_data, - BUS_DATAREADY_IN(5) => last_lsm_read, - BUS_WRITE_ACK_IN(5) => '0', - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_UNKNOWN_ADDR_IN(5) => lsm_write, + BUS_DATAREADY_IN(6) => last_lsm_read, + BUS_WRITE_ACK_IN(6) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => lsm_write, STAT_DEBUG => open ); diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 391e689..6edea80 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -865,6 +865,9 @@ begin if rising_edge(CLK) then if RESET = '1' then buf_COMMON_CTRL_REG_OUT(j) <= '0'; + if j = 95 then + buf_COMMON_CTRL_REG_OUT(j) <= '1'; + end if; elsif COMMON_REGISTERS_OUT_write_enable(i) = '1' then tmp := saved_Reg_high & saved_Reg_low; buf_COMMON_CTRL_REG_OUT(j) <= tmp(j-i*c_REGIO_REG_WIDTH); diff --git a/trb_net16_term_ibuf.vhd b/trb_net16_term_ibuf.vhd index 3cd79ef..eb3c7b8 100644 --- a/trb_net16_term_ibuf.vhd +++ b/trb_net16_term_ibuf.vhd @@ -72,8 +72,8 @@ architecture trb_net16_term_ibuf_arch of trb_net16_term_ibuf is signal got_eob_out, reg_eob_out: std_logic; signal sbuf_free, comb_next_read: std_logic; signal tmp_INT_DATAREADY_OUT: std_logic; - signal tmp_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal tmp_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); + signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR); signal current_error_state, next_error_state : ERROR_STATE; signal next_rec_buffer_size_out, current_rec_buffer_size_out : std_logic_vector(3 downto 0); diff --git a/trb_net16_trigger.vhd b/trb_net16_trigger.vhd index ab4e4cd..36b8b6c 100644 --- a/trb_net16_trigger.vhd +++ b/trb_net16_trigger.vhd @@ -25,11 +25,11 @@ entity trb_net16_trigger is INT_DATAREADY_OUT: out std_logic; INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; + INT_READ_IN: in std_logic := '0'; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_IN: in std_logic := '0'; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0) := (others => '0'); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0) := (others => '0'); INT_READ_OUT: out std_logic; -- Trigger information output @@ -45,21 +45,21 @@ end entity; architecture trb_net16_trigger_arch of trb_net16_trigger is - signal next_TRG_TYPE_OUT, reg_TRG_TYPE_OUT: std_logic_vector(3 downto 0); - signal next_TRG_NUMBER_OUT, reg_TRG_NUMBER_OUT: std_logic_vector(15 downto 0); - signal next_TRG_CODE_OUT, reg_TRG_CODE_OUT: std_logic_vector(7 downto 0); - signal next_TRG_INFORMATION_OUT, reg_TRG_INFORMATION_OUT: std_logic_vector(23 downto 0); - signal next_TRG_RECEIVED_OUT, reg_TRG_RECEIVED_OUT: std_logic; - signal buf_TRG_ERROR_PATTERN_IN: std_logic_vector(31 downto 0); + signal next_TRG_TYPE_OUT, reg_TRG_TYPE_OUT: std_logic_vector(3 downto 0) := (others => '0'); + signal next_TRG_NUMBER_OUT, reg_TRG_NUMBER_OUT: std_logic_vector(15 downto 0) := (others => '0'); + signal next_TRG_CODE_OUT, reg_TRG_CODE_OUT: std_logic_vector(7 downto 0) := (others => '0'); + signal next_TRG_INFORMATION_OUT, reg_TRG_INFORMATION_OUT: std_logic_vector(23 downto 0) := (others => '0'); + signal next_TRG_RECEIVED_OUT, reg_TRG_RECEIVED_OUT: std_logic := '0'; + signal buf_TRG_ERROR_PATTERN_IN: std_logic_vector(31 downto 0) := (others => '0'); - signal saved_packet_type : std_logic_vector(2 downto 0); + signal saved_packet_type : std_logic_vector(2 downto 0) := (others => '0'); - signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal send_trm, next_send_trm : std_logic; - signal buf_INT_DATAREADY_OUT, next_INT_DATAREADY_OUT : std_logic; - signal buf_INT_DATA_OUT, next_INT_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal next_seqnr, seqnr : std_logic_vector(7 downto 0); + signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); + signal send_trm, next_send_trm : std_logic := '0'; + signal buf_INT_DATAREADY_OUT, next_INT_DATAREADY_OUT : std_logic := '0'; + signal buf_INT_DATA_OUT, next_INT_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); + signal next_seqnr, seqnr : std_logic_vector(7 downto 0) := (others => '0'); begin diff --git a/trb_net_components.vhd b/trb_net_components.vhd index d73403e..4c9645b 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -343,6 +343,7 @@ end component trb_net16_med_scm_sfp_gbe; APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers --standard values for output registers @@ -459,7 +460,8 @@ end component trb_net16_med_scm_sfp_gbe; CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end component; @@ -483,6 +485,7 @@ end component trb_net16_med_scm_sfp_gbe; REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; CLOCK_FREQUENCY : integer range 1 to 200 := 100; --Configure data handler DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; @@ -578,7 +581,8 @@ end component trb_net16_med_scm_sfp_gbe; CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end component; @@ -1044,6 +1048,52 @@ end component trb_net16_med_scm_sfp_gbe; + component handler_lvl1 is + generic( + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES + ); + port( + RESET : in std_logic; + CLOCK : in std_logic; + --Timing Trigger + LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics + LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger + --LVL1_handler connection + LVL1_TRG_RECEIVED_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS + LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS + + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release + LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter + LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter + + --FEE logic / Data Handler + LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...) + LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected + LVL1_DELAY_OUT : out std_logic_vector(15 downto 0); + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE + LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE + + --Stat/Control + STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers + TRG_ENABLE_IN : in std_logic; -- trigger enable flag + TRG_INVERT_IN : in std_logic; -- trigger invert flag + --Debug + DEBUG_OUT : out std_logic_vector (15 downto 0) + ); + end component; + + + + component handler_trigger_and_data is generic( diff --git a/trb_net_sbuf.vhd b/trb_net_sbuf.vhd index 0624e0f..e3939bd 100644 --- a/trb_net_sbuf.vhd +++ b/trb_net_sbuf.vhd @@ -49,8 +49,8 @@ end trb_net_sbuf; architecture trb_net_sbuf_arch of trb_net_sbuf is - signal current_b1_buffer, next_b1_buffer : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - signal current_b2_buffer, next_b2_buffer : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + signal current_b1_buffer, next_b1_buffer : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => '0'); + signal current_b2_buffer, next_b2_buffer : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => '0'); signal next_next_READ_OUT, current_next_READ_OUT : std_logic; signal next_SYN_DATAREADY_OUT, current_SYN_DATAREADY_OUT : std_logic; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 7356a16..c694b5f 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -110,7 +110,7 @@ package trb_net_std is --common registers --maximum: 4, because of regio implementation - constant std_COMSTATREG : integer := 2; + constant std_COMSTATREG : integer := 4; constant std_COMCTRLREG : integer := 3; --needed address width for common registers constant std_COMneededwidth : integer := 2;