From: Jan Michel Date: Fri, 1 Apr 2016 08:44:18 +0000 (+0200) Subject: Committing missing changes from depc363 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=db70b28b557db4a271bce95252bd7b5696945c68;p=dirich.git Committing missing changes from depc363 --- diff --git a/dirich/compile.pl b/dirich/compile.pl index 8a19aa6..933ff60 120000 --- a/dirich/compile.pl +++ b/dirich/compile.pl @@ -1 +1 @@ -../../trb3sc/scripts/compile.pl \ No newline at end of file +../../trb3/scripts/compile.pl \ No newline at end of file diff --git a/dirich/config.vhd b/dirich/config.vhd index a16a010..39c7d80 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -11,15 +11,21 @@ package config is ------------------------------------------------------------------------------ --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 41; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, -- 3: same channel with stretcher - constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file - --ring buffer size: 32,64,96,128,dyn + constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 @@ -120,4 +126,4 @@ function generateIncludedFeatures return std_logic_vector is constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; -end package body; \ No newline at end of file +end package body; diff --git a/dirich/config_compile_gsi.pl b/dirich/config_compile_gsi.pl index e7f0dff..cc419be 100644 --- a/dirich/config_compile_gsi.pl +++ b/dirich/config_compile_gsi.pl @@ -13,6 +13,8 @@ synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_ nodelist_file => '../nodes_lxhadeb07.txt', pinout_file => 'dirich', +par_options => '../par.p2t', + include_TDC => 1, include_GBE => 0, diff --git a/dirich/diamond/dirich.ldf b/dirich/diamond/dirich.ldf index 42fd87b..ce80521 100644 --- a/dirich/diamond/dirich.ldf +++ b/dirich/diamond/dirich.ldf @@ -2,7 +2,7 @@ - + @@ -318,6 +318,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/dirich/dirich.prj b/dirich/dirich.prj index 02e46e3..bea3ecb 100644 --- a/dirich/dirich.prj +++ b/dirich/dirich.prj @@ -201,12 +201,12 @@ add_file -vhdl -lib work "tdc_release/TDC_record.vhd" add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" add_file -vhdl -lib work "tdc_release/up_counter.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" -add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg.vhd" -add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg.vhd" -add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" -add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg.vhd" -add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 94ff711..5cace1b 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -395,8 +395,8 @@ THE_PWM_GEN : entity work.pwm_generator -- For ToT Measurements gen_double : if DOUBLE_EDGE_TYPE = 2 generate Gen_Hit_In_Signals : for i in 1 to 16 generate - hit_in_i(i*2-1) <= INPUT(i-1); - hit_in_i(i*2) <= not INPUT(i-1); + hit_in_i(i*2-1) <= INPUT(i); + hit_in_i(i*2) <= not INPUT(i); end generate Gen_Hit_In_Signals; end generate; diff --git a/dirich/par.p2t b/dirich/par.p2t index f72683d..37870ba 100644 --- a/dirich/par.p2t +++ b/dirich/par.p2t @@ -1,21 +1,69 @@ -w --i 15 --l 5 --n 1 -y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. -s 12 --t 24 +-t 1 -c 1 -e 2 -#-g guidefile.ncd -#-m nodelist.txt -# -w -# -i 6 -# -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 +-i 15 +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: + + +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. # --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf index 012f2a5..f8cda3d 100644 --- a/pinout/dirich.lpf +++ b/pinout/dirich.lpf @@ -147,4 +147,4 @@ LOCATE COMP "TEST_LINE[12]" SITE "M1"; LOCATE COMP "TEST_LINE[13]" SITE "P4"; LOCATE COMP "TEST_LINE[14]" SITE "N1"; DEFINE PORT GROUP "TEST_group" "TEST*" ; -IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; \ No newline at end of file +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5;