From: Benedikt Gutsche Date: Wed, 10 Jan 2024 10:59:38 +0000 (+0100) Subject: added stuff to work X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=db9b3219bb095be90d652663e01a126993dc8598;p=trb5sc.git added stuff to work --- diff --git a/vldb/trb5sc_mimosis.prj b/vldb/trb5sc_mimosis.prj index df0bfb1..6c049dd 100644 --- a/vldb/trb5sc_mimosis.prj +++ b/vldb/trb5sc_mimosis.prj @@ -54,6 +54,7 @@ impl -active "workdir" add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + #Packages add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" @@ -70,7 +71,6 @@ add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" - #Fifos add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" @@ -214,6 +214,22 @@ add_file -vhdl -lib work "./code/InputStage.vhd" add_file -vhdl -lib work "./code/WordAlign.vhd" add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd" +#GBT Core +add_file -vhdl -lib work "./code/gbt_core.vhd" +add_file -vhdl -lib work "./code/GBT-SC/gbtsc_top.vhd" +add_file -vhdl -lib work "./code/GBT-SC/SCA/sca_deserializer.vhd" +add_file -vhdl -lib work "./code/GBT-SC/SCA/sca_pkg.vhd" +add_file -vhdl -lib work "./code/GBT-SC/SCA/sca_rx_fifo.vhd" +add_file -vhdl -lib work "./code/GBT-SC/SCA/sca_rx.vhd" +add_file -vhdl -lib work "./code/GBT-SC/SCA/sca_top.vhd" +add_file -vhdl -lib work "./code/GBT-SC/SCA/sca_tx.vhd" +add_file -vhdl -lib work "./code/GBT-SC/IC/ic_deserializer.vhd" +add_file -vhdl -lib work "./code/GBT-SC/IC/ic_rx_fifo.vhd" +add_file -vhdl -lib work "./code/GBT-SC/IC/ic_rx.vhd" +add_file -vhdl -lib work "./code/GBT-SC/IC/ic_top.vhd" +add_file -vhdl -lib work "./code/GBT-SC/IC/ic_tx.vhd" + + #GbE