From: Jan Michel Date: Wed, 6 Jul 2016 12:51:58 +0000 (+0200) Subject: Update dirich files X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=dbaa970c8a595eb092bda5378a112f087c8a3bff;p=dirich.git Update dirich files --- diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 6893cc9..f22becd 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -60,7 +60,7 @@ THE_PLL : entity work.pll_240_100 --PLL with 200 MHz input! ); gen_slow_clock : if USE_120_MHZ = 0 generate - RAW_CLK_OUT <= clock_240; + RAW_CLK_OUT <= clock_200; sys_clk_i <= clock_100; REF_CLK_OUT <= clock_200; end generate; @@ -93,7 +93,7 @@ THE_RESET_HANDLER : trb_net_reset_handler port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => clear_n_i, -- reset input (low active, async) - CLK_IN => clock_240, -- raw master clock, NOT from PLL/DLL! + CLK_IN => clock_200, -- raw master clock, NOT from PLL/DLL! SYSCLK_IN => sys_clk_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) diff --git a/code/pwm_generator.vhd b/code/pwm_generator.vhd index 463c0af..4ece0bc 100644 --- a/code/pwm_generator.vhd +++ b/code/pwm_generator.vhd @@ -12,7 +12,7 @@ entity pwm_generator is ); port( CLK : in std_logic; - + CLK_FAST : in std_logic; BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; TEMP_IN : in std_logic_vector(11 downto 0); @@ -42,6 +42,9 @@ signal flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); signal pwm_i : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); signal ci : integer range 0 to CHANNELS-1; +signal clock_enable : std_logic; +signal timer : unsigned(3 downto 0); + begin PROC_MEM : process @@ -83,19 +86,35 @@ GEN_REAL_VALUES : process begin set_tmp(ci) <= unsigned(signed(set(ci)) + compensate); ci <= ci + 1; - - temp_i <= TEMP_IN; - temp_calc_i <= signed(temp_i) * signed(set_compensate); - compensate <= temp_calc_i(27 downto 12); +-- +-- temp_i <= signed(TEMP_IN); +-- temp_calc_i <= signed(temp_i) * signed(set_compensate); +-- compensate <= temp_calc_i(27 downto 12); end process; +process begin + wait until rising_edge(CLK); + timer <= timer + 1; + if timer(2 downto 0) = "000" then + clock_enable <= '1'; + else + clock_enable <= '0'; + end if; +end process; + -gen_channels : for i in 0 to 15 generate +gen_channels : for i in 0 to CHANNELS-1 generate flag(i) <= cnt(i)(16); - last_flag(i) <= flag(i) when rising_edge(CLK); - pwm_i(i) <= (last_flag(i) xor flag(i)) when rising_edge(CLK); - cnt(i) <= cnt(i) + resize(set_tmp(i),17) when rising_edge(CLK); + + process begin + wait until rising_edge(CLK); + if clock_enable = '1' then + last_flag(i) <= flag(i); + pwm_i(i) <= (last_flag(i) xor flag(i)); + cnt(i) <= cnt(i) + resize(set_tmp(i),17); + end if; + end process; end generate; diff --git a/dirich/config.vhd b/dirich/config.vhd index 39c7d80..bca93e2 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -11,7 +11,7 @@ package config is ------------------------------------------------------------------------------ --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 2; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, @@ -27,8 +27,8 @@ package config is -- 14: Debug - single fine time and the ROM addresses for the two transitions -- 15: Debug - complete carry chain dump - constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N - constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -40,16 +40,14 @@ package config is constant INIT_ADDRESS : std_logic_vector := x"F3D1"; constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"51"; ---set to 0 for backplane serdes, set to 3 for front SFP serdes - - constant INCLUDE_UART : integer := c_NO; - constant INCLUDE_SPI : integer := c_YES; - constant INCLUDE_LCD : integer := c_NO; - constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_YES; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --300 slices --input monitor and trigger generation logic - constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; - constant INCLUDE_STATISTICS : integer := c_YES; + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_YES; --1300 slices, 1 RAM @32 constant TRIG_GEN_INPUT_NUM : integer := 32; constant TRIG_GEN_OUTPUT_NUM : integer := 2; constant MONITOR_INPUT_NUM : integer := 32; @@ -73,6 +71,8 @@ package config is x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", + x"8a", x"0a", + x"8b", x"0a", others => x"00"); ------------------------------------------------------------------------------ diff --git a/dirich/config_compile_frankfurt.pl b/dirich/config_compile_frankfurt.pl index 84f4911..9f01cff 100644 --- a/dirich/config_compile_frankfurt.pl +++ b/dirich/config_compile_frankfurt.pl @@ -7,12 +7,14 @@ Speedgrade => '8', TOPNAME => "dirich", lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.6_x64', +lattice_path => '/d/jspc29/lattice/diamond/3.7_x64', synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', -synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options", # synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", # synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", nodelist_file => 'nodelist_frankfurt.txt', +pinout_file => 'dirich', +par_options => '../par.p2t', #Include only necessary lpf files diff --git a/dirich/diamond/dirich.ldf b/dirich/diamond/dirich.ldf index ce80521..087c214 100644 --- a/dirich/diamond/dirich.ldf +++ b/dirich/diamond/dirich.ldf @@ -1,8 +1,8 @@ - + - - + + @@ -372,6 +372,24 @@ + + + + + + + + + + + + + + + + + + diff --git a/pinout/basic_constraints.lpf b/dirich/dirich.lpf similarity index 85% rename from pinout/basic_constraints.lpf rename to dirich/dirich.lpf index a3054a9..6769e9b 100644 --- a/pinout/basic_constraints.lpf +++ b/dirich/dirich.lpf @@ -8,7 +8,7 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# FREQUENCY PORT CLOCK_IN 200 MHz; -FREQUENCY PORT CLOCK_CAL 33 MHz; +FREQUENCY PORT CLOCK_CAL 200 MHz; @@ -26,3 +26,4 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; GSR_NET NET "GSR_N"; +LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; diff --git a/dirich/dirich.prj b/dirich/dirich.prj index bea3ecb..3817d7f 100644 --- a/dirich/dirich.prj +++ b/dirich/dirich.prj @@ -131,10 +131,12 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" -add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0_softlogic.v" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" +add_file -verilog -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0_softlogic.v" +add_file -vhdl -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0.vhd" +add_file -vhdl -lib work "diamond/pcs/pcs.vhd" + #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd deleted file mode 120000 index 146d3da..0000000 --- a/dirich/dirich.vhd +++ /dev/null @@ -1 +0,0 @@ -tdc_release/dirich.vhd \ No newline at end of file diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd new file mode 100644 index 0000000..b5379ad --- /dev/null +++ b/dirich/dirich.vhd @@ -0,0 +1,424 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity dirich is + port( + CLOCK_IN : in std_logic; --Main Oscillator + TRIG_IN : in std_logic; --Reference Time + CLOCK_CAL : in std_logic; --on-board calibration oscillator + + INPUT : in std_logic_vector(32 downto 1); + PWM : out std_logic_vector(32 downto 1); + + --Additional IO + SIG : inout std_logic_vector( 4 downto 1); + --1:master ready, 2: slave ready, 3-4 trigger, 5 reset + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + --ADC + ADC_SCLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + TEMP_LINE : inout std_logic; + + --Test Connectors + TEST_LINE : inout std_logic_vector(14 downto 1) + ); + + + attribute syn_useioff : boolean; +-- attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + attribute syn_useioff of INPUT : signal is false; + +end entity; + +architecture dirich_arch of dirich is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal link_stat_in, link_stat_out : std_logic; + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_clk_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal pwm_i : std_logic_vector(31 downto 0); + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + signal hdr_io : std_logic_vector(9 downto 0); + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(32 downto 1); + signal logic_analyser_i : std_logic_vector(16 downto 1); + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + + component usrmclk + port( + USRMCLKI : in std_ulogic; + USRMCLKTS : in std_ulogic + ); + end component; +attribute syn_noprune: boolean ; +attribute syn_noprune of USRMCLK: component is true; + + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLOCK_IN, + RESET_FROM_NET => med2int(0).stat_op(13), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => link_stat_in, + SD_LOS_IN => link_stat_in, + SD_TXDIS_OUT => link_stat_out, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + +SIG(2) <= '1' when link_stat_out = '1' else '0'; +link_stat_in <= SIG(1); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => EVENT_BUFFER_SIZE/2, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_IN, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => TEMP_LINE, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busthresh_rx, + BUS_RX(4) => bustdc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busthresh_tx, + BUS_TX(4) => bustdc_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => open, --FLASH_CS, + FLASH_CLK => flash_clk_i, --FLASH_CLK, + FLASH_IN => '0', --FLASH_OUT, + FLASH_OUT => open,--FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => open, + SPI_MOSI_OUT => open, + SPI_MISO_IN => open, + SPI_CLK_OUT => open, + --Header + HEADER_IO => hdr_io, + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => lcd_data, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => INPUT, + TRIG_GEN_INPUTS => INPUT, + TRIG_GEN_OUTPUTS => SIG(4 downto 3), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + +-- THE_FLASH_CLOCK : usrmclk +-- port map( +-- USRMCLKI => time_counter(23), +-- USRMCLKTS => '1' +-- ); +-- +-- FLASH_CLK <= time_counter(23); +-- FLASH_HOLD <= time_counter(27); +-- FLASH_WP <= time_counter(26); +-- FLASH_CS <= time_counter(25); +-- FLASH_IN <= time_counter(24); + +--------------------------------------------------------------------------- +-- PWM / Thresh +--------------------------------------------------------------------------- + +THE_PWM_GEN : entity work.pwm_generator + port map( + CLK => clk_sys, + CLK_FAST => CLOCK_IN, + BUS_RX => busthresh_rx, + BUS_TX => busthresh_tx, + TEMP_IN => timer.temperature, + PWM => pwm_i + ); + +PWM <= pwm_i; + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); + hdr_io(8) <= TEST_LINE(9); + TEST_LINE(10) <= hdr_io(9); + TEST_LINE(14 downto 11) <= time_counter(31 downto 28); + +--------------------------------------------------------------------------- +-- LCD Data to display +--------------------------------------------------------------------------- + lcd_data(15 downto 0) <= timer.network_address; + lcd_data(47 downto 16) <= timer.microsecond; + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)); + lcd_data(91 downto 80) <= timer.temperature; + lcd_data(95 downto 92) <= x"0"; + lcd_data(159 downto 96) <= timer.uid; + lcd_data(191 downto 160) <= debug_tools; + lcd_data(511 downto 192) <= (others => '0'); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_ORANGE <= '1' or led_off; + LED_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_YELLOW <= '1' or led_off; + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + +-- THE_TDC : entity work.TDC_record +-- generic map ( +-- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module +-- STATUS_REG_NR => 21, -- Number of status regs +-- DEBUG => c_YES, +-- SIMULATION => c_NO) +-- port map ( +-- RESET => reset_i, +-- CLK_TDC => CLOCK_IN, +-- CLK_READOUT => clk_sys, -- Clock for the readout +-- REFERENCE_TIME => TRIG_IN, -- Reference time input +-- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals +-- HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC +-- -- Trigger signals from handler +-- BUSRDO_RX => readout_rx, +-- BUSRDO_TX => readout_tx(0), +-- -- Slow control bus +-- BUS_RX => bustdc_rx, +-- BUS_TX => bustdc_tx, +-- -- Dubug signals +-- INFO_IN => timer, +-- LOGIC_ANALYSER_OUT => logic_analyser_i +-- ); +-- +-- -- For single edge measurements +-- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate +-- hit_in_i <= INPUT; +-- end generate; +-- +-- -- For ToT Measurements +-- gen_double : if DOUBLE_EDGE_TYPE = 2 generate +-- Gen_Hit_In_Signals : for i in 1 to 16 generate +-- hit_in_i(i*2-1) <= INPUT(i); +-- hit_in_i(i*2) <= not INPUT(i); +-- end generate Gen_Hit_In_Signals; +-- end generate; + +end architecture; + + + diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf index f8cda3d..9102479 100644 --- a/pinout/dirich.lpf +++ b/pinout/dirich.lpf @@ -86,7 +86,7 @@ LOCATE COMP "PWM[30]" SITE "A16"; LOCATE COMP "PWM[31]" SITE "E14"; LOCATE COMP "PWM[32]" SITE "E15"; DEFINE PORT GROUP "PWM_group" "PWM*" ; -IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; +IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS25 DRIVE=12 SLEWRATE=FAST BANK_VCCIO=2.5; LOCATE COMP "LED_GREEN" SITE "G16"; LOCATE COMP "LED_ORANGE" SITE "H16"; @@ -118,14 +118,18 @@ DEFINE PORT GROUP "SIG_group" "SIG*" ; IOBUF GROUP "SIG_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; -# LOCATE COMP "FLASH_CLK" SITE "U3"; +LOCATE COMP "FLASH_CLK" SITE "U1"; LOCATE COMP "FLASH_CS" SITE "R2"; LOCATE COMP "FLASH_IN" SITE "W2"; LOCATE COMP "FLASH_OUT" SITE "V2"; +LOCATE COMP "FLASH_HOLD" SITE "W1"; +LOCATE COMP "FLASH_WP" SITE "Y2"; IOBUF PORT "FLASH_CLK" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; IOBUF PORT "FLASH_IN" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; IOBUF PORT "FLASH_OUT" IO_TYPE=LVTTL33 BANK_VCCIO=3.3; IOBUF PORT "FLASH_CS" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_HOLD" IO_TYPE=LVTTL33 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_WP" IO_TYPE=LVTTL33 BANK_VCCIO=3.3; LOCATE COMP "TEMP_LINE" SITE "R1";