From: Peter Lemmens Date: Thu, 12 Mar 2015 13:59:52 +0000 (+0100) Subject: Trb3 over copper, soda over fiber. Automatic error reporting to slow control works. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=dc285d1347a646b2cf6e56f621840d68a9c0af2a;p=soda.git Trb3 over copper, soda over fiber. Automatic error reporting to slow control works. --- diff --git a/SODA_addressmap b/SODA_addressmap index 28b89ba..b37255d 100644 --- a/SODA_addressmap +++ b/SODA_addressmap @@ -12,15 +12,7 @@ BE01 super_burst_nr_S BE02 calib_register_S BE03 CTRL_STATUS_register_i -control(read & write): -CTRL_STATUS_register_i[3..0] : LEDs -CTRL_STATUS_register_i[8] : dead_channel -CTRL_STATUS_register_i[15] : reset errors -status(read-only): -CTRL_STATUS_register_i[17] : timeout-error -CTRL_STATUS_register_i[18] : downstream-error -CTRL_STATUS_register_i[31] : report error - +c SODA_CLIENT (0xF356) ++++++++++++++++++++ @@ -40,7 +32,36 @@ BE06 Debug_SOS_count BE07 Debug_CMD_count +Cu_TRB_SODA_HUB (0xF35B) +++++++++++++++++++++++++++ +WRITE_REG: + +BE00 soda_cmd_word_S +BE01 CTRL_STATUS_register_S(15 downto 0) channel1 +BE02 CTRL_STATUS_register_S(15 downto 0) channel2 +BE03 CTRL_STATUS_register_S(15 downto 0) channel3 +BE04 CTRL_STATUS_register_S(15 downto 0) channel4 +READ_REG: + +BE00 '0' & soda_cmd_word_S +BE01 '0' & superburst_nr_S +BE04 calib_register_S channel1 +BE05 calib_register_S channel2 +BE06 calib_register_S channel3 +BE07 calib_register_S channel4 +BE08 calib_register_S channel1 +BE09 calib_register_S channel2 +BE10 calib_register_S channel3 +BE11 calib_register_S channel4 + +control(read & write): +CTRL_STATUS_register_i[8] : dead_channel +CTRL_STATUS_register_i[15] : reset errors +status(read-only): +CTRL_STATUS_register_i[17] : timeout-error +CTRL_STATUS_register_i[18] : downstream-error +CTRL_STATUS_register_i[31] : report error DEBUG_STATUS(31) <= send_link_reset_i when rising_edge(SYSCLK); DEBUG_STATUS(30) <= '0'; diff --git a/code/soda_calibration_timer.vhd b/code/soda_calibration_timer.vhd index c6a2084..951aa53 100644 --- a/code/soda_calibration_timer.vhd +++ b/code/soda_calibration_timer.vhd @@ -22,6 +22,7 @@ entity soda_calibration_timer is --Internal Connection START_CALIBRATION : in std_logic := '0'; END_CALIBRATION : in std_logic := '0'; + CALIBRATION_RUNNING : out std_logic := '0'; -- VALID_OUT : out std_logic := '0'; -- CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0'); TIMEOUT_ERROR : out std_logic := '0' @@ -36,12 +37,14 @@ architecture Behavioral of soda_calibration_timer is signal calibration_timer_S : std_logic_vector(15 downto 0) := (others => '0'); -- from super-burst-nr-generator begin + + CALIBRATION_RUNNING <= calibration_running_S; packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S) begin if rising_edge(SODACLK) then if (RESET='1') then - VALID_OUT <= '0'; + VALID_OUT <= '0'; CALIB_TIME_OUT <= (others => '0'); calibration_running_S <= '0'; calibration_timer_S <= (others => '0'); diff --git a/code/soda_components.vhd b/code/soda_components.vhd index 3b4a267..594b699 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -86,7 +86,7 @@ package soda_components is SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - TIME_CAL_OUT : out std_logic := '0'; -- + SEND_TIME_CAL_OUT : out std_logic := '0'; -- TX_DLM_PREVIEW_OUT : out std_logic := '0'; -- TX_DLM_OUT : out std_logic := '0'; -- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') @@ -284,6 +284,7 @@ package soda_components is --Internal Connection START_CALIBRATION : in std_logic := '0'; END_CALIBRATION : in std_logic := '0'; + CALIBRATION_RUNNING : out std_logic := '0'; -- VALID_OUT : out std_logic := '0'; -- CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0'); TIMEOUT_ERROR : out std_logic := '0' diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd index 8afb431..b20d938 100644 --- a/code/soda_hub.vhd +++ b/code/soda_hub.vhd @@ -74,12 +74,15 @@ architecture Behavioral of soda_hub is signal recv_start_calibration_S : std_logic := '0'; signal send_start_calibration_S : t_HUB_BIT_ARRAY := (others => '0'); signal start_calibration_S : t_HUB_BIT_ARRAY := (others => '0'); + signal stop_calibration_S : t_HUB_BIT_ARRAY := (others => '0'); signal calib_data_valid_S : t_HUB_BIT_ARRAY := (others => '0'); signal calibration_time_S : t_HUB_WORD_ARRAY := (others => (others => '0')); signal calib_register_s : t_HUB_LWORD_ARRAY := (others => (others => '0')); - signal reply_timeout_error_S : t_HUB_BIT_ARRAY := (others => '0'); - signal channel_timeout_status_S : t_HUB_BIT_ARRAY := (others => '0'); - signal downstream_error_S : t_HUB_BIT_ARRAY := (others => '0'); + signal calib_timeout_error_S : t_HUB_BIT_ARRAY; + signal calibration_running_S : t_HUB_BIT_ARRAY; + signal channel_timeout_status_S : t_HUB_BIT_ARRAY; + signal report_error_S : t_HUB_BIT_ARRAY; + signal downstream_error_S : t_HUB_BIT_ARRAY; signal dead_channel_S : t_HUB_BIT_ARRAY := (others => '0'); @@ -144,135 +147,96 @@ begin channel :for i in c_HUB_CHILDREN-1 downto 0 generate - --X_clk_domain : process(TX_SODACLK(i)) - --begin - --if rising_edge(TX_SODACLK(i)) then - --if RESET='1' then - --TXsoda_cmd_valid_S(i) <= '0'; - --TXstart_of_superburst_S(i) <= '0'; - --TXsoda_cmd_word_S(i) <= (others => '0'); - --TXsuper_burst_nr_S(i) <= (others => '0'); - --else --- TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; --- TXstart_of_superburst_S(i) <= start_of_superburst_S; --- TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; --- TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; + --X_clk_domain : process(TX_SODACLK(i)) + --begin + --if rising_edge(TX_SODACLK(i)) then + --if RESET='1' then + --TXsoda_cmd_valid_S(i) <= '0'; + --TXstart_of_superburst_S(i) <= '0'; + --TXsoda_cmd_word_S(i) <= (others => '0'); + --TXsuper_burst_nr_S(i) <= (others => '0'); + --else + -- TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; + -- TXstart_of_superburst_S(i) <= start_of_superburst_S; + -- TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; + -- TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; + --end if; --end if; - --end if; - --end process; - - - - start_calibration_S(i) <= send_start_calibration_S(i); + --end process; + + + + start_calibration_S(i) <= send_start_calibration_S(i); - packet_builder : soda_packet_builder + packet_builder : soda_packet_builder + port map( + SODACLK => SODACLK, + RESET => RESET, + --Internal Connection + LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ? + SODA_CYCLE_IN => '1', -- 40MHz cycle is only required to sync superbursts at the source PL! 24022015 + SODA_CMD_STROBE_IN => trb_cmd_strobe_S, --soda_cmd_valid_S, --TXsoda_cmd_valid_S(i), + START_OF_SUPERBURST => start_of_superburst_S, --TXstart_of_superburst_S(i), + SUPER_BURST_NR_IN => super_burst_nr_S, --TXsuper_burst_nr_S(i)(30 downto 0), + SODA_CMD_WORD_IN => trb_cmd_word_S, --soda_cmd_word_S, --TXsoda_cmd_word_S(i)(30 downto 0), + EXPECTED_REPLY_OUT => expected_reply_S(i), + SEND_TIME_CAL_OUT => send_start_calibration_S(i), + TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i), + TX_DLM_OUT => TXDN_DLM_OUT(i), + TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i) + ); + + hub_reply_handler : soda_reply_handler + port map( + SODACLK => SODACLK, + RESET => RESET, + CLEAR => '0', + CLK_EN => '1', + --Internal Connection + -- LAST_PACKET => last_packet_sent_S, + EXPECTED_REPLY_IN => expected_reply_S(i), + RX_DLM_IN => RXDN_DLM_IN(i), + RX_DLM_WORD_IN => RXDN_DLM_WORD_IN(i), + REPLY_VALID_OUT => reply_data_valid_S(i), + REPLY_OK_OUT => reply_OK_S(i) + ); + + hub_calibration_timer : soda_calibration_timer port map( SODACLK => SODACLK, - RESET => RESET, + RESET => RESET, + CLEAR => '0', + CLK_EN => '1', --Internal Connection - LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ? - SODA_CYCLE_IN => '1', -- 40MHz cycle is only required to sync superbursts at the source PL! 24022015 - SODA_CMD_STROBE_IN => soda_cmd_valid_S, --TXsoda_cmd_valid_S(i), - START_OF_SUPERBURST => start_of_superburst_S, --TXstart_of_superburst_S(i), - SUPER_BURST_NR_IN => super_burst_nr_S, --TXsuper_burst_nr_S(i)(30 downto 0), - SODA_CMD_WORD_IN => soda_cmd_word_S, --TXsoda_cmd_word_S(i)(30 downto 0), - EXPECTED_REPLY_OUT => expected_reply_S(i), - TIME_CAL_OUT => send_start_calibration_S(i), - TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i), - TX_DLM_OUT => TXDN_DLM_OUT(i), - TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i) + START_CALIBRATION => start_calibration_S(i), + END_CALIBRATION => stop_calibration_S(i), + CALIBRATION_RUNNING => calibration_running_S(i), + VALID_OUT => calib_data_valid_S(i), + CALIB_TIME_OUT => calibration_time_S(i), + TIMEOUT_ERROR => calib_timeout_error_S(i) ); - hub_reply_handler : soda_reply_handler - port map( - SODACLK => SODACLK, - RESET => RESET, - CLEAR => '0', - CLK_EN => '1', - --Internal Connection --- LAST_PACKET => last_packet_sent_S, - EXPECTED_REPLY_IN => expected_reply_S(i), - RX_DLM_IN => RXDN_DLM_IN(i), - RX_DLM_WORD_IN => RXDN_DLM_WORD_IN(i), - REPLY_VALID_OUT => reply_data_valid_S(i), - REPLY_OK_OUT => reply_OK_S(i) - ); - - hub_calibration_timer : soda_calibration_timer - port map( - SODACLK => SODACLK, - RESET => RESET, - CLEAR => '0', - CLK_EN => '1', - --Internal Connection - START_CALIBRATION => start_calibration_S(i), - END_CALIBRATION => reply_data_valid_S(i), - VALID_OUT => calib_data_valid_S(i), - CALIB_TIME_OUT => calibration_time_S(i), - TIMEOUT_ERROR => reply_timeout_error_S(i) - ); + stop_calibration_S(i) <= '1' when ((calibration_running_S(i)='1') and ((reply_data_valid_S(i) = '1') or (calib_timeout_error_S(i)='1'))) else '0'; + channel_timeout_status_S(i) <= '1' when ((calibration_running_S(i)='0') and (calib_timeout_error_S(i)='1')) else '0'; + downstream_error_S(i) <= '1' when ((reply_data_valid_S(i) = '1') and (reply_OK_S(i) = '0')) else '0'; + report_error_S(i) <= '1' when ((dead_channel_S(i) = '0') and ((downstream_error_S(i)='1') or (channel_timeout_status_S(i)='1'))) else '0'; - sodahub_calib_timeout_proc : process(SYSCLK) -- converting to sysclk domain - begin - if rising_edge(SYSCLK) then - if( RESET = '1' ) then - calib_register_S(i) <= (others => '0'); - channel_timeout_status_S(i) <= '0'; - downstream_error_S(i) <= '0'; - CTRL_STATUS_register_S(i)(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit - CTRL_STATUS_register_S(i)(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit - CTRL_STATUS_register_S(i)(31) <= '0'; -- reset REPORT_ERROR status-bit - elsif (calib_data_valid_S(i) = '1') then -- calibration finished in time - calib_register_S(i) <= x"0000" & calibration_time_S(i); - channel_timeout_status_S(i) <= '0'; - elsif (reply_data_valid_S(i) = '1') then -- the reply was correct - channel_timeout_status_S(i) <= '0'; - if (reply_OK_S(i) = '1') then - downstream_error_S(i) <= '0'; - elsif (dead_channel_S(i) = '0') then - downstream_error_S(i) <= '1'; - CTRL_STATUS_register_S(i)(16) <= '1'; -- set DOWNSTREAM_ERROR status-bit - CTRL_STATUS_register_S(i)(31) <= '1'; -- set REPORT_ERROR status-bit + sodahub_calib_timeout_proc : process(SYSCLK) -- converting to sysclk domain + begin + if rising_edge(SYSCLK) then + if( RESET = '1' ) then + CTRL_STATUS_register_S(i)(31 downto 16) <= (others => '0'); -- reset REPORT_ERROR status-bit + calib_register_S(i) <= (others => '0'); -- reset REPORT_ERROR status-bit + else + CTRL_STATUS_register_S(i)(16) <= downstream_error_S(i); -- reset DOWNSTREAM_ERROR status-bit + CTRL_STATUS_register_S(i)(17) <= channel_timeout_status_S(i); -- reset CALIBRATION_TIMEOUT_ERROR status-bit + CTRL_STATUS_register_S(i)(31) <= report_error_S(i); -- reset REPORT_ERROR status-bit + if (reply_data_valid_S(i) = '1') then -- calibration time has ended and there is a reply + calib_register_S(i) <= x"0000" & calibration_time_S(i); -- store the elapsed time + end if; end if; - elsif ((reply_timeout_error_S(i) = '1') and (reply_OK_S(i) = '1')) then - channel_timeout_status_S(i) <= '1'; - CTRL_STATUS_register_S(i)(17) <= '1'; -- set CALIBRATION_TIMEOUT_ERROR status-bit - CTRL_STATUS_register_S(i)(31) <= '1'; -- set REPORT_ERROR status-bit - elsif (CTRL_STATUS_register_S(i)(15) = '1') then -- check if slowcontrol wants to reset errors - CTRL_STATUS_register_S(i)(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit - CTRL_STATUS_register_S(i)(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit - CTRL_STATUS_register_S(i)(31) <= '0'; -- reset REPORT_ERROR status-bit end if; - end if; - end process; - --- hub_store_calib_proc : process(SYSCLK) --- begin --- if rising_edge(SYSCLK) then --- if( RESET = '1' ) then --- calib_register_S(i) <= (others => '0'); --- else --- calib_register_S(i)(15 downto 0) <= calibration_time_S(i); --- end if; --- end if; --- end process; - - ----------------------------------------------------------- - -- Reply status report -- - ----------------------------------------------------------- --- reply_report_proc : process(SYSCLK) --- begin --- if rising_edge(SYSCLK) then --- if( RESET = '1' ) then --- channel_status_S(i) <= '0'; --- elsif (reply_data_valid_S(i)='1') then --- channel_status_S(i) <= reply_OK_S(i) or dead_channels_S(i); --- else --- channel_status_S(i) <= '0'; --- end if; --- end if; --- --- end process; + end process; end generate; @@ -410,8 +374,8 @@ end process TRANSFORM; dead_channel_S(0) <= CTRL_STATUS_register_S(0)(8); -- slow-control can declare a channel dead dead_channel_S(1) <= CTRL_STATUS_register_S(1)(8); -- slow-control can declare a channel dead - dead_channel_S(2) <= CTRL_STATUS_register_S(2)(8); -- slow-control can declare a channel dead - dead_channel_S(3) <= CTRL_STATUS_register_S(3)(8); -- slow-control can declare a channel dead + dead_channel_S(2) <= CTRL_STATUS_register_S(2)(8); -- slow-control can declare a channel dead + dead_channel_S(3) <= CTRL_STATUS_register_S(3)(8); -- slow-control can declare a channel dead -- register read THE_READ_REG_PROC: process( SYSCLK ) diff --git a/code/soda_packet_builder.vhd b/code/soda_packet_builder.vhd index 641efe5..1b7de86 100644 --- a/code/soda_packet_builder.vhd +++ b/code/soda_packet_builder.vhd @@ -22,7 +22,7 @@ entity soda_packet_builder is SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - TIME_CAL_OUT : out std_logic := '0'; + SEND_TIME_CAL_OUT : out std_logic := '0'; TX_DLM_PREVIEW_OUT : out std_logic := '0'; -- TX_DLM_OUT : out std_logic := '0'; -- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0') @@ -149,7 +149,7 @@ begin -- end if; -- else -- build_packet_state_S <= c_IDLE; --- TIME_CAL_OUT <= '0'; +-- SEND_TIME_CAL_OUT <= '0'; -- soda_pkt_valid_S <= '0'; -- soda_pkt_word_S <= (others=>'0'); -- end if; @@ -181,7 +181,7 @@ begin else build_packet_bits_S <= x"00"; build_packet_state_S <= c_IDLE; - TIME_CAL_OUT <= '0'; + SEND_TIME_CAL_OUT <= '0'; reg1_soda_pkt_valid_S <= '0'; soda_pkt_word_S <= (others=>'0'); end if; @@ -276,13 +276,13 @@ begin build_packet_state_S <= c_CMD2; soda_dlm_preview_S <= '1'; reg1_soda_pkt_valid_S <= '0'; - TIME_CAL_OUT <= soda_cmd_word_S(30); + SEND_TIME_CAL_OUT <= soda_cmd_word_S(30); when c_CMD2 => build_packet_bits_S <= x"23"; build_packet_state_S <= c_CMD3; reg1_soda_pkt_valid_S <= '1'; soda_pkt_word_S <= soda_cmd_word_S(23 downto 16); - TIME_CAL_OUT <= '0'; + SEND_TIME_CAL_OUT <= '0'; when c_CMD3 => build_packet_bits_S <= x"24"; build_packet_state_S <= c_CMD4; diff --git a/code/soda_reply_handler.vhd b/code/soda_reply_handler.vhd index b96b4ed..b4c3094 100644 --- a/code/soda_reply_handler.vhd +++ b/code/soda_reply_handler.vhd @@ -34,36 +34,37 @@ begin begin if rising_edge(SODACLK) then if (RESET='1') then - REPLY_VALID_OUT <= '0'; - REPLY_OK_OUT <= '0'; - reply_recv_state_S <= c_IDLE; + REPLY_VALID_OUT <= '0'; + REPLY_OK_OUT <= '0'; + reply_recv_state_S <= c_IDLE; else - REPLY_VALID_OUT <= '0'; + REPLY_VALID_OUT <= '0'; case reply_recv_state_S is when c_IDLE => if (RX_DLM_IN='1') then - reply_recv_state_S <= c_REPLY; - REPLY_VALID_OUT <= '1'; + reply_recv_state_S <= c_REPLY; + REPLY_VALID_OUT <= '1'; if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then - REPLY_OK_OUT <= '1'; + REPLY_OK_OUT <= '1'; else - REPLY_OK_OUT <= '0'; - end if; + REPLY_OK_OUT <= '0'; + end if; end if; when c_REPLY => + REPLY_VALID_OUT <= '0'; + REPLY_OK_OUT <= '0'; if (RX_DLM_IN='0') then - REPLY_VALID_OUT <= '1'; - reply_recv_state_S <= c_IDLE; + reply_recv_state_S <= c_IDLE; else - reply_recv_state_S <= c_ERROR; + reply_recv_state_S <= c_ERROR; end if; when c_ERROR => - reply_recv_state_S <= c_IDLE; - REPLY_OK_OUT <= '0'; - REPLY_OK_OUT <= '0'; + reply_recv_state_S <= c_IDLE; + REPLY_OK_OUT <= '0'; + REPLY_OK_OUT <= '0'; when others => - reply_recv_state_S <= c_IDLE; - REPLY_OK_OUT <= '0'; + reply_recv_state_S <= c_IDLE; + REPLY_OK_OUT <= '0'; end case; end if; end if; diff --git a/ctsh.ldf b/ctsh.ldf index 649498b..e5c10de 100644 --- a/ctsh.ldf +++ b/ctsh.ldf @@ -2,7 +2,7 @@ - + diff --git a/ctsh.lpf b/ctsh.lpf index 0cadf6a..d9815bd 100644 --- a/ctsh.lpf +++ b/ctsh.lpf @@ -29,63 +29,63 @@ LOCATE COMP "FPGA5_COMM_10" SITE "V10"; LOCATE COMP "FPGA5_COMM_11" SITE "W10"; DEFINE PORT GROUP "FPGA_group" "FPGA*" ; IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -LOCATE COMP "TEST_LINE[0]" SITE "A5" ; -LOCATE COMP "TEST_LINE[1]" SITE "A6" ; -LOCATE COMP "TEST_LINE[2]" SITE "G8" ; -LOCATE COMP "TEST_LINE[3]" SITE "F9" ; -LOCATE COMP "TEST_LINE[4]" SITE "D9" ; -LOCATE COMP "TEST_LINE[5]" SITE "D10" ; -LOCATE COMP "TEST_LINE[6]" SITE "F10" ; -LOCATE COMP "TEST_LINE[7]" SITE "E10" ; -LOCATE COMP "TEST_LINE[8]" SITE "A8" ; -LOCATE COMP "TEST_LINE[9]" SITE "B8" ; -LOCATE COMP "TEST_LINE[10]" SITE "G10" ; -LOCATE COMP "TEST_LINE[11]" SITE "G9" ; -LOCATE COMP "TEST_LINE[12]" SITE "C9" ; -LOCATE COMP "TEST_LINE[13]" SITE "C10" ; -LOCATE COMP "TEST_LINE[14]" SITE "H10" ; -LOCATE COMP "TEST_LINE[15]" SITE "H11" ; +LOCATE COMP "TEST_LINE_0" SITE "A5" ; +LOCATE COMP "TEST_LINE_1" SITE "A6" ; +LOCATE COMP "TEST_LINE_2" SITE "G8" ; +LOCATE COMP "TEST_LINE_3" SITE "F9" ; +LOCATE COMP "TEST_LINE_4" SITE "D9" ; +LOCATE COMP "TEST_LINE_5" SITE "D10" ; +LOCATE COMP "TEST_LINE_6" SITE "F10" ; +LOCATE COMP "TEST_LINE_7" SITE "E10" ; +LOCATE COMP "TEST_LINE_8" SITE "A8" ; +LOCATE COMP "TEST_LINE_9" SITE "B8" ; +LOCATE COMP "TEST_LINE_10" SITE "G10" ; +LOCATE COMP "TEST_LINE_11" SITE "G9" ; +LOCATE COMP "TEST_LINE_12" SITE "C9" ; +LOCATE COMP "TEST_LINE_13" SITE "C10" ; +LOCATE COMP "TEST_LINE_14" SITE "H10" ; +LOCATE COMP "TEST_LINE_15" SITE "H11" ; DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; ################################################################# # Connection to AddOn ################################################################# -LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 -LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 -LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 -LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 -LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 -LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 -LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 -LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 -LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 -LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 -LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 -LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 -LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 -LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 -LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 -LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 -LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 -LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 -LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 -LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 -LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 -LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 -LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 -LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 -LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 -LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 -LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 -LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 -LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 -LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 -LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 -LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 -LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 -LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 -LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 +LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1 +LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3 +LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5 +LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7 +LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15 +LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17 +LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21 +LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23 +LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25 +LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27 +LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35 +LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 +LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2 +LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4 +LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6 +LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8 +LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18 +LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22 +LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24 +LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26 +LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28 +LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36 +LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38 +LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169 +LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171 +LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173 +LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175 +LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183 +LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185 +LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170 +LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172 +LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174 +LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176 +LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184 +LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186 DEFINE PORT GROUP "SFP_group" "SFP*" ; IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; ################################################################# @@ -117,10 +117,10 @@ IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; LOCATE COMP "TEMPSENS" SITE "A13" ; IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; #coding of FPGA number -LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; -LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; -IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "CODE_LINE_1" SITE "AA20" ; +LOCATE COMP "CODE_LINE_0" SITE "Y21" ; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; #terminated differential pair to pads LOCATE COMP "SUPPL" SITE "C14" ; #IOBUF PORT "SUPPL" IO_TYPE=LVDS25; diff --git a/soda_hub/serdes_sync_upstream.txt b/soda_hub/serdes_sync_upstream.txt index a057cb3..9f2bf0d 100644 --- a/soda_hub/serdes_sync_upstream.txt +++ b/soda_hub/serdes_sync_upstream.txt @@ -44,7 +44,7 @@ CH3_COMMA_M "1111111100" CH3_RXWA "ENABLED" CH3_ILSM "ENABLED" CH3_CTC "DISABLED" -CH3_CC_MATCH4 "0100011100" +CH3_CC_MATCH4 "0000000000" CH3_CC_MATCH_MODE "1" CH3_CC_MIN_IPG "3" CCHMARK "9"