From: Michael Boehmer Date: Mon, 13 Dec 2021 14:18:58 +0000 (+0100) Subject: playing with probes X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=dcac0187dcee808510a434574168beeeca881a6f;p=trbnet.git playing with probes --- diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 1fac808..53621cd 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -257,7 +257,8 @@ begin ------------------------------------------------- -- Serdes ------------------------------------------------- - gen_pcs3: if SERDES_NUM = 3 generate -- needed for LPF constraints, should be changed +-- include this for certain designs (placement!) +-- gen_pcs3: if SERDES_NUM = 3 generate -- needed for LPF constraints, should be changed THE_SERDES : entity work.serdes_sync_all_RS port map( hdinp_ch0 => hdinp(0), @@ -402,7 +403,7 @@ begin serdes_rst_qd_c => '0', -- was wrong tx_sync_qd_c => SYNC_TX_PLL_IN ); - end generate; +-- end generate; gen_control : for i in 0 to 3 generate gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate @@ -517,13 +518,13 @@ end generate; STAT_DEBUG(7 downto 4) <= clk_tx_full(3 downto 0); STAT_DEBUG(63 downto 8) <= (others => '0'); --- DEBUG_OUT <= debug_i(3*32+31 downto 3*32); - DEBUG_OUT(11 downto 0) <= debug_i(3*32+11 downto 3*32); - DEBUG_OUT(12) <= debug_tx_control_i(3*32+4); - DEBUG_OUT(13) <= debug_tx_control_i(3*32+5); - DEBUG_OUT(14) <= debug_tx_control_i(3*32+30); - DEBUG_OUT(15) <= debug_tx_control_i(3*32+31); - DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16); + DEBUG_OUT <= debug_i(3*32+31 downto 3*32); +-- DEBUG_OUT(11 downto 0) <= debug_i(3*32+11 downto 3*32); +-- DEBUG_OUT(12) <= debug_i(3*32+12); --debug_tx_control_i(3*32+4); +-- DEBUG_OUT(13) <= debug_i(3*32+13); --debug_tx_control_i(3*32+5); +-- DEBUG_OUT(14) <= debug_i(3*32+14); --debug_tx_control_i(3*32+30); +-- DEBUG_OUT(15) <= debug_i(3*32+15); --debug_tx_control_i(3*32+31); +-- DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16); end architecture; diff --git a/media_interfaces/sync/main_tx_reset_RS.vhd b/media_interfaces/sync/main_tx_reset_RS.vhd index 83d119c..8f568fa 100644 --- a/media_interfaces/sync/main_tx_reset_RS.vhd +++ b/media_interfaces/sync/main_tx_reset_RS.vhd @@ -36,7 +36,6 @@ architecture main_tx_reset_RS_arch of main_tx_reset_RS is signal NEXT_STATE : statetype; -- next state of lsm signal tx_pcs_rst_ch_c_int : std_logic; - signal rst_qd_c_int : std_logic; signal sync_tx_quad_int : std_logic; signal link_tx_ready_int : std_logic; signal sync_tx_quad_trans : std_logic; @@ -141,6 +140,7 @@ begin STATE_OUT <= x"3"; tx_pcs_rst_ch_c_int <= '1'; reset_timer <= '1'; + sync_tx_quad_int <= '1'; NEXT_STATE <= SYNC_DONE; when SYNC_DONE => diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index c738793..fc1dd56 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -80,7 +80,6 @@ architecture med_sync_control_arch of med_sync_control_RS is signal reset_i : std_logic; signal link_rx_ready_i : std_logic; - signal link_rx_ready_qsys : std_logic; signal link_half_done_i : std_logic; signal link_full_done_i : std_logic; @@ -94,6 +93,25 @@ architecture med_sync_control_arch of med_sync_control_RS is signal is_wap_zero_i : std_logic; signal debug_tx_control_i : std_logic_vector(31 downto 0); + signal rx_lsm_state : std_logic_vector(3 downto 0); + + signal link_rx_ready_qsys : std_logic; + signal link_tx_ready_qsys : std_logic; + signal link_status : std_logic_vector(3 downto 0); + signal link_status_qsys : std_logic_vector(3 downto 0); + +-- attribute syn_keep : boolean; +-- attribute syn_preserve : boolean; +-- attribute syn_keep of rx_lsm_state : signal is true; +-- attribute syn_preserve of rx_lsm_state : signal is true; +-- attribute syn_keep of link_half_done_i : signal is true; +-- attribute syn_preserve of link_half_done_i : signal is true; +-- attribute syn_keep of link_full_done_i : signal is true; +-- attribute syn_preserve of link_full_done_i : signal is true; +-- attribute syn_keep of word_sync_rx_i : signal is true; +-- attribute syn_preserve of word_sync_rx_i : signal is true; +-- attribute syn_keep of word_sync_tx_i : signal is true; +-- attribute syn_preserve of word_sync_tx_i : signal is true; begin @@ -171,27 +189,27 @@ begin CLK_RXI => CLK_RXI, CLK_SYS => CLK_SYS, RESET => reset_i, - + -- RX_DATA_OUT => media_med2int_i.data, RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, RX_WRITE_OUT => media_med2int_i.dataready, - + -- RX_DATA_IN => RX_DATA_IN, RX_K_IN => RX_K_IN, - + -- WORD_SYNC_OUT => word_sync_rx_i, - + -- RX_DLM_OUT => RX_DLM_OUT, RX_DLM_WORD_OUT => RX_DLM_WORD_OUT, - + -- RX_RST_OUT => RX_RST_OUT, RX_RST_WORD_OUT => RX_RST_WORD_OUT, - + -- LINK_RX_READY_IN => link_rx_ready_i, LINK_TX_READY_IN => LINK_TX_READY_IN, LINK_HALF_DONE_IN => link_half_done_i, LINK_FULL_DONE_IN => link_full_done_i, - + -- DEBUG_OUT => DEBUG_RX_CONTROL, STAT_REG_OUT => STAT_RX_CONTROL ); @@ -204,12 +222,12 @@ begin RX_DATA_IN => RX_DATA_IN, LINK_HALF_DONE_OUT => link_half_done_i, LINK_FULL_DONE_OUT => link_full_done_i, - STATE_OUT => open + STATE_OUT => rx_lsm_state --open ); -- clocks for media interface - media_med2int_i.clk_half <= CLK_RXHALF; - media_med2int_i.clk_full <= CLK_RXI; + media_med2int_i.clk_half <= CLK_RXHALF; -- goes to clock and reset handler + media_med2int_i.clk_full <= CLK_RXI; -- goes to clock and reset handler ------------------------------------------------- -- TX Data @@ -292,30 +310,46 @@ begin media_med2int_i.stat_op(11) <= led_tx; media_med2int_i.stat_op(10) <= led_rx or last_led_rx; media_med2int_i.stat_op(9) <= '0'; --led_ok - media_med2int_i.stat_op(8 downto 5) <= (others => '0'); --- media_med2int_i.stat_op(5) <= link_tx_ready_i; - media_med2int_i.stat_op(4) <= link_rx_ready_i; - media_med2int_i.stat_op(3 downto 0) <= x"0" when link_half_done_i = '1' and link_full_done_i = '1' - else x"7"; + media_med2int_i.stat_op(8 downto 6) <= (others => '0'); + media_med2int_i.stat_op(5) <= link_tx_ready_qsys; + media_med2int_i.stat_op(4) <= link_rx_ready_qsys; + media_med2int_i.stat_op(3 downto 0) <= link_status_qsys; + + link_status <= x"0" when ((link_half_done_i = '1') and (link_full_done_i = '1')) + else x"7"; + + SYNC_MEDIA_SIGS : entity work.signal_sync + generic map( + WIDTH => 6, + DEPTH => 3 + ) + port map( + RESET => '0', + CLK0 => CLK_SYS, + CLK1 => CLK_SYS, + D_IN(5) => LINK_TX_READY_IN, + D_IN(4) => link_rx_ready_i, + D_IN(3 downto 0) => link_status, + D_OUT(5) => link_tx_ready_qsys, + D_OUT(4) => link_rx_ready_qsys, + D_OUT(3 downto 0) => link_status_qsys + ); -- TEST_LINE signals - DEBUG_OUT(3 downto 0) <= rx_fsm_state when rising_edge(CLK_REF); - DEBUG_OUT(4) <= RX_LOS_IN when rising_edge(CLK_REF); - DEBUG_OUT(5) <= RX_CDR_LOL_IN when rising_edge(CLK_REF); - DEBUG_OUT(6) <= TX_PLL_LOL_IN when rising_edge(CLK_REF); - DEBUG_OUT(7) <= LINK_TX_READY_IN when rising_edge(CLK_REF); - DEBUG_OUT(8) <= link_rx_ready_i when rising_edge(CLK_REF); - DEBUG_OUT(9) <= is_wap_zero_i when rising_edge(CLK_REF); - DEBUG_OUT(10) <= link_half_done_i when rising_edge(CLK_REF); - DEBUG_OUT(11) <= link_full_done_i when rising_edge(CLK_REF); - DEBUG_OUT(12) <= '0'; - DEBUG_OUT(13) <= '0'; - DEBUG_OUT(14) <= '0'; - DEBUG_OUT(15) <= '0'; --- 16 pin debug connector ends here - DEBUG_OUT(16) <= word_sync_rx_i; - DEBUG_OUT(17) <= word_sync_tx_i; - DEBUG_OUT(31 downto 18) <= (others => '0'); + DEBUG_OUT(3 downto 0) <= rx_fsm_state; + DEBUG_OUT(4) <= RX_LOS_IN; + DEBUG_OUT(5) <= RX_CDR_LOL_IN; + DEBUG_OUT(6) <= TX_PLL_LOL_IN; + DEBUG_OUT(7) <= LINK_TX_READY_IN; + DEBUG_OUT(8) <= link_rx_ready_i; + DEBUG_OUT(9) <= is_wap_zero_i; + DEBUG_OUT(10) <= link_half_done_i; + DEBUG_OUT(11) <= link_full_done_i; + DEBUG_OUT(15 downto 12) <= debug_tx_control_i(3 downto 0); + DEBUG_OUT(19 downto 16) <= rx_lsm_state; + DEBUG_OUT(20) <= word_sync_rx_i; + DEBUG_OUT(21) <= word_sync_tx_i; + DEBUG_OUT(31 downto 22) <= (others => '0'); -- DEBUG_OUT <= (others => '0'); -- Some remarks on the SerDes issue: diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 31e17ab..9bcfcbb 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -76,6 +76,11 @@ architecture rx_control_arch of rx_control_RS is signal link_full_done_qrx : std_logic; signal link_full_done_qsys : std_logic; +-- attribute syn_keep : boolean; +-- attribute syn_preserve : boolean; +-- attribute syn_keep of sync_k_i : signal is true; +-- attribute syn_preserve of sync_k_i : signal is true; + begin -- Syncing things diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd index a6b725a..06bc1be 100644 --- a/media_interfaces/sync/rx_rsl.vhd +++ b/media_interfaces/sync/rx_rsl.vhd @@ -30,9 +30,9 @@ architecture rx_rsl_arc of rx_rsl is constant Tshort : unsigned(31 downto 0) := x"0000000a"; -- @200MHz 100ms - constant Tplol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; - constant Tcdr : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; - constant Tviol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tplol : unsigned(31 downto 0) := x"01312d00"; --x"003fffff"; + constant Tcdr : unsigned(31 downto 0) := x"01312d00"; --x"003fffff"; + constant Tviol : unsigned(31 downto 0) := x"01312d00"; --x"003fffff"; signal pll_lol_s : std_logic; signal cdr_lol_s : std_logic; @@ -89,7 +89,8 @@ begin RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then +-- if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then + if( (pll_lol_s = '1') or (sd_los_s = '1') ) then cnt <= (others => '0'); else if( cnt = Tplol ) then diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 00ecc2d..f6799d4 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -15,7 +15,7 @@ entity tx_control_RS is IS_MODE : integer := c_IS_UNUSED ); port( - CLK_TXI : in std_logic; + CLK_TXI : in std_logic; CLK_SYS : in std_logic; RESET : in std_logic; -- async/sync reset -- Media Interface @@ -89,6 +89,8 @@ architecture arch of tx_control_RS is signal load_sop : std_logic; signal load_eop : std_logic; signal toggle_idle : std_logic; + signal send_steady_idle_int : std_logic; + signal word_sync_i : std_logic; signal link_tx_ready_qtx : std_logic; signal link_rx_ready_qtx : std_logic; @@ -97,8 +99,11 @@ architecture arch of tx_control_RS is signal link_active_int : std_logic; signal link_active_qtx : std_logic; signal link_active_qsys : std_logic; - - signal send_steady_idle_int : std_logic; + +-- attribute syn_keep : boolean; +-- attribute syn_preserve : boolean; +-- attribute syn_keep of word_sync_i : signal is true; +-- attribute syn_preserve of word_sync_i : signal is true; begin @@ -259,15 +264,16 @@ begin begin if( (LINK_TX_READY_IN = '0') or (RESET = '1') ) then current_state <= IDLE; - TX_K_OUT <= '1'; + TX_K_OUT <= '1'; TX_DATA_OUT <= K_NULL; - WORD_SYNC_OUT <= '0'; + word_sync_i <= '0'; + toggle_idle <= '1'; else if( rising_edge(CLK_TXI) ) then - TX_K_OUT <= '0'; - WORD_SYNC_OUT <= '0'; - debug_sending_dlm <= '0'; - debug_sending_rst <= '0'; + TX_K_OUT <= '0'; + word_sync_i <= '0'; + debug_sending_dlm <= '0'; + debug_sending_rst <= '0'; case current_state is when SEND_IDLE_L => TX_DATA_OUT <= K_IDLE; @@ -279,7 +285,7 @@ begin end if; when SEND_IDLE_H => - WORD_SYNC_OUT <= '1'; + word_sync_i <= '1'; if( (send_steady_idle_int = '1') or (toggle_idle = '1') ) then TX_DATA_OUT <= D_IDLE1; toggle_idle <= send_steady_idle_int; @@ -295,8 +301,8 @@ begin current_state <= SEND_DATA_H; when SEND_DATA_H => - WORD_SYNC_OUT <= '1'; - TX_DATA_OUT <= ram_dout(15 downto 8); + word_sync_i <= '1'; + TX_DATA_OUT <= ram_dout(15 downto 8); when SEND_DLM_L => TX_DATA_OUT <= K_DLM; @@ -305,8 +311,8 @@ begin debug_sending_dlm <= '1'; when SEND_DLM_H => - WORD_SYNC_OUT <= '1'; - TX_DATA_OUT <= send_dlm_word_i; + word_sync_i <= '1'; + TX_DATA_OUT <= send_dlm_word_i; when SEND_RST_L => TX_DATA_OUT <= K_RST; @@ -321,8 +327,8 @@ begin -- used to get out of async reset when SEND_RST_H => - WORD_SYNC_OUT <= '1'; - TX_DATA_OUT <= send_rst_word_i; + word_sync_i <= '1'; + TX_DATA_OUT <= send_rst_word_i; when others => current_state <= SEND_IDLE_L; @@ -417,9 +423,9 @@ send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); DEBUG_OUT(30) <= send_dlm_i; DEBUG_OUT(29) <= debug_sending_rst when rising_edge(CLK_TXI); DEBUG_OUT(28 downto 6) <= (others => '0'); - DEBUG_OUT(5) <= send_steady_idle_int; - DEBUG_OUT(4) <= toggle_idle; - DEBUG_OUT(3 downto 0) <= state_bits; + DEBUG_OUT(5) <= send_steady_idle_int when rising_edge(CLK_TXI); + DEBUG_OUT(4) <= toggle_idle when rising_edge(CLK_TXI); + DEBUG_OUT(3 downto 0) <= state_bits when rising_edge(CLK_TXI); process(CLK_SYS) begin @@ -443,13 +449,15 @@ send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); end if; end process; -state_bits <= x"0" when current_state = IDLE else - x"1" when current_state = SEND_IDLE_L else - x"2" when current_state = SEND_IDLE_H else - x"3" when current_state = SEND_DATA_L else - x"4" when current_state = SEND_DATA_H else - x"5" when current_state = SEND_DLM_L else - x"6" when current_state = SEND_DLM_H else - x"F"; + state_bits <= x"0" when current_state = IDLE else + x"1" when current_state = SEND_IDLE_L else + x"2" when current_state = SEND_IDLE_H else + x"3" when current_state = SEND_DATA_L else + x"4" when current_state = SEND_DATA_H else + x"5" when current_state = SEND_DLM_L else + x"6" when current_state = SEND_DLM_H else + x"F"; + WORD_SYNC_OUT <= word_sync_i; + end architecture;