From: Jan Michel Date: Fri, 14 Apr 2023 13:21:31 +0000 (+0200) Subject: add iD lines, I2C, update identification registers X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=dd06b2a38f890d9abc24dccbb40f14fdd343760c;p=mdcupgrade.git add iD lines, I2C, update identification registers --- diff --git a/DBO/config.vhd b/DBO/config.vhd index 45bf249..c7abcfd 100644 --- a/DBO/config.vhd +++ b/DBO/config.vhd @@ -36,7 +36,6 @@ package config is constant INCLUDE_SPI : integer := c_NO; --300 slices constant INCLUDE_ADC : integer := c_NO; constant INCLUDE_I2C : integer := c_NO; - constant INCLUDE_LCD : integer := c_NO; --800 slices constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices --input monitor and trigger generation logic @@ -50,10 +49,6 @@ package config is --End of design configuration ------------------------------------------------------------------------------ - - type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); - constant LCD_DATA : data_t := (others => x"00"); - ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ @@ -85,15 +80,13 @@ function generateIncludedFeatures return std_logic_vector is t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); --- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); --- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(11 downto 8) := std_logic_vector(to_unsigned(5,4)); --clock TDC double edge, same channel, no stretcher + t(14 downto 12) := std_logic_vector(to_unsigned(0,3)); t(15) := '1'; --TDC - t(17 downto 16) := "00"; - - t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); diff --git a/DBO/mdctdc.prj b/DBO/mdctdc.prj index 2b7559d..30ace65 100644 --- a/DBO/mdctdc.prj +++ b/DBO/mdctdc.prj @@ -148,7 +148,6 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" -add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" diff --git a/DBO/mdctdc.vhd b/DBO/mdctdc.vhd index f6318e1..05194b9 100644 --- a/DBO/mdctdc.vhd +++ b/DBO/mdctdc.vhd @@ -23,6 +23,7 @@ entity mdctdc is TEST : out std_logic_vector(3 downto 0); INJ : out std_logic_vector(3 downto 0); PTEN : out std_logic_vector(2 downto 1); + ID : in std_logic_vector(1 downto 0); RSTN : out std_logic_vector(2 downto 1); MISO : in std_logic_vector(2 downto 1); @@ -171,6 +172,7 @@ begin REGIO_INIT_ENDPOINT_ID => x"0001", REGIO_USE_1WIRE_INTERFACE => c_I2C, TIMING_TRIGGER_RAW => c_YES, + REGIO_USE_VAR_ENDPOINT_ID => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 2, DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, @@ -209,6 +211,8 @@ begin ONEWIRE_INOUT => open, I2C_SCL => I2C_SCL, I2C_SDA => I2C_SDA, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + REGIO_VAR_ENDPOINT_ID(1 downto 0) => ID, --Timing registers TIMERS_OUT => timer ); diff --git a/OEP/config.vhd b/OEP/config.vhd index da98f26..76e6373 100644 --- a/OEP/config.vhd +++ b/OEP/config.vhd @@ -28,7 +28,7 @@ package config is constant INCLUDE_UART : integer := c_NO; constant INCLUDE_SPI : integer := c_NO; constant INCLUDE_ADC : integer := c_YES; - constant INCLUDE_I2C : integer := c_NO; + constant INCLUDE_I2C : integer := c_YES; constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --input monitor and trigger generation logic @@ -80,6 +80,7 @@ function generateIncludedFeatures return std_logic_vector is t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); return t; diff --git a/OEP/config_compile_frankfurt.pl b/OEP/config_compile_frankfurt.pl index 310aee4..de5e337 100644 --- a/OEP/config_compile_frankfurt.pl +++ b/OEP/config_compile_frankfurt.pl @@ -10,7 +10,7 @@ lm_license_file_for_par => "1702\@jspc29", lattice_path => '/d/jspc29/lattice/diamond/3.12', synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', -nodelist_file => '../nodelist_frankfurt.txt', +nodelist_file => 'nodelist_frankfurt.txt', pinout_file => 'oep', par_options => '../par.p2t', diff --git a/OEP/mdcoep.prj b/OEP/mdcoep.prj index 3ac56e6..4523d84 100644 --- a/OEP/mdcoep.prj +++ b/OEP/mdcoep.prj @@ -103,7 +103,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" - +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" @@ -212,6 +212,9 @@ add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" add_file -vhdl -lib work "./mdcoep.vhd" #add_file -fpga_constraint "./synplify.fdc" diff --git a/OEP/mdcoep.vhd b/OEP/mdcoep.vhd index 1a97f6b..f2c9e47 100644 --- a/OEP/mdcoep.vhd +++ b/OEP/mdcoep.vhd @@ -38,6 +38,8 @@ entity mdcoep is SFP_LOS : in std_logic; SFP_TX_DIS : out std_logic; SFP_MOD0 : in std_logic; + SFP_MOD1 : inout std_logic; + SFP_MOD2 : inout std_logic; ADC_MISO : in std_logic; ADC_MOSI : out std_logic; @@ -216,7 +218,7 @@ begin USE_ONEWIRE => c_I2C, HARDWARE_VERSION => HARDWARE_INFO, INCLUDED_FEATURES => INCLUDED_FEATURES, - INIT_ENDPOINT_ID => x"0001", + INIT_ENDPOINT_ID => x"0005", INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & x"00000000_00000000_00000000_00000000" & x"00000000_00000000_800a4000_00000000" & @@ -343,13 +345,16 @@ begin SPI_MISO_IN => open, SPI_CLK_OUT => open, --Header - HEADER_IO => open, + --HEADER_IO => open, ADDITIONAL_REG => additional_reg, --ADC ADC_CS => ADC_CS, ADC_MOSI => ADC_MOSI, ADC_MISO => ADC_MISO, ADC_CLK => ADC_SCK, + --I2C + HEADER_IO(7) => SFP_MOD2, + HEADER_IO(8) => SFP_MOD1, --Trigger & Monitor MONITOR_INPUTS => monitor_inputs_i, TRIG_GEN_INPUTS => trigger_inputs_i, diff --git a/pinout/dbo.lpf b/pinout/dbo.lpf index 0571332..d32d6d0 100644 --- a/pinout/dbo.lpf +++ b/pinout/dbo.lpf @@ -31,6 +31,12 @@ LOCATE COMP "GPIO_3" SITE "B16"; DEFINE PORT GROUP "GPIO_group" "GPIO*"; IOBUF GROUP "GPIO_group" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ID_0" SITE "R1"; +LOCATE COMP "ID_1" SITE "T1"; +DEFINE PORT GROUP "ID_group" "ID*"; +IOBUF GROUP "ID_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + LOCATE COMP "I2C_SCL" SITE "A17"; LOCATE COMP "I2C_SDA" SITE "A18"; IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; diff --git a/pinout/oep.lpf b/pinout/oep.lpf index 655fa65..7686d07 100644 --- a/pinout/oep.lpf +++ b/pinout/oep.lpf @@ -88,6 +88,8 @@ IOBUF PORT "LONG_SHORT" IO_TYPE=LVCMOS25 PULLMODE=UP; LOCATE COMP "SFP_LOS" SITE "A7"; LOCATE COMP "SFP_TX_DIS" SITE "A8"; LOCATE COMP "SFP_MOD0" SITE "B9"; +LOCATE COMP "SFP_MOD1" SITE "A10"; +LOCATE COMP "SFP_MOD2" SITE "B11"; DEFINE PORT GROUP "SFP_group" "SFP*"; IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 ;