From: Andreas Neiser Date: Tue, 17 Feb 2015 13:53:03 +0000 (+0100) Subject: Sim works somehow, now feed in reasonable data X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=dd96483e71162efddf88eec74e901a17c981effc;p=trb3.git Sim works somehow, now feed in reasonable data --- diff --git a/ADC/sim/adcprocessor.mpf b/ADC/sim/adcprocessor.mpf index e2a0ad2..2325499 100644 --- a/ADC/sim/adcprocessor.mpf +++ b/ADC/sim/adcprocessor.mpf @@ -1755,7 +1755,7 @@ Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v Project_File_6 = ../cores/mulacc2.vhd Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423224716 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_7 = tb_adcprocessor.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424179717 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424180821 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_8 = /home/aneiser/trb3/base/cores/dqsinput_7x5.vhd Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1391588655 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_9 = /home/aneiser/trb3/base/cores/fifo_cdt_200_50.vhd diff --git a/ADC/sim/tb_adcprocessor.vhd b/ADC/sim/tb_adcprocessor.vhd index ad8ed90..e248519 100644 --- a/ADC/sim/tb_adcprocessor.vhd +++ b/ADC/sim/tb_adcprocessor.vhd @@ -64,10 +64,10 @@ end component; signal clock100 : std_logic := '1'; signal clock200 : std_logic := '1'; -signal adc_data : std_logic_vector(39 downto 0) := (others => '0'); -signal adc_data_ser : std_logic_vector(24 downto 0); -signal adc_dco : std_logic_vector(5 downto 1); -signal adc_valid : std_logic := '0'; +signal adc_data : std_logic_vector(199 downto 0) := (others => '0'); +signal adc_data_ser : std_logic_vector(24 downto 0) := (others => '0'); +signal adc_dco : std_logic_vector(5 downto 1) := (others => '0'); +signal adc_valid : std_logic_vector(4 downto 0) := (others => '1'); signal stop_in : std_logic := '0'; signal trigger_out: std_logic := '0'; signal config : cfg_t; @@ -208,9 +208,9 @@ THE_ADC : adc_ad9219 ADCCLK_OUT => open, ADC_DATA => adc_data_ser, ADC_DCO => adc_dco, - DATA_OUT(39 downto 0) => adc_data, + DATA_OUT => adc_data, FCO_OUT => open, - DATA_VALID_OUT(0) => adc_valid, + DATA_VALID_OUT => adc_valid, DEBUG => open ); @@ -220,8 +220,8 @@ UUT: adc_processor ) port map( CLK => clock100, - ADC_DATA => adc_data, - ADC_VALID => adc_valid, + ADC_DATA => adc_data(39 downto 0), + ADC_VALID => adc_valid(0), STOP_IN => stop_in, TRIGGER_OUT=> trigger_out,