From: Jan Michel Date: Thu, 15 Dec 2022 10:54:34 +0000 (+0100) Subject: add GbE ping module from blackcat branch X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=de525c483418f28bbcd7a174355c4adc06ef6459;p=trbnet.git add GbE ping module from blackcat branch --- diff --git a/gbe_trb/base/gbe_protocol_selector.vhd b/gbe_trb/base/gbe_protocol_selector.vhd new file mode 100644 index 0000000..6c22e2b --- /dev/null +++ b/gbe_trb/base/gbe_protocol_selector.vhd @@ -0,0 +1,830 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; + +--******** +-- multiplexes between different protocols and manages the responses +-- +-- + + +entity trb_net16_gbe_protocol_selector is + generic( + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + INCLUDE_FWD : std_logic := '0'; + READOUT_BUFFER_SIZE : integer range 1 to 4; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 + ); + port( + CLK : in std_logic; -- system clock + RESET : in std_logic; + RESET_FOR_DHCP : in std_logic; + + -- signals to/from main controller + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + PS_RESPONSE_READY_OUT : out std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + -- singals to/from transmit controller with constructed response + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_RD_EN_IN : in std_logic; + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + MC_BUSY_IN : in std_logic; + + -- misc signals for response constructors + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_OUT : out std_logic_vector(31 downto 0); + DHCP_START_IN : in std_logic; + DHCP_DONE_OUT : out std_logic; + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + MAKE_RESET_OUT : out std_logic; + + MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0); + ISSUE_REBOOT_OUT : out std_logic; + + -- signal for data readout + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + CFG_AUTO_THROTTLE_IN : in std_logic; + CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0); + +-- Forwarder +FWD_DST_MAC_IN : in std_logic_vector(47 downto 0); +FWD_DST_IP_IN : in std_logic_vector(31 downto 0); +FWD_DST_UDP_IN : in std_logic_vector(15 downto 0); +FWD_DATA_IN : in std_logic_vector(7 downto 0); +FWD_DATA_VALID_IN : in std_logic; +FWD_SOP_IN : in std_logic; +FWD_EOP_IN : in std_logic; +FWD_READY_OUT : out std_logic; +FWD_FULL_OUT : out std_logic; + + -- input for statistics from outside + STAT_DATA_IN : in std_logic_vector(31 downto 0); + STAT_ADDR_IN : in std_logic_vector(7 downto 0); + STAT_DATA_RDY_IN : in std_logic; + STAT_DATA_ACK_OUT : out std_logic; + MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0); + DATA_HIST_OUT : out hist_array; + SCTRL_HIST_OUT : out hist_array; + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end trb_net16_gbe_protocol_selector; + +architecture trb_net16_gbe_protocol_selector of trb_net16_gbe_protocol_selector is + + --attribute HGROUP : string; + --attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group"; + + attribute syn_encoding : string; + + signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal tc_data : std_logic_vector(c_MAX_PROTOCOLS * 9 - 1 downto 0); + signal tc_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal tc_type : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal selected : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal tc_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0); + signal tc_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal tc_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal tc_src_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0); + signal tc_src_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal tc_src_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0); + + -- plus 1 is for the outside + signal stat_data : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal stat_addr : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0); + signal stat_rdy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal stat_ack : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal tc_ip_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal tc_udp_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal tc_size_left : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal tc_flags_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + + signal tc_data_not_valid : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP); + signal select_current_state, select_next_state : select_states; + attribute syn_encoding of select_current_state : signal is "onehot"; + + signal state : std_logic_vector(3 downto 0); + signal index : integer range 0 to c_MAX_PROTOCOLS - 1; + + signal mult : std_logic; + + signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); + signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_keep of state, mult : signal is true; + attribute syn_preserve of state, mult : signal is true; + + signal my_ip : std_logic_vector(31 downto 0); + signal select_state : std_logic_vector(3 downto 0); + +begin + zeros <= (others => '0'); + MY_IP_OUT <= my_ip; + + arp_gen : if INCLUDE_ARP = '1' generate + -- protocol Nr. 1 ARP + ARP : trb_net16_gbe_response_constructor_ARP + generic map(STAT_ADDRESS_BASE => 6 + ) + port map( + CLK => CLK, + RESET => RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0), + PS_RESPONSE_READY_OUT => resp_ready(0), + PS_BUSY_OUT => busy(0), + PS_SELECTED_IN => selected(0), + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9), + TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16), + TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8), + TC_IDENT_OUT => tc_ident(1 * 16 - 1 downto 0 * 16), + TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48), + TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32), + TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16), + TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48), + TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32), + TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16), + STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32), + STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8), + STAT_DATA_RDY_OUT => stat_rdy(0), + STAT_DATA_ACK_IN => stat_ack(0), + RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16), + SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16), + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32) + -- END OF INTERFACE + ); + end generate arp_gen; + + no_arp_gen : if INCLUDE_ARP = '0' generate + resp_ready(0) <= '0'; + busy(0) <= '0'; + end generate no_arp_gen; + + dhcp_gen : if INCLUDE_DHCP = '1' generate + -- protocol No. 2 DHCP + DHCP : trb_net16_gbe_response_constructor_DHCP + generic map( + STAT_ADDRESS_BASE => 0, + DO_SIMULATION => DO_SIMULATION + ) + port map( + CLK => CLK, + RESET => RESET_FOR_DHCP, --RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1), + PS_RESPONSE_READY_OUT => resp_ready(1), + PS_BUSY_OUT => busy(1), + PS_SELECTED_IN => selected(1), + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9), + TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16), + TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8), + TC_IDENT_OUT => tc_ident(2 * 16 - 1 downto 1 * 16), + TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48), + TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32), + TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16), + TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48), + TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32), + TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16), + STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32), + STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8), + STAT_DATA_RDY_OUT => stat_rdy(1), + STAT_DATA_ACK_IN => stat_ack(1), + RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16), + SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16), + -- END OF INTERFACE + + MY_IP_OUT => my_ip, + DHCP_START_IN => DHCP_START_IN, + DHCP_DONE_OUT => DHCP_DONE_OUT, + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32) + ); + end generate dhcp_gen; + + no_dhcp_gen : if INCLUDE_DHCP = '0' generate + resp_ready(1) <= '0'; + busy(1) <= '0'; + end generate no_dhcp_gen; + + ping_gen : if INCLUDE_PING = '1' generate + --protocol No. 3 Ping + Ping : entity work.gbe_response_constructor_Ping + port map( + CLK => CLK, + RESET => RESET, + + ---- INTERFACE + MY_MAC_IN => MY_MAC_IN, + --MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN, + --ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT, + MY_IP_IN => my_ip, + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4), + PS_RESPONSE_READY_OUT => resp_ready(4), + PS_BUSY_OUT => busy(4), + PS_FRAME_SIZE_IN => PS_FRAME_SIZE_IN, + PS_FRAME_INFO_IN => open, + PS_SELECTED_IN => selected(4), + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + --PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + --PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + --PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9), + TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16), + TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8), + TC_IDENT_OUT => tc_ident(5 * 16 - 1 downto 4 * 16), + TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48), + TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32), + TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16), + TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48), + TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32), + TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16), + --STAT_DATA_OUT => open, + --STAT_ADDR_OUT => open, + --STAT_DATA_RDY_OUT => open, + --STAT_DATA_ACK_IN => '0', + --RECEIVED_FRAMES_OUT => open, + --SENT_FRAMES_OUT => open, + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(5 * 64 - 1 downto 4 * 64) + -- END OF INTERFACE + ); + end generate ping_gen; + + no_ping_gen : if INCLUDE_PING = '0' generate + resp_ready(4) <= '0'; + busy(4) <= '0'; + end generate no_ping_gen; + + sctrl_gen : if INCLUDE_SLOWCTRL = '1' generate + SCTRL : trb_net16_gbe_response_constructor_SCTRL + generic map(STAT_ADDRESS_BASE => 8, + SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE + ) + port map( + CLK => CLK, + RESET => RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2), + PS_RESPONSE_READY_OUT => resp_ready(2), + PS_BUSY_OUT => busy(2), + PS_SELECTED_IN => selected(2), + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9), + TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16), + TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8), + TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16), + TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48), + TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32), + TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16), + TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48), + TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32), + TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16), + STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32), + STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8), + STAT_DATA_RDY_OUT => stat_rdy(2), + STAT_DATA_ACK_IN => stat_ack(2), + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(3 * 64 - 1 downto 2 * 64), + -- END OF INTERFACE + + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, + GSC_BUSY_IN => GSC_BUSY_IN, + CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, + CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, + MAKE_RESET_OUT => MAKE_RESET_OUT, + MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(3 * 32 - 1 downto 2 * 32), + MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(3 * 32 - 1 downto 2 * 32), + MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(3 * 32 - 1 downto 2 * 32), + MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(3 * 32 - 1 downto 2 * 32), + DATA_HIST_OUT => SCTRL_HIST_OUT + ); + end generate sctrl_gen; + + no_sctrl_gen : if INCLUDE_SLOWCTRL = '0' generate + resp_ready(2) <= '0'; + busy(2) <= '0'; + MAKE_RESET_OUT <= '0'; + + GSC_INIT_DATAREADY_OUT <= '0'; + GSC_INIT_DATA_OUT <= (others => '0'); + GSC_INIT_PACKET_NUM_OUT <= (others => '0'); + GSC_REPLY_READ_OUT <= '1'; + + end generate no_sctrl_gen; + + trbnet_gen : if INCLUDE_READOUT = '1' generate + TrbNetData : trb_net16_gbe_response_constructor_TrbNetData + generic map( + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE + ) + port map( + CLK => CLK, + RESET => RESET, + + -- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3), + PS_RESPONSE_READY_OUT => resp_ready(3), + PS_BUSY_OUT => busy(3), + PS_SELECTED_IN => selected(3), + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9), + TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16), + TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8), + TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16), + TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48), + TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32), + TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16), + TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48), + TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32), + TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16), + STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32), + STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8), + STAT_DATA_RDY_OUT => stat_rdy(3), + STAT_DATA_ACK_IN => stat_ack(3), + DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64), + -- END OF INTERFACE + + -- CTS interface + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data payload interface + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, + CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, + CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, + CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, + CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, + CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, + CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, + CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, + CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, + CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, + CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, + CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, + CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, + CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN, + CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN, + MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32), + MONITOR_SELECT_DROP_IN_OUT => open, + DATA_HIST_OUT => DATA_HIST_OUT + ); + end generate trbnet_gen; + + no_readout_gen : if INCLUDE_READOUT = '0' generate + resp_ready(3) <= '0'; + busy(3) <= '0'; + CTS_DATA_OUT <= (others => '0'); + CTS_DATAREADY_OUT <= '0'; + CTS_READOUT_FINISHED_OUT <= '0'; + CTS_LENGTH_OUT <= (others => '0'); + CTS_ERROR_PATTERN_OUT <= (others => '0'); + FEE_READ_OUT <= '0'; + end generate no_readout_gen; + + + fwd_gen : if INCLUDE_FWD = '1' generate + + Forward : entity work.trb_net16_gbe_response_constructor_Forward + port map( + CLK => CLK, + RESET => RESET, + + ---- INTERFACE + MY_MAC_IN => MY_MAC_IN, + MY_IP_IN => my_ip, + PS_DATA_IN => PS_DATA_IN, + PS_WR_EN_IN => PS_WR_EN_IN, + PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(5), + PS_RESPONSE_READY_OUT => resp_ready(5), + PS_BUSY_OUT => busy(5), + PS_SELECTED_IN => selected(5), + PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_DATA_OUT => tc_data(6 * 9 - 1 downto 5 * 9), + TC_FRAME_SIZE_OUT => tc_size(6 * 16 - 1 downto 5 * 16), + TC_FRAME_TYPE_OUT => tc_type(6 * 16 - 1 downto 5 * 16), + TC_IP_PROTOCOL_OUT => tc_ip_proto(6 * 8 - 1 downto 5 * 8), + TC_IDENT_OUT => tc_ident(6 * 16 - 1 downto 5 * 16), + TC_DEST_MAC_OUT => tc_mac(6 * 48 - 1 downto 5 * 48), + TC_DEST_IP_OUT => tc_ip(6 * 32 - 1 downto 5 * 32), + TC_DEST_UDP_OUT => tc_udp(6 * 16 - 1 downto 5 * 16), + TC_SRC_MAC_OUT => tc_src_mac(6 * 48 - 1 downto 5 * 48), + TC_SRC_IP_OUT => tc_src_ip(6 * 32 - 1 downto 5 * 32), + TC_SRC_UDP_OUT => tc_src_udp(6 * 16 - 1 downto 5 * 16), + RECEIVED_FRAMES_OUT => open, + SENT_FRAMES_OUT => open, + + FWD_DST_MAC_IN => FWD_DST_MAC_IN, + FWD_DST_IP_IN => FWD_DST_IP_IN, + FWD_DST_UDP_IN => FWD_DST_UDP_IN, + FWD_DATA_IN => FWD_DATA_IN, + FWD_DATA_VALID_IN => FWD_DATA_VALID_IN, + FWD_SOP_IN => FWD_SOP_IN, + FWD_EOP_IN => FWD_EOP_IN, + FWD_READY_OUT => FWD_READY_OUT, + FWD_FULL_OUT => FWD_FULL_OUT, + + + + DEBUG_OUT => open + -- END OF INTERFACE + ); + + end generate fwd_gen; + + no_fwd_gen : if INCLUDE_FWD = '0' generate + resp_ready(5) <= '0'; + busy(5) <= '0'; + end generate no_fwd_gen; + + --stat_gen : if g_SIMULATE = 0 generate + --Stat : trb_net16_gbe_response_constructor_Stat + --generic map( STAT_ADDRESS_BASE => 10 + --) + --port map ( + -- CLK => CLK, + -- RESET => RESET, + -- + ---- INTERFACE + -- PS_DATA_IN => PS_DATA_IN, + -- PS_WR_EN_IN => PS_WR_EN_IN, + -- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4), + -- PS_RESPONSE_READY_OUT => resp_ready(4), + -- PS_BUSY_OUT => busy(4), + -- PS_SELECTED_IN => selected(4), + -- + -- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, + -- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, + -- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, + -- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, + -- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, + -- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, + -- + -- TC_WR_EN_OUT => TC_WR_EN_OUT, + -- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9), + -- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16), + -- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16), + -- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8), + -- + -- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48), + -- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32), + -- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16), + -- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48), + -- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32), + -- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16), + -- + -- TC_IP_SIZE_OUT => tc_ip_size(5 * 16 - 1 downto 4 * 16), + -- TC_UDP_SIZE_OUT => tc_udp_size(5 * 16 - 1 downto 4 * 16), + -- TC_FLAGS_OFFSET_OUT => tc_flags_size(5 * 16 - 1 downto 4 * 16), + -- + -- TC_BUSY_IN => TC_BUSY_IN, + -- + -- STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32), + -- STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8), + -- STAT_DATA_RDY_OUT => stat_rdy(4), + -- STAT_DATA_ACK_IN => stat_ack(4), + -- + -- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16), + -- SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16), + -- DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32), + -- + -- STAT_DATA_IN => stat_data, + -- STAT_ADDR_IN => stat_addr, + -- STAT_DATA_RDY_IN => stat_rdy, + -- STAT_DATA_ACK_OUT => stat_ack + --); + --end generate; + + --*************** + -- DO NOT TOUCH, response selection logic + + --stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN; + --stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN; + --stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN; + --STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS); + + --mult <= or_all(resp_ready(2 downto 0)); --or_all(resp_ready(2 downto 0)) and or_all(resp_ready(4 downto 3)); + + PS_BUSY_OUT <= busy; + + SELECT_MACHINE_PROC : process(RESET, CLK) + begin + if RESET = '1' then + select_current_state <= IDLE; + elsif rising_edge(CLK) then + -- if (RESET = '1') then + -- select_current_state <= IDLE; + -- else + select_current_state <= select_next_state; + -- end if; + end if; + end process SELECT_MACHINE_PROC; + + SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros, busy) + begin + select_state <= x"0"; + + case (select_current_state) is + when IDLE => + select_state <= x"1"; + if (MC_BUSY_IN = '0') then + select_next_state <= LOOP_OVER; + else + select_next_state <= IDLE; + end if; + + when LOOP_OVER => + select_state <= x"2"; + if (resp_ready /= zeros) then + if (resp_ready(index) = '1') then + select_next_state <= SELECT_ONE; + elsif (index = c_MAX_PROTOCOLS) then + select_next_state <= CLEANUP; + else + select_next_state <= LOOP_OVER; + end if; + else + select_next_state <= CLEANUP; + end if; + + when SELECT_ONE => + select_state <= x"3"; + if (MC_BUSY_IN = '1') then + select_next_state <= PROCESS_REQUEST; + else + select_next_state <= SELECT_ONE; + end if; + + when PROCESS_REQUEST => + select_state <= x"4"; + if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then + select_next_state <= CLEANUP; + else + select_next_state <= PROCESS_REQUEST; + end if; + + when CLEANUP => + select_state <= x"5"; + select_next_state <= IDLE; + + when others => select_next_state <= IDLE; + + end case; + + end process SELECT_MACHINE; + + INDEX_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (select_current_state = IDLE) then + index <= 0; + elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0') then + index <= index + 1; + else + index <= index; + end if; + end if; + end process INDEX_PROC; + + SELECTOR_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST) then + TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9); + TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16); + TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16); + TC_DEST_MAC_OUT <= tc_mac((index + 1) * 48 - 1 downto index * 48); + TC_DEST_IP_OUT <= tc_ip((index + 1) * 32 - 1 downto index * 32); + TC_DEST_UDP_OUT <= tc_udp((index + 1) * 16 - 1 downto index * 16); + TC_SRC_MAC_OUT <= tc_src_mac((index + 1) * 48 - 1 downto index * 48); + TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32); + TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16); + TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8); + TC_IDENT_OUT <= tc_ident((index + 1) * 16 - 1 downto index * 16); + if (select_current_state = SELECT_ONE) then + PS_RESPONSE_READY_OUT <= '1'; + selected(index) <= '0'; + else + PS_RESPONSE_READY_OUT <= '0'; + selected(index) <= '1'; + end if; + else + TC_DATA_OUT <= (others => '0'); + TC_FRAME_SIZE_OUT <= (others => '0'); + TC_FRAME_TYPE_OUT <= (others => '0'); + TC_DEST_MAC_OUT <= (others => '0'); + TC_DEST_IP_OUT <= (others => '0'); + TC_DEST_UDP_OUT <= (others => '0'); + TC_SRC_MAC_OUT <= (others => '0'); + TC_SRC_IP_OUT <= (others => '0'); + TC_SRC_UDP_OUT <= (others => '0'); + TC_IP_PROTOCOL_OUT <= (others => '0'); + TC_IDENT_OUT <= (others => '0'); + PS_RESPONSE_READY_OUT <= '0'; + selected <= (others => '0'); + end if; + end if; + end process SELECTOR_PROC; + + process(CLK) + begin + if rising_edge(CLK) then + DEBUG_OUT(3 downto 0) <= select_state; + DEBUG_OUT(11 downto 4) <= std_logic_vector(to_unsigned(index, 8)); + DEBUG_OUT(19 downto 12) <= "00" & resp_ready; -- 4:0 + DEBUG_OUT(27 downto 20) <= "00" & busy; -- 4:0 + DEBUG_OUT(63 downto 28) <= (others => '0'); + end if; + end process; + +end trb_net16_gbe_protocol_selector; + + diff --git a/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.lpc b/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.lpc new file mode 100644 index 0000000..99cfb24 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.lpc @@ -0,0 +1,63 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN672C +SpeedGrade=6 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP_TRUE +CoreRevision=7.5 +ModuleName=ram_dp_true_2kx9 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/18/2022 +Time=00:17:59 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +AAddress=2048 +BAddress=2048 +AData=9 +BData=9 +enByte=0 +ByteSize=8 +AadPipeline=0 +BadPipeline=0 +AinPipeline=0 +BinPipeline=0 +AoutPipeline=0 +BoutPipeline=0 +AMOR=0 +BMOR=0 +AInData=Registered +BInData=Registered +AAdControl=Registered +BAdControl=Registered +MemFile= +MemFormat=bin +Reset=Sync +GSR=Enabled +WriteA=Normal +WriteB=Normal +Pad=0 +EnECC=0 +Optimization=Speed +Pipeline=0 + +[FilesGenerated] +=mem + +[Command] +cmd_line= -w -n ram_dp_true_2kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ramdp -device LFE3-150EA -aaddr_width 11 -widtha 9 -baddr_width 11 -widthb 9 -anum_words 2048 -bnum_words 2048 -writemodeA NORMAL -writemodeB NORMAL -cascade -1 diff --git a/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.vhd b/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.vhd new file mode 100644 index 0000000..b985071 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.vhd @@ -0,0 +1,178 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 7.5 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n ram_dp_true_2kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 9 -rdata_width 9 -num_rows 2048 -writemodeA NORMAL -writemodeB NORMAL -cascade -1 + +-- Fri Nov 18 00:18:00 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ram_dp_true_2kx9 is + port ( + DataInA: in std_logic_vector(8 downto 0); + DataInB: in std_logic_vector(8 downto 0); + AddressA: in std_logic_vector(10 downto 0); + AddressB: in std_logic_vector(10 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(8 downto 0); + QB: out std_logic_vector(8 downto 0)); +end ram_dp_true_2kx9; + +architecture Structure of ram_dp_true_2kx9 is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ram_dp_true_2kx9_0_0_0 : label is "ram_dp_true_2kx9.lpc"; + attribute MEM_INIT_FILE of ram_dp_true_2kx9_0_0_0 : label is ""; + attribute RESETMODE of ram_dp_true_2kx9_0_0_0 : label is "SYNC"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + ram_dp_true_2kx9_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), + DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), + DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>AddressA(0), ADA4=>AddressA(1), ADA5=>AddressA(2), + ADA6=>AddressA(3), ADA7=>AddressA(4), ADA8=>AddressA(5), + ADA9=>AddressA(6), ADA10=>AddressA(7), ADA11=>AddressA(8), + ADA12=>AddressA(9), ADA13=>AddressA(10), CEA=>ClockEnA, + CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, + DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2), + DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5), + DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8), + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>AddressB(0), ADB4=>AddressB(1), ADB5=>AddressB(2), + ADB6=>AddressB(3), ADB7=>AddressB(4), ADB8=>AddressB(5), + ADB9=>AddressB(6), ADB10=>AddressB(7), ADB11=>AddressB(8), + ADB12=>AddressB(9), ADB13=>AddressB(10), CEB=>ClockEnB, + CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0), + DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4), + DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8), + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2), + DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6), + DOB7=>QB(7), DOB8=>QB(8), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ram_dp_true_2kx9 is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/protocols/gbe_response_constructor_Ping.vhd b/gbe_trb/protocols/gbe_response_constructor_Ping.vhd new file mode 100644 index 0000000..900399c --- /dev/null +++ b/gbe_trb/protocols/gbe_response_constructor_Ping.vhd @@ -0,0 +1,304 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + +-- BUG: answers always with PING REPLY. No choice on TYPE/CODE is made! + +entity gbe_response_constructor_Ping is + port( + CLK : in std_logic; -- system clock + RESET : in std_logic; + -- INTERFACE + MY_MAC_IN : in std_logic_vector(47 downto 0); + MY_IP_IN : in std_logic_vector(31 downto 0); + PS_DATA_IN : in std_logic_vector(8 downto 0); + PS_WR_EN_IN : in std_logic; + PS_ACTIVATE_IN : in std_logic; + PS_RESPONSE_READY_OUT : out std_logic; + PS_BUSY_OUT : out std_logic; + PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + PS_FRAME_INFO_IN : in std_logic_vector(7 downto 0); + PS_SELECTED_IN : in std_logic; + PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + -- + TC_RD_EN_IN : in std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + -- END OF INTERFACE + -- debug + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end gbe_response_constructor_Ping; + +architecture gbe_response_constructor_Ping_arch of gbe_response_constructor_Ping is + + attribute HGROUP : string; + attribute HGROUP of gbe_response_constructor_Ping_arch: architecture is "gbe_response_constructor_Ping_group"; + + attribute syn_encoding : string; + + type DISSECT_STATES is (IDLE, READ_FRAME, DELAY, DO_HEADER, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP); + signal DISSECT_CS, DISSECT_NS : DISSECT_STATES; + attribute syn_encoding of DISSECT_CS: signal is "onehot"; + + signal state : std_logic_vector(3 downto 0); + + signal sent_frames : unsigned(15 downto 0); + + signal dissect_ctr : unsigned(10 downto 0); + signal hdr_wr_x : std_logic; + signal hdr_wr : std_logic; + signal crc_l : unsigned(19 downto 0); + signal crc_r : unsigned(19 downto 0); + signal crc_ll : unsigned(15 downto 0); + signal crc_rr : unsigned(15 downto 0); + signal crc_lll : unsigned(15 downto 0); + signal crc_rrr : unsigned(15 downto 0); + signal crc : std_logic_vector(15 downto 0); + signal hdr_data : std_logic_vector(8 downto 0); + signal pl_data_x : std_logic_vector(8 downto 0); + signal pl_data : std_logic_vector(8 downto 0); + signal transmit_size : unsigned(15 downto 0); + + signal ps_response_ready : std_logic; + signal ps_busy : std_logic; + +begin + + PROC_DISSEC_CTR: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + dissect_ctr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( (DISSECT_CS = IDLE) and (PS_WR_EN_IN = '0') ) then + dissect_ctr <= (others => '0'); + elsif( (DISSECT_CS = WAIT_FOR_LOAD) or (DISSECT_CS = DELAY) ) then + dissect_ctr <= (others => '0'); + elsif( (DISSECT_CS = IDLE) and (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then -- first byte + dissect_ctr <= dissect_ctr + 1; + elsif( (DISSECT_CS = READ_FRAME) and (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then -- frame data + dissect_ctr <= dissect_ctr + 1; + elsif( (DISSECT_CS = LOAD_FRAME) and (TC_RD_EN_IN = '1') ) then -- reply frame data + dissect_ctr <= dissect_ctr + 1; + elsif( (DISSECT_CS = DO_HEADER) ) then -- header construction + dissect_ctr <= dissect_ctr + 1; + end if; + end if; + end process PROC_DISSEC_CTR; + + PROC_CRC: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( DISSECT_CS = IDLE ) then + crc_l(19 downto 0) <= (others => '0'); + crc_r(19 downto 0) <= (others => '0'); + crc_ll(15 downto 0) <= (others => '0'); + crc_rr(15 downto 0) <= (others => '0'); + crc_lll(15 downto 0) <= (others => '0'); + crc_rrr(15 downto 0) <= (others => '0'); + elsif( (DISSECT_CS = READ_FRAME) and (dissect_ctr > 3) ) then + case dissect_ctr(0) is + when '1' => + crc_l <= crc_l + unsigned(PS_DATA_IN(7 downto 0)); + when '0' => + crc_r <= crc_r + unsigned(PS_DATA_IN(7 downto 0)); + when others => + null; + end case; + end if; + + crc_ll <= x"0000" + crc_l(7 downto 0) + crc_r(19 downto 8); + crc_rr <= x"0000" + crc_r(7 downto 0) + crc_l(19 downto 8); + + crc_lll <= x"0000" + crc_ll(7 downto 0) + crc_rr(15 downto 8); + crc_rrr <= x"0000" + crc_rr(7 downto 0) + crc_ll(15 downto 8); + + end if; + end process PROC_CRC; + + crc(7 downto 0) <= not std_logic_vector(crc_rrr(7 downto 0) + crc_lll(15 downto 8)); + crc(15 downto 8) <= not std_logic_vector(crc_lll(7 downto 0) + crc_rrr(15 downto 8)); + + PROC_HDR_DATA: process( dissect_ctr, crc ) + begin + case dissect_ctr(1 downto 0) is + when b"00" => hdr_data <= '0' & x"00"; + when b"01" => hdr_data <= '0' & x"00"; + when b"10" => hdr_data <= '0' & crc(7 downto 0); + when b"11" => hdr_data <= '0' & crc(15 downto 8); + when others => hdr_data <= '0' & x"00"; + end case; + end process PROC_HDR_DATA; + + THE_RAM_DP_TRUE: entity work.ram_dp_true_2kx9 + port map( + DataInA => PS_DATA_IN, + DataInB => hdr_data, + AddressA => std_logic_vector(dissect_ctr), + AddressB => std_logic_vector(dissect_ctr), + ClockA => CLK, + ClockB => CLK, + ClockEnA => PS_ACTIVATE_IN, + ClockEnB => '1', + WrA => PS_WR_EN_IN, + WrB => hdr_wr, + ResetA => RESET, + ResetB => RESET, + QA => open, + QB => pl_data_x + ); + + pl_data <= pl_data_x when rising_edge(CLK); + + -- store transmit frame size + PROC_TC_CTR: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( DISSECT_CS = DELAY ) then + transmit_size <= b"00000" & dissect_ctr; + end if; + end if; + end process PROC_TC_CTR; + + -- state machine + PROC_DISSECT_FSM: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + DISSECT_CS <= IDLE; + hdr_wr <= '0'; + elsif( rising_edge(CLK) ) then + DISSECT_CS <= DISSECT_NS; + hdr_wr <= hdr_wr_x; + end if; + end process PROC_DISSECT_FSM; + + PROC_DISSECT_TRANSITIONS: process( DISSECT_CS, PS_WR_EN_IN, PS_SELECTED_IN, PS_ACTIVATE_IN, PS_FRAME_SIZE_IN, PS_DATA_IN, transmit_size, dissect_ctr ) + begin + hdr_wr_x <= '0'; + + case DISSECT_CS is + + when IDLE => + state <= x"0"; + if( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then + DISSECT_NS <= READ_FRAME; + else + DISSECT_NS <= IDLE; + end if; + + when READ_FRAME => + state <= x"1"; + if( dissect_ctr = unsigned(PS_FRAME_SIZE_IN) - 1 ) then + DISSECT_NS <= DELAY; + else + DISSECT_NS <= READ_FRAME; + end if; + + when DELAY => + state <= x"2"; + DISSECT_NS <= DO_HEADER; + hdr_wr_x <= '1'; + + when DO_HEADER => + state <= x"3"; + if( dissect_ctr = 3 ) then + DISSECT_NS <= WAIT_FOR_LOAD; + else + DISSECT_NS <= DO_HEADER; + hdr_wr_x <= '1'; + end if; + + when WAIT_FOR_LOAD => + state <= x"4"; + if( PS_SELECTED_IN = '1' ) then + DISSECT_NS <= LOAD_FRAME; + else + DISSECT_NS <= WAIT_FOR_LOAD; + end if; + + when LOAD_FRAME => + state <= x"5"; + if( dissect_ctr = transmit_size - 1 ) then + DISSECT_NS <= CLEANUP; + else + DISSECT_NS <= LOAD_FRAME; + end if; + + when CLEANUP => + state <= x"6"; + DISSECT_NS <= IDLE; + + when others => + state <= x"f"; + DISSECT_NS <= IDLE; + + end case; + end process PROC_DISSECT_TRANSITIONS; + + + PROC_PS_RESPONSE_SYNC: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( (DISSECT_CS = WAIT_FOR_LOAD) or (DISSECT_CS = LOAD_FRAME) or (DISSECT_CS = CLEANUP) ) then + ps_response_ready <= '1'; + else + ps_response_ready <= '0'; + end if; + + if( DISSECT_CS = IDLE ) then + ps_busy <= '0'; + else + ps_busy <= '1'; + end if; + end if; + end process PROC_PS_RESPONSE_SYNC; + + PS_RESPONSE_READY_OUT <= ps_response_ready; + PS_BUSY_OUT <= ps_busy; + + TC_DATA_OUT <= pl_data; + TC_FRAME_SIZE_OUT <= std_logic_vector(transmit_size); + TC_FRAME_TYPE_OUT <= x"0008"; + TC_DEST_UDP_OUT <= x"0000"; -- not used + TC_SRC_MAC_OUT <= MY_MAC_IN; + TC_SRC_IP_OUT <= MY_IP_IN; + TC_SRC_UDP_OUT <= x"0000"; -- not used + TC_IP_PROTOCOL_OUT <= X"01"; -- ICMP + TC_IDENT_OUT <= x"2" & std_logic_vector(sent_frames(11 downto 0)); + + PROC_ADDR: process( CLK ) + begin + if( rising_edge(CLK) ) then +-- if( DISSECT_CS = READ_FRAME ) then + if( DISSECT_CS = DELAY ) then + TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; + TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; + end if; + end if; + end process PROC_ADDR; + + PROC_SENT_FRAMES: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + sent_frames <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( DISSECT_CS = CLEANUP ) then + sent_frames <= sent_frames + 1; + end if; + end if; + end process PROC_SENT_FRAMES; + +end gbe_response_constructor_Ping_arch;