From: Manuel Penschuck Date: Thu, 16 Oct 2014 19:24:45 +0000 (+0200) Subject: CBMNet: Increase read-out buffer to 128 kb, TrbNet pattern generator for testing... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=de9f328a027f0371f0ddc74a0d21e4c728ab1731;p=trb3.git CBMNet: Increase read-out buffer to 128 kb, TrbNet pattern generator for testing the read-out in periph FPGA, small improvements and bug-fix to the bridge --- diff --git a/cbmnet/code/cbmnet_bridge.lpf b/cbmnet/code/cbmnet_bridge.lpf index e2bc63e..3652e26 100644 --- a/cbmnet/code/cbmnet_bridge.lpf +++ b/cbmnet/code/cbmnet_bridge.lpf @@ -23,25 +23,28 @@ DEFINE BUS cbmnet_bridge_tx_data PRIORITIZE BUS "cbmnet_bridge_rx_data" 100 ; PRIORITIZE BUS "cbmnet_bridge_tx_data" 100 ; -MULTICYCLE TO CELL "THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/delay_clock_buf_i" 2 X; +MULTICYCLE TO CELL "THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/delay_clock_crs_i" 2 X; -UGROUP "CBMNET_PHY_GROUP" BBOX 13 26 - BLKNAME THE_CBM_BRIDGE/THE_CBM_PHY; +UGROUP "CBMNET_PHY_GROUP" BBOX 24 30 +# BLKNAME THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR +# BLKNAME THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR + BLKNAME THE_CBM_BRIDGE/THE_CBM_PHY +; -UGROUP "CBMNET_BRIDGE_GROUP" BBOX 40 50 +UGROUP "CBMNET_BRIDGE_GROUP" BBOX 65 64 BLKNAME THE_CBM_BRIDGE/THE_CBMNET_READOUT BLKNAME THE_CBM_BRIDGE/THE_CBM_ENDPOINT BLKNAME THE_CBM_BRIDGE/THE_DLM_REFLECT BLKNAME THE_CBM_BRIDGE/THE_CBM_LINK_TESTER BLKNAME THE_CBM_BRIDGE/THE_SYNC_MODULE - BLKNAME THE_CBM_BRIDGE/THE_BUS_HANDLER; - -# while this signal is important, fsm are setup to handle large delays and PAR cannot get it right anyways -BLOCK PATH FROM CELL "THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/delay_clock_i" TO CELL "THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/delay_clock_crs_i"; + BLKNAME THE_CBM_BRIDGE/THE_BUS_HANDLER +; ######################################################## # TODO: Adopt placement to your design ! -#### - +######################################################## +#LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R105C110D"; +#LOCATE UGROUP "CBMNET_BRIDGE_GROUP" SITE "R76C85D"; +#LOCATE COMP "THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ; diff --git a/cbmnet/code/cbmnet_bridge.vhd b/cbmnet/code/cbmnet_bridge.vhd index 01cad2a..5440a39 100644 --- a/cbmnet/code/cbmnet_bridge.vhd +++ b/cbmnet/code/cbmnet_bridge.vhd @@ -412,7 +412,7 @@ begin CTRL_PADDING => 16#A5A5#, - OWN_ADDR => "1000000000000000", + OWN_ADDR => x"0000", DEST_ADDR => "0000000000000000", PACKET_MODE => 1 --if enabled generates another packet size order to test further corner cases ) port map ( @@ -468,7 +468,8 @@ begin TRB_RDO_DATA_OUT => TRB_RDO_DATA_OUT, -- out std_logic_vector(31 downto 0); TRB_RDO_WRITE_OUT => TRB_RDO_WRITE_OUT, -- out std_logic; TRB_RDO_FINISHED_OUT => TRB_RDO_FINISHED_OUT, -- out std_logic; - + TRB_RDO_STATUSBIT_OUT => open, + -- reg io TRB_REGIO_ADDR_IN(15 downto 4) => x"000", TRB_REGIO_ADDR_IN(3 downto 0) => cbm_sync_regio_addr_i, -- in std_logic_vector(15 downto 0); @@ -501,6 +502,7 @@ begin CBM_CTRL_DATA_END_IN => cbm_ctrl_rec_end_i, -- in std_logic; CBM_CTRL_DATA_STOP_OUT => cbm_ctrl_rec_stop_i, -- out std_logic; + DEBUG_OUT => open -- out std_logic_vector(31 downto 0) ); @@ -516,6 +518,8 @@ begin cbm_lt_data2send_stop_i <= (not cbm_data_mux_crs_i) or cbm_data2send_stop_i; cbm_rdo_data2send_stop_i <= cbm_data_mux_crs_i or cbm_data2send_stop_i; + cbm_data_rec_stop_i <= '1'; + THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => 3, @@ -526,7 +530,8 @@ begin CLK => TRB_CLK_IN, RESET => TRB_RESET_IN, - DAT_ADDR_IN => REGIO_ADDR_IN, + DAT_ADDR_IN(8 downto 0) => REGIO_ADDR_IN(8 downto 0), + DAT_ADDR_IN(15 downto 9) => (others => '0'), DAT_DATA_IN => REGIO_DATA_IN, DAT_DATA_OUT => REGIO_DATA_OUT, DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN, @@ -572,7 +577,9 @@ begin BUS_DATAREADY_IN(2) => cbm_sync_regio_read_ack_i, BUS_WRITE_ACK_IN(2) => cbm_sync_regio_write_ack_i, BUS_NO_MORE_DATA_IN(2) => '0', - BUS_UNKNOWN_ADDR_IN(2) => cbm_sync_regio_unknown_i + BUS_UNKNOWN_ADDR_IN(2) => cbm_sync_regio_unknown_i, + + stat_debug => open ); diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd index 3048d25..7bd2abc 100644 --- a/cbmnet/code/cbmnet_interface_pkg.vhd +++ b/cbmnet/code/cbmnet_interface_pkg.vhd @@ -89,6 +89,39 @@ package cbmnet_interface_pkg is REGIO_UNKNOWN_ADDR_OUT : out std_logic ); end component; + + component trbnet_rdo_pattern_generator is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + HUB_CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); + HUB_CTS_CODE_OUT : out std_logic_vector (7 downto 0); + HUB_CTS_OUTFORMATION_OUT : out std_logic_vector (7 downto 0); + HUB_CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + HUB_CTS_START_READOUT_OUT : out std_logic; + HUB_CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM + HUB_CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + HUB_FEE_DATA_OUT : out std_logic_vector (15 downto 0); + HUB_FEE_DATAREADY_OUT : out std_logic; + HUB_FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready + HUB_FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + HUB_FEE_BUSY_OUT : out std_logic; + + + REGIO_READ_ENABLE_IN : in std_logic; + REGIO_WRITE_ENABLE_IN : in std_logic; + REGIO_DATA_IN : in std_logic_vector (31 downto 0); + REGIO_ADDR_IN : in std_logic_vector (15 downto 0); + REGIO_TIMEOUT_IN : in std_logic; + REGIO_DATA_OUT : out std_logic_vector (31 downto 0); + REGIO_DATAREADY_OUT : out std_logic; + REGIO_WRITE_ACK_OUT : out std_logic; + REGIO_NO_MORE_DATA_OUT : out std_logic; + REGIO_UNKNOWN_ADDR_OUT : out std_logic + ); + end component; + constant K280 : std_logic_vector(7 downto 0) := "00011100"; diff --git a/cbmnet/code/cbmnet_phy_tx_gear.vhd b/cbmnet/code/cbmnet_phy_tx_gear.vhd index 2d41303..d8c4eb9 100644 --- a/cbmnet/code/cbmnet_phy_tx_gear.vhd +++ b/cbmnet/code/cbmnet_phy_tx_gear.vhd @@ -54,11 +54,6 @@ begin process is begin wait until rising_edge(CLK_250_IN); - data_in_buf250_0_i <= data_in_buf125_i; - data_in_buf250_i <= data_in_buf250_0_i; - - - clk_125_xfer_buf_i <= CLK_125_IN; clk_125_xfer_del_i <= clk_125_xfer_buf_i; CLK_125_OUT <= '0'; @@ -71,13 +66,7 @@ begin delay_data_i <= data_in_buf250_i(17) & data_in_buf250_i(15 downto 8); DATA_OUT <= data_in_buf250_i(16) & data_in_buf250_i( 7 downto 0); fsm_i <= FSM_LOW; - --- if clk_125_xfer_buf_i /= clk_125_xfer_del_i and ALLOW_RELOCK_IN = '1' then --- fsm_i <= FSM_HIGH; --- delay_counter_i <= delay_counter_i + 1; --- end if; - - + when FSM_LOW => fsm_i <= FSM_HIGH; @@ -100,5 +89,25 @@ begin data_in_buf125_i <= data_in_buf125_0_i; end process; + THE_DATA_SYNC: signal_sync + generic map (WIDTH => 18, DEPTH => 3) + port map ( + RESET => RESET_IN, + CLK0 => CLK_125_IN, + CLK1 => CLK_250_IN, + D_IN => DATA_IN, + D_OUT => data_in_buf250_i + ); + + THE_CLK_SYNC: signal_sync + generic map (WIDTH => 1, DEPTH => 3) + port map ( + RESET => RESET_IN, + CLK0 => CLK_250_IN, + CLK1 => CLK_250_IN, + D_IN(0) => CLK_125_IN, + D_OUT(0) => clk_125_xfer_buf_i + ); + DEBUG_OUT <= (others => '0'); -- x"0000" & STD_LOGIC_VECTOR( delay_counter_i ); end architecture CBMNET_PHY_TX_GEAR_ARCH; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_readout_fifo_ecp3.vhd b/cbmnet/code/cbmnet_readout_fifo_ecp3.vhd index cdf6b99..0754a29 100644 --- a/cbmnet/code/cbmnet_readout_fifo_ecp3.vhd +++ b/cbmnet/code/cbmnet_readout_fifo_ecp3.vhd @@ -41,7 +41,7 @@ end CBMNET_READOUT_FIFO; architecture cbmnet_readout_fifo_arch of CBMNET_READOUT_FIFO is constant FIFO_NUM_C : positive := 2; - component cbmnet_fifo_18x2k_dp is + component cbmnet_fifo_18x32k_dp is port ( Data: in std_logic_vector(17 downto 0); WrClock: in std_logic; @@ -51,13 +51,13 @@ architecture cbmnet_readout_fifo_arch of CBMNET_READOUT_FIFO is Reset: in std_logic; RPReset: in std_logic; Q: out std_logic_vector(17 downto 0); - WCNT: out std_logic_vector(11 downto 0); Empty: out std_logic; Full: out std_logic; AlmostFull: out std_logic ); end component; + signal rread_fifo_i, wread_fifo_i, rwrite_fifo_i, wwrite_fifo_i : integer range 0 to FIFO_NUM_C-1; signal fifo_enqueue_i : std_logic_vector(FIFO_NUM_C-1 downto 0); @@ -67,7 +67,7 @@ architecture cbmnet_readout_fifo_arch of CBMNET_READOUT_FIFO is signal fifo_almost_full_i : std_logic_vector(FIFO_NUM_C-1 downto 0); signal fifo_data_i : std_logic_vector(FIFO_NUM_C*18 - 1 downto 0); - signal fifo_wcount_i : std_logic_vector(FIFO_NUM_C*12 - 1 downto 0); + signal fifo_wcount_i : std_logic_vector(FIFO_NUM_C*16 - 1 downto 0); signal fifo_reset_i : std_logic_vector(FIFO_NUM_C - 1 downto 0); signal fifo_rreset_i : std_logic_vector(FIFO_NUM_C - 1 downto 0); @@ -253,7 +253,7 @@ begin GEN_FIFOS: for i in 0 to FIFO_NUM_C-1 generate - THE_FIFO: cbmnet_fifo_18x2k_dp + THE_FIFO: cbmnet_fifo_18x32k_dp port map ( Data => WDATA_IN, -- in std_logic_vector(17 downto 0); WrClock => WCLK_IN, -- in std_logic; @@ -263,7 +263,6 @@ begin Reset => fifo_wreset_i(i), -- in std_logic; RPReset => fifo_rreset_i(i), -- in std_logic; Q => fifo_data_i(17 + 18*i downto 18*i), -- out std_logic_vector(17 downto 0); - WCNT => open, -- out std_logic_vector(11 downto 0); Empty => fifo_empty_i(i), -- out std_logic; Full => fifo_full_i(i), -- out std_logic; AlmostFull => fifo_almost_full_i(i) -- out std_logic diff --git a/cbmnet/code/cbmnet_readout_frame_packer.vhd b/cbmnet/code/cbmnet_readout_frame_packer.vhd index fa59526..4aff007 100644 --- a/cbmnet/code/cbmnet_readout_frame_packer.vhd +++ b/cbmnet/code/cbmnet_readout_frame_packer.vhd @@ -114,7 +114,7 @@ begin remaining_words_to_dequeue_i(14 downto 0) <= UNSIGNED(fifo_data_i(15 downto 1)) - TO_UNSIGNED(1, 15); assert(fifo_token_i = "10") report "Invalid LENGTH_L token" severity failure; assert(to_integer(UNSIGNED(fifo_data_i)) >= 24) report "TrbNet packet too short. Expect minimal length of 24 bytes." severity failure; - assert(to_integer(UNSIGNED(fifo_data_i)) < 4096) report "TrbNet packet too long. This module should support sending of transactions with upto 32kb data, but only 4kb transactions have been specified and tested" severity failure; + assert(to_integer(UNSIGNED(fifo_data_i)) < 35536) report "TrbNet packet too long." severity failure; fsm_i <= FIRST_FRAME_SEND_HDR; when FIRST_FRAME_SEND_HDR => diff --git a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd index 8baba44..be699cb 100644 --- a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd +++ b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd @@ -50,7 +50,7 @@ architecture cbmnet_readout_trbnet_decoder_arch of CBMNET_READOUT_TRBNET_DECODER signal data_i : std_logic_vector(15 downto 0); signal dec_evt_info_i : std_logic_vector(31 downto 0); - signal dec_length_i : std_logic_vector(15 downto 0); + signal dec_length_i : std_logic_vector(15 downto 0); -- in bytes ! signal dec_source_i : std_logic_vector(15 downto 0); signal dec_error_i : std_logic; diff --git a/cbmnet/code/cbmnet_sync_module.vhd b/cbmnet/code/cbmnet_sync_module.vhd index cc95831..be96d82 100644 --- a/cbmnet/code/cbmnet_sync_module.vhd +++ b/cbmnet/code/cbmnet_sync_module.vhd @@ -241,6 +241,7 @@ begin begin wait until rising_edge(CBM_CLK_IN); + CBM_TIMING_TRIGGER_OUT <= '0'; if CBM_RESET_IN='1' or cbm_from_trb_reset_in ='1' then cbm_trb_rdo_fsm_i <= IDLE; @@ -250,7 +251,7 @@ begin case (cbm_trb_rdo_fsm_i) is when IDLE => - if cbm_from_trb_trigger_buf_in = '1' then + if cbm_from_trb_trigger_in = '1' then CBM_TIMING_TRIGGER_OUT <= '1'; end if; diff --git a/cbmnet/code/trbnet_rdo_pattern_generator.vhd b/cbmnet/code/trbnet_rdo_pattern_generator.vhd new file mode 100644 index 0000000..0d66f50 --- /dev/null +++ b/cbmnet/code/trbnet_rdo_pattern_generator.vhd @@ -0,0 +1,276 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity trbnet_rdo_pattern_generator is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + HUB_CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); + HUB_CTS_CODE_OUT : out std_logic_vector (7 downto 0); + HUB_CTS_OUTFORMATION_OUT : out std_logic_vector (7 downto 0); + HUB_CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + HUB_CTS_START_READOUT_OUT : out std_logic; + HUB_CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM + HUB_CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + HUB_FEE_DATA_OUT : out std_logic_vector (15 downto 0); + HUB_FEE_DATAREADY_OUT : out std_logic; + HUB_FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready + HUB_FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + HUB_FEE_BUSY_OUT : out std_logic; + + + REGIO_READ_ENABLE_IN : in std_logic; + REGIO_WRITE_ENABLE_IN : in std_logic; + REGIO_DATA_IN : in std_logic_vector (31 downto 0); + REGIO_ADDR_IN : in std_logic_vector (15 downto 0); + REGIO_TIMEOUT_IN : in std_logic; + REGIO_DATA_OUT : out std_logic_vector (31 downto 0); + REGIO_DATAREADY_OUT : out std_logic; + REGIO_WRITE_ACK_OUT : out std_logic; + REGIO_NO_MORE_DATA_OUT : out std_logic; + REGIO_UNKNOWN_ADDR_OUT : out std_logic + ); +end entity; + +architecture trbnet_rdo_pattern_generator_arch of trbnet_rdo_pattern_generator is + type TRB_FSM_T is ( + IDLE, START_READOUT, START_READOUT_WAIT, FEE_BUSY, + SEND_EINF_H, SEND_EINF_L, + SEND_LENGTH, SEND_SOURCE, SEND_SOURCE_WAIT, + SEND_PAYLOAD_SSEHDR_H, SEND_PAYLOAD_SSEHDR_L, + SEND_PAYLOAD_RT_H, SEND_PAYLOAD_RT_L, + SEND_PAYLOAD_H, SEND_PAYLOAD_L, + COMPL_WAIT, COMPL_NOT_BUSY_WAIT, EVT_WAIT + ); + signal trb_fsm_i : TRB_FSM_T; + + signal send_enabled_i : std_logic; + + signal event_id : unsigned(31 downto 0); + signal event_gap_i : unsigned(31 downto 0); + signal event_gap_cnt_i : unsigned(31 downto 0); + + signal send_length_min_i : unsigned(15 downto 0); + signal send_length_max_i : unsigned(15 downto 0); + signal send_length_step_i : unsigned(15 downto 0); + signal send_length_cnt_i : unsigned(15 downto 0); + + signal send_counter_i : unsigned(15 downto 0); + +begin + PROC_PGEN_REGIO: process is + variable address : integer; + begin + wait until rising_edge(CLK_IN); + + address := to_integer(UNSIGNED(REGIO_ADDR_IN(3 downto 0))); + + REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; + REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN; + REGIO_UNKNOWN_ADDR_OUT <= '0'; + REGIO_NO_MORE_DATA_OUT <= '0'; + REGIO_DATA_OUT <= (others => '0'); + + if RESET_IN = '1' then + send_length_min_i <= x"0010"; + send_length_max_i <= x"0800"; + send_length_step_i <= x"0001"; + send_enabled_i <= '0'; + event_gap_i <= x"00001000"; + + else + case address is + when 0 => + REGIO_DATA_OUT(0) <= send_enabled_i; + + when 1 => REGIO_DATA_OUT(15 downto 0) <= send_length_min_i; + when 2 => REGIO_DATA_OUT(15 downto 0) <= send_length_max_i; + when 3 => REGIO_DATA_OUT(15 downto 0) <= send_length_step_i; + when 4 => REGIO_DATA_OUT <= event_id; + when 5 => REGIO_DATA_OUT <= event_gap_i; + + when others => + REGIO_UNKNOWN_ADDR_OUT <= REGIO_WRITE_ENABLE_IN or REGIO_READ_ENABLE_IN; + + end case; + + if REGIO_WRITE_ENABLE_IN = '1' then + case address is + when 0 => send_enabled_i <= REGIO_DATA_IN(0); + when 1 => send_length_min_i <= REGIO_DATA_IN(15 downto 0); + when 2 => send_length_max_i <= REGIO_DATA_IN(15 downto 0); + when 3 => send_length_step_i <= REGIO_DATA_IN(15 downto 0); + when 5 => event_gap_i <= REGIO_DATA_IN; + + when others => + REGIO_WRITE_ACK_OUT <= '0'; + + end case; + end if; + end if; + end process; + + + PROC_TRB_DATA: process is + variable wait_cnt_v : integer range 0 to 15 := 0; + begin + wait until rising_edge(CLK_IN); + + HUB_CTS_START_READOUT_OUT <= '1'; + HUB_FEE_BUSY_OUT <= '1'; + HUB_FEE_DATAREADY_OUT <= '0'; + + if RESET_IN='1' then + trb_fsm_i <= IDLE; + else + case(trb_fsm_i) is + when IDLE => + HUB_CTS_START_READOUT_OUT <= '0'; + HUB_FEE_BUSY_OUT <= '0'; + if send_enabled_i = '1' then + trb_fsm_i <= START_READOUT; + end if; + + if send_length_cnt_i < send_length_min_i then + send_length_cnt_i <= send_length_min_i; + else + send_length_cnt_i <= send_length_cnt_i + 1; + end if; + + when START_READOUT => + if send_length_cnt_i < send_length_min_i or send_length_cnt_i > send_length_max_i then + send_length_cnt_i <= send_length_min_i; + end if; + + trb_fsm_i <= START_READOUT_WAIT; + wait_cnt_v := 10; + HUB_FEE_BUSY_OUT <= '0'; + event_id <= event_id + 1; + + when START_READOUT_WAIT => + if wait_cnt_v = 0 then + trb_fsm_i <= FEE_BUSY; + wait_cnt_v := 5; + else + wait_cnt_v := wait_cnt_v - 1; + end if; + + HUB_FEE_BUSY_OUT <= '0'; + + when FEE_BUSY => + if wait_cnt_v = 0 then + trb_fsm_i <= SEND_EINF_H; + else + wait_cnt_v := wait_cnt_v - 1; + end if; + + HUB_FEE_BUSY_OUT <= '1'; + + when SEND_EINF_H => + HUB_FEE_DATA_OUT <= x"0e" & STD_LOGIC_VECTOR(event_id(23 downto 16)); + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_EINF_L; + when SEND_EINF_L => + HUB_FEE_DATA_OUT <= std_logic_vector(event_id(15 downto 0)); + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_LENGTH; + + when SEND_LENGTH => + HUB_FEE_DATA_OUT <= std_logic_vector(send_length_cnt_i); + send_counter_i <= send_length_cnt_i; + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_SOURCE; + when SEND_SOURCE => + HUB_FEE_DATA_OUT <= x"affe"; + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_SOURCE_WAIT; + + when SEND_SOURCE_WAIT => + trb_fsm_i <= SEND_PAYLOAD_SSEHDR_H; + + when SEND_PAYLOAD_SSEHDR_H => + HUB_FEE_DATA_OUT <= std_logic_vector(send_counter_i - 1); + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_PAYLOAD_SSEHDR_L; + + when SEND_PAYLOAD_SSEHDR_L => + HUB_FEE_DATA_OUT <= x"4444"; + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_PAYLOAD_H; + send_counter_i <= send_counter_i - 1; + + trb_fsm_i <= SEND_PAYLOAD_RT_H; + + when SEND_PAYLOAD_RT_H => + HUB_FEE_DATA_OUT <= x"dead"; + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_PAYLOAD_RT_L; + + when SEND_PAYLOAD_RT_L => + HUB_FEE_DATA_OUT <= x"c0de"; + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_PAYLOAD_H; + send_counter_i <= send_counter_i - 1; + + if send_counter_i = 1 then + trb_fsm_i <= COMPL_WAIT; + wait_cnt_v := 5; + end if; + + when SEND_PAYLOAD_H => + HUB_FEE_DATA_OUT <= x"bb" & std_logic_vector(event_id(7 downto 0)); + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_PAYLOAD_L; + + when SEND_PAYLOAD_L => + HUB_FEE_DATA_OUT <= x"c" & std_logic_vector(send_counter_i(11 downto 0)); + HUB_FEE_DATAREADY_OUT <= '1'; + trb_fsm_i <= SEND_PAYLOAD_H; + send_counter_i <= send_counter_i - 1; + + if send_counter_i = 1 then + trb_fsm_i <= COMPL_WAIT; + wait_cnt_v := 5; + end if; + + when COMPL_WAIT => + if wait_cnt_v = 0 then + wait_cnt_v := 5; + trb_fsm_i <= COMPL_NOT_BUSY_WAIT; + else + wait_cnt_v := wait_cnt_v - 1; + end if; + + HUB_FEE_BUSY_OUT <= '1'; + + + when COMPL_NOT_BUSY_WAIT => + HUB_CTS_START_READOUT_OUT <= '0'; + if wait_cnt_v = 0 then + trb_fsm_i <= EVT_WAIT; + wait_cnt_v := 5; + else + wait_cnt_v := wait_cnt_v - 1; + end if; + + HUB_FEE_BUSY_OUT <= '0'; + event_gap_cnt_i <= (others => '0'); + + + when EVT_WAIT => + HUB_CTS_START_READOUT_OUT <= '0'; + HUB_FEE_BUSY_OUT <= '0'; + + event_gap_cnt_i <= event_gap_cnt_i + 1; + + if event_gap_cnt_i >= UNSIGNED(event_gap_i) then + trb_fsm_i <= IDLE; + end if; + + end case; + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/cbmnet/compile_constraints.pl b/cbmnet/compile_constraints.pl index c54ae42..c22932b 100755 --- a/cbmnet/compile_constraints.pl +++ b/cbmnet/compile_constraints.pl @@ -32,4 +32,5 @@ symlink "$back/../../base/cores/cbmnet_sfp1.txt", 'cbmnet_sfp1.txt'; chdir($script_dir); system("cp ../base/$TOPNAME.lpf $workdir/$TOPNAME.lpf"); +system("cat ./code/cbmnet_bridge.lpf >> $workdir/$TOPNAME.lpf"); system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf"); diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl index 2dca5f1..7cb13d4 100755 --- a/cbmnet/compile_periph_frankfurt.pl +++ b/cbmnet/compile_periph_frankfurt.pl @@ -109,7 +109,7 @@ execute($c); my $tpmap = $TOPNAME . "_map" ; -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/map -hier -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; execute($c); @@ -123,10 +123,10 @@ $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); # TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/trce -p -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/trce -p -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; diff --git a/cbmnet/cores/cbmnet_fifo_18x32k_dp.edn b/cbmnet/cores/cbmnet_fifo_18x32k_dp.edn new file mode 100644 index 0000000..0e87104 --- /dev/null +++ b/cbmnet/cores/cbmnet_fifo_18x32k_dp.edn @@ -0,0 +1,10420 @@ +(edif cbmnet_fifo_18x32k_dp + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2014 10 15 12 28 36) + (program "SCUBA" (version "Diamond (64-bit) 3.2.0.134")))) + (comment "/d/jspc29/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n cbmnet_fifo_18x32k_dp -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 18 -regout -no_enable -pe -1 -pf 32760 -pf2 506 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell AGEB2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port GE + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell CU2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT)) + (port PC0 + (direction INPUT)) + (port PC1 + (direction INPUT)) + (port CO + (direction OUTPUT)) + (port NC0 + (direction OUTPUT)) + (port NC1 + (direction OUTPUT))))) + (cell FADD2B + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port CI + (direction INPUT)) + (port COUT + (direction OUTPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell MUX161 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port D2 + (direction INPUT)) + (port D3 + (direction INPUT)) + (port D4 + (direction INPUT)) + (port D5 + (direction INPUT)) + (port D6 + (direction INPUT)) + (port D7 + (direction INPUT)) + (port D8 + (direction INPUT)) + (port D9 + (direction INPUT)) + (port D10 + (direction INPUT)) + (port D11 + (direction INPUT)) + (port D12 + (direction INPUT)) + (port D13 + (direction INPUT)) + (port D14 + (direction INPUT)) + (port D15 + (direction INPUT)) + (port SD1 + (direction INPUT)) + (port SD2 + (direction INPUT)) + (port SD3 + (direction INPUT)) + (port SD4 + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell OR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA0 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA17 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA13 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB9 + (direction INPUT)) + (port DIB10 + (direction INPUT)) + (port DIB11 + (direction INPUT)) + (port DIB12 + (direction INPUT)) + (port DIB13 + (direction INPUT)) + (port DIB14 + (direction INPUT)) + (port DIB15 + (direction INPUT)) + (port DIB16 + (direction INPUT)) + (port DIB17 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB13 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA9 + (direction OUTPUT)) + (port DOA10 + (direction OUTPUT)) + (port DOA11 + (direction OUTPUT)) + (port DOA12 + (direction OUTPUT)) + (port DOA13 + (direction OUTPUT)) + (port DOA14 + (direction OUTPUT)) + (port DOA15 + (direction OUTPUT)) + (port DOA16 + (direction OUTPUT)) + (port DOA17 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB9 + (direction OUTPUT)) + (port DOB10 + (direction OUTPUT)) + (port DOB11 + (direction OUTPUT)) + (port DOB12 + (direction OUTPUT)) + (port DOB13 + (direction OUTPUT)) + (port DOB14 + (direction OUTPUT)) + (port DOB15 + (direction OUTPUT)) + (port DOB16 + (direction OUTPUT)) + (port DOB17 + (direction OUTPUT))))) + (cell cbmnet_fifo_18x32k_dp + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(17:0)") 18) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port RPReset + (direction INPUT)) + (port (array (rename Q "Q(17:0)") 18) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t32 + (viewRef view1 + (cellRef AND2))) + (instance INV_9 + (viewRef view1 + (cellRef INV))) + (instance AND2_t31 + (viewRef view1 + (cellRef AND2))) + (instance INV_8 + (viewRef view1 + (cellRef INV))) + (instance OR2_t30 + (viewRef view1 + (cellRef OR2))) + (instance XOR2_t29 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t28 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t27 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t26 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t25 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t24 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t23 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t22 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t21 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t20 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t19 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t18 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t17 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t16 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t15 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t14 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t13 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t12 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t11 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t10 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t9 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t8 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t7 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t6 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t5 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t4 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t3 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t1 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_7 + (viewRef view1 + (cellRef INV))) + (instance INV_6 + (viewRef view1 + (cellRef INV))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance LUT4_114 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance LUT4_113 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_112 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_111 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_110 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_109 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_108 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_107 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_106 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_105 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_104 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_103 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_102 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_101 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_100 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_99 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_98 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_97 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_96 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_95 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_94 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_93 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_92 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_91 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_90 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_89 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_88 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_87 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_86 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_85 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_84 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_83 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_82 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_81 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_80 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_79 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_78 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_77 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_76 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_75 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_74 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_73 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_72 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_71 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_70 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_69 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_68 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_67 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_66 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_65 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_64 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_63 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_62 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_61 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_60 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_59 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_58 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_57 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_56 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_55 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_54 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_53 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_52 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_51 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_50 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_49 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_48 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_47 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_46 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_45 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_44 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_43 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_42 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_41 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_40 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_39 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_38 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_37 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_36 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_35 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_34 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_33 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_32 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_31 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_30 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_29 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_28 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_27 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_26 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_25 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_24 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_23 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_22 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_21 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_20 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_19 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_18 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_17 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_16 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_15 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_14 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_13 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_12 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_11 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_10 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_9 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x6996"))) + (instance LUT4_8 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x0410"))) + (instance LUT4_7 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x1004"))) + (instance LUT4_6 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x0140"))) + (instance LUT4_5 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4001"))) + (instance LUT4_4 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4c32"))) + (instance LUT4_3 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8001"))) + (instance LUT4_2 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4c32"))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8001"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x4450"))) + (instance pdp_ram_0_0_31 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_1_30 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_0_29 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_1_28 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_0_27 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_1_26 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_0_25 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_1_24 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_0_23 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_1_22 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_0_21 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_1_20 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_0_19 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_1_18 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_0_17 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_1_16 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_8_0_15 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_8_1_14 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_9_0_13 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_9_1_12 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_10_0_11 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_10_1_10 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_11_0_9 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_11_1_8 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_12_0_7 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_12_1_6 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_13_0_5 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_13_1_4 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_14_0_3 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_14_1_2 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_15_0_1 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_15_1_0 + (viewRef view1 + (cellRef DP16KC)) + (property MEM_LPC_FILE + (string "cbmnet_fifo_18x32k_dp.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "DISABLED")) + (property RESETMODE + (string "SYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_202 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_201 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_200 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_199 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_198 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_197 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_196 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_195 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_194 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_193 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_192 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_191 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_190 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_189 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_188 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_187 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_186 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_185 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_184 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_183 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_182 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_181 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_180 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_179 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_178 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_177 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_176 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_175 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_174 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_173 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_172 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_171 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_170 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_169 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_168 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_167 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_166 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_165 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_164 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_163 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_162 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_161 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_160 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_159 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_158 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_157 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_156 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_155 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_154 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_153 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_152 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_151 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_150 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_149 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_148 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_147 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_146 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_145 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_144 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_143 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_142 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_141 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_140 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_139 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_138 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_137 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_136 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_135 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_134 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_133 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_132 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_131 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_130 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_129 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_128 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_127 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_126 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_125 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_124 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_123 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_122 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_121 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_120 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_119 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_118 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_117 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_116 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_115 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_114 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_113 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_112 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_111 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_110 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_109 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_108 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_107 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_106 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_105 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_104 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_103 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_102 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_101 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_100 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_99 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_98 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_97 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_96 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_95 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_94 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_93 + 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pdp_ram_0_1_30)) + (portRef DIB6 (instanceRef pdp_ram_0_1_30)) + (portRef DIB5 (instanceRef pdp_ram_0_1_30)) + (portRef DIB4 (instanceRef pdp_ram_0_1_30)) + (portRef DIB3 (instanceRef pdp_ram_0_1_30)) + (portRef DIB2 (instanceRef pdp_ram_0_1_30)) + (portRef DIB1 (instanceRef pdp_ram_0_1_30)) + (portRef DIB0 (instanceRef pdp_ram_0_1_30)) + (portRef CSB2 (instanceRef pdp_ram_1_0_29)) + (portRef CSA2 (instanceRef pdp_ram_1_0_29)) + (portRef CSB1 (instanceRef pdp_ram_1_0_29)) + (portRef CSA1 (instanceRef pdp_ram_1_0_29)) + (portRef WEB (instanceRef pdp_ram_1_0_29)) + (portRef ADB2 (instanceRef pdp_ram_1_0_29)) + (portRef ADA2 (instanceRef pdp_ram_1_0_29)) + (portRef ADB1 (instanceRef pdp_ram_1_0_29)) + (portRef ADA1 (instanceRef pdp_ram_1_0_29)) + (portRef ADB0 (instanceRef pdp_ram_1_0_29)) + (portRef ADA0 (instanceRef pdp_ram_1_0_29)) + (portRef DIB17 (instanceRef pdp_ram_1_0_29)) + (portRef DIA17 (instanceRef pdp_ram_1_0_29)) + (portRef DIB16 (instanceRef pdp_ram_1_0_29)) + (portRef DIA16 (instanceRef pdp_ram_1_0_29)) + (portRef DIB15 (instanceRef pdp_ram_1_0_29)) + (portRef DIA15 (instanceRef pdp_ram_1_0_29)) + (portRef DIB14 (instanceRef pdp_ram_1_0_29)) + (portRef DIA14 (instanceRef pdp_ram_1_0_29)) + (portRef DIB13 (instanceRef pdp_ram_1_0_29)) + (portRef DIA13 (instanceRef pdp_ram_1_0_29)) + (portRef DIB12 (instanceRef pdp_ram_1_0_29)) + (portRef DIA12 (instanceRef pdp_ram_1_0_29)) + (portRef DIB11 (instanceRef pdp_ram_1_0_29)) + (portRef DIA11 (instanceRef pdp_ram_1_0_29)) + (portRef DIB10 (instanceRef pdp_ram_1_0_29)) + (portRef DIA10 (instanceRef pdp_ram_1_0_29)) + (portRef DIB9 (instanceRef pdp_ram_1_0_29)) + (portRef DIA9 (instanceRef pdp_ram_1_0_29)) + (portRef DIB8 (instanceRef pdp_ram_1_0_29)) + (portRef DIB7 (instanceRef pdp_ram_1_0_29)) + (portRef DIB6 (instanceRef pdp_ram_1_0_29)) + (portRef DIB5 (instanceRef pdp_ram_1_0_29)) + (portRef DIB4 (instanceRef pdp_ram_1_0_29)) + (portRef DIB3 (instanceRef pdp_ram_1_0_29)) + (portRef DIB2 (instanceRef pdp_ram_1_0_29)) + (portRef DIB1 (instanceRef pdp_ram_1_0_29)) + (portRef DIB0 (instanceRef pdp_ram_1_0_29)) + (portRef CSB2 (instanceRef pdp_ram_1_1_28)) + (portRef CSA2 (instanceRef pdp_ram_1_1_28)) + (portRef CSB1 (instanceRef pdp_ram_1_1_28)) + (portRef CSA1 (instanceRef pdp_ram_1_1_28)) + (portRef WEB (instanceRef pdp_ram_1_1_28)) + (portRef ADB2 (instanceRef pdp_ram_1_1_28)) + (portRef ADA2 (instanceRef pdp_ram_1_1_28)) + (portRef ADB1 (instanceRef pdp_ram_1_1_28)) + (portRef ADA1 (instanceRef pdp_ram_1_1_28)) + (portRef ADB0 (instanceRef pdp_ram_1_1_28)) + (portRef ADA0 (instanceRef pdp_ram_1_1_28)) + (portRef DIB17 (instanceRef pdp_ram_1_1_28)) + (portRef DIA17 (instanceRef pdp_ram_1_1_28)) + (portRef DIB16 (instanceRef pdp_ram_1_1_28)) + (portRef DIA16 (instanceRef pdp_ram_1_1_28)) + (portRef DIB15 (instanceRef pdp_ram_1_1_28)) + (portRef DIA15 (instanceRef pdp_ram_1_1_28)) + (portRef DIB14 (instanceRef pdp_ram_1_1_28)) + (portRef DIA14 (instanceRef pdp_ram_1_1_28)) + (portRef DIB13 (instanceRef pdp_ram_1_1_28)) + (portRef DIA13 (instanceRef pdp_ram_1_1_28)) + (portRef DIB12 (instanceRef pdp_ram_1_1_28)) + (portRef DIA12 (instanceRef pdp_ram_1_1_28)) + (portRef DIB11 (instanceRef pdp_ram_1_1_28)) + (portRef DIA11 (instanceRef pdp_ram_1_1_28)) + (portRef DIB10 (instanceRef pdp_ram_1_1_28)) + (portRef DIA10 (instanceRef pdp_ram_1_1_28)) + (portRef DIB9 (instanceRef pdp_ram_1_1_28)) + (portRef DIA9 (instanceRef pdp_ram_1_1_28)) + (portRef DIB8 (instanceRef pdp_ram_1_1_28)) + (portRef DIB7 (instanceRef pdp_ram_1_1_28)) + (portRef DIB6 (instanceRef pdp_ram_1_1_28)) + (portRef DIB5 (instanceRef pdp_ram_1_1_28)) + (portRef DIB4 (instanceRef pdp_ram_1_1_28)) + (portRef DIB3 (instanceRef pdp_ram_1_1_28)) + (portRef DIB2 (instanceRef pdp_ram_1_1_28)) + (portRef DIB1 (instanceRef pdp_ram_1_1_28)) + (portRef DIB0 (instanceRef pdp_ram_1_1_28)) + (portRef CSB2 (instanceRef pdp_ram_2_0_27)) + (portRef CSA2 (instanceRef pdp_ram_2_0_27)) + (portRef CSB1 (instanceRef pdp_ram_2_0_27)) + (portRef CSA1 (instanceRef pdp_ram_2_0_27)) + (portRef WEB (instanceRef pdp_ram_2_0_27)) + (portRef ADB2 (instanceRef pdp_ram_2_0_27)) + (portRef ADA2 (instanceRef pdp_ram_2_0_27)) + (portRef ADB1 (instanceRef pdp_ram_2_0_27)) + (portRef ADA1 (instanceRef pdp_ram_2_0_27)) + (portRef ADB0 (instanceRef pdp_ram_2_0_27)) + (portRef ADA0 (instanceRef pdp_ram_2_0_27)) + (portRef DIB17 (instanceRef pdp_ram_2_0_27)) + (portRef DIA17 (instanceRef pdp_ram_2_0_27)) + (portRef DIB16 (instanceRef pdp_ram_2_0_27)) + (portRef DIA16 (instanceRef pdp_ram_2_0_27)) + (portRef DIB15 (instanceRef pdp_ram_2_0_27)) + (portRef DIA15 (instanceRef pdp_ram_2_0_27)) + (portRef DIB14 (instanceRef pdp_ram_2_0_27)) + (portRef DIA14 (instanceRef pdp_ram_2_0_27)) + (portRef DIB13 (instanceRef pdp_ram_2_0_27)) + (portRef DIA13 (instanceRef pdp_ram_2_0_27)) + (portRef DIB12 (instanceRef pdp_ram_2_0_27)) + (portRef DIA12 (instanceRef pdp_ram_2_0_27)) + (portRef DIB11 (instanceRef pdp_ram_2_0_27)) + (portRef DIA11 (instanceRef pdp_ram_2_0_27)) + (portRef DIB10 (instanceRef pdp_ram_2_0_27)) + (portRef DIA10 (instanceRef pdp_ram_2_0_27)) + (portRef DIB9 (instanceRef pdp_ram_2_0_27)) + (portRef DIA9 (instanceRef pdp_ram_2_0_27)) + (portRef DIB8 (instanceRef pdp_ram_2_0_27)) + (portRef DIB7 (instanceRef pdp_ram_2_0_27)) + (portRef DIB6 (instanceRef pdp_ram_2_0_27)) + (portRef DIB5 (instanceRef pdp_ram_2_0_27)) + (portRef DIB4 (instanceRef pdp_ram_2_0_27)) + (portRef DIB3 (instanceRef pdp_ram_2_0_27)) + (portRef DIB2 (instanceRef pdp_ram_2_0_27)) + (portRef DIB1 (instanceRef pdp_ram_2_0_27)) + (portRef DIB0 (instanceRef pdp_ram_2_0_27)) + (portRef CSB2 (instanceRef pdp_ram_2_1_26)) + (portRef CSA2 (instanceRef pdp_ram_2_1_26)) + (portRef CSB1 (instanceRef pdp_ram_2_1_26)) + (portRef CSA1 (instanceRef pdp_ram_2_1_26)) + (portRef WEB (instanceRef pdp_ram_2_1_26)) + (portRef ADB2 (instanceRef pdp_ram_2_1_26)) + (portRef ADA2 (instanceRef pdp_ram_2_1_26)) + (portRef ADB1 (instanceRef pdp_ram_2_1_26)) + (portRef ADA1 (instanceRef pdp_ram_2_1_26)) + (portRef ADB0 (instanceRef pdp_ram_2_1_26)) + (portRef ADA0 (instanceRef pdp_ram_2_1_26)) + (portRef DIB17 (instanceRef pdp_ram_2_1_26)) + (portRef DIA17 (instanceRef pdp_ram_2_1_26)) + (portRef DIB16 (instanceRef pdp_ram_2_1_26)) + (portRef DIA16 (instanceRef pdp_ram_2_1_26)) + (portRef DIB15 (instanceRef pdp_ram_2_1_26)) + (portRef DIA15 (instanceRef pdp_ram_2_1_26)) + (portRef DIB14 (instanceRef pdp_ram_2_1_26)) + (portRef DIA14 (instanceRef pdp_ram_2_1_26)) + (portRef DIB13 (instanceRef pdp_ram_2_1_26)) + (portRef DIA13 (instanceRef pdp_ram_2_1_26)) + (portRef DIB12 (instanceRef pdp_ram_2_1_26)) + (portRef DIA12 (instanceRef pdp_ram_2_1_26)) + (portRef DIB11 (instanceRef pdp_ram_2_1_26)) + (portRef DIA11 (instanceRef pdp_ram_2_1_26)) + (portRef DIB10 (instanceRef pdp_ram_2_1_26)) + (portRef DIA10 (instanceRef pdp_ram_2_1_26)) + (portRef DIB9 (instanceRef pdp_ram_2_1_26)) + (portRef DIA9 (instanceRef pdp_ram_2_1_26)) + (portRef DIB8 (instanceRef pdp_ram_2_1_26)) + (portRef DIB7 (instanceRef pdp_ram_2_1_26)) + (portRef DIB6 (instanceRef pdp_ram_2_1_26)) + (portRef DIB5 (instanceRef pdp_ram_2_1_26)) + (portRef DIB4 (instanceRef pdp_ram_2_1_26)) + (portRef DIB3 (instanceRef pdp_ram_2_1_26)) + (portRef DIB2 (instanceRef pdp_ram_2_1_26)) + (portRef DIB1 (instanceRef pdp_ram_2_1_26)) + (portRef DIB0 (instanceRef pdp_ram_2_1_26)) + (portRef CSB2 (instanceRef pdp_ram_3_0_25)) + (portRef CSA2 (instanceRef pdp_ram_3_0_25)) + (portRef CSB1 (instanceRef pdp_ram_3_0_25)) + (portRef CSA1 (instanceRef pdp_ram_3_0_25)) + (portRef WEB (instanceRef pdp_ram_3_0_25)) + (portRef ADB2 (instanceRef pdp_ram_3_0_25)) + (portRef ADA2 (instanceRef pdp_ram_3_0_25)) + (portRef ADB1 (instanceRef pdp_ram_3_0_25)) + (portRef ADA1 (instanceRef pdp_ram_3_0_25)) + (portRef ADB0 (instanceRef pdp_ram_3_0_25)) + (portRef ADA0 (instanceRef pdp_ram_3_0_25)) + (portRef DIB17 (instanceRef pdp_ram_3_0_25)) + (portRef DIA17 (instanceRef pdp_ram_3_0_25)) + (portRef DIB16 (instanceRef pdp_ram_3_0_25)) + (portRef DIA16 (instanceRef pdp_ram_3_0_25)) + (portRef DIB15 (instanceRef pdp_ram_3_0_25)) + (portRef DIA15 (instanceRef pdp_ram_3_0_25)) + (portRef DIB14 (instanceRef pdp_ram_3_0_25)) + (portRef DIA14 (instanceRef pdp_ram_3_0_25)) + (portRef DIB13 (instanceRef pdp_ram_3_0_25)) + (portRef DIA13 (instanceRef pdp_ram_3_0_25)) + (portRef DIB12 (instanceRef pdp_ram_3_0_25)) + (portRef DIA12 (instanceRef pdp_ram_3_0_25)) + (portRef DIB11 (instanceRef pdp_ram_3_0_25)) + (portRef DIA11 (instanceRef pdp_ram_3_0_25)) + (portRef DIB10 (instanceRef pdp_ram_3_0_25)) + (portRef DIA10 (instanceRef pdp_ram_3_0_25)) + (portRef DIB9 (instanceRef pdp_ram_3_0_25)) + (portRef DIA9 (instanceRef pdp_ram_3_0_25)) + (portRef DIB8 (instanceRef pdp_ram_3_0_25)) + (portRef DIB7 (instanceRef pdp_ram_3_0_25)) + (portRef DIB6 (instanceRef pdp_ram_3_0_25)) + (portRef DIB5 (instanceRef pdp_ram_3_0_25)) + (portRef DIB4 (instanceRef pdp_ram_3_0_25)) + (portRef DIB3 (instanceRef pdp_ram_3_0_25)) + (portRef DIB2 (instanceRef pdp_ram_3_0_25)) + (portRef DIB1 (instanceRef pdp_ram_3_0_25)) + (portRef DIB0 (instanceRef pdp_ram_3_0_25)) + (portRef CSB2 (instanceRef pdp_ram_3_1_24)) + (portRef CSA2 (instanceRef pdp_ram_3_1_24)) + (portRef CSB1 (instanceRef pdp_ram_3_1_24)) + (portRef CSA1 (instanceRef pdp_ram_3_1_24)) + (portRef WEB (instanceRef pdp_ram_3_1_24)) + (portRef ADB2 (instanceRef pdp_ram_3_1_24)) + (portRef ADA2 (instanceRef pdp_ram_3_1_24)) + (portRef ADB1 (instanceRef pdp_ram_3_1_24)) + (portRef ADA1 (instanceRef pdp_ram_3_1_24)) + (portRef ADB0 (instanceRef pdp_ram_3_1_24)) + (portRef ADA0 (instanceRef pdp_ram_3_1_24)) + (portRef DIB17 (instanceRef pdp_ram_3_1_24)) + (portRef DIA17 (instanceRef pdp_ram_3_1_24)) + (portRef DIB16 (instanceRef pdp_ram_3_1_24)) + (portRef DIA16 (instanceRef pdp_ram_3_1_24)) + (portRef DIB15 (instanceRef pdp_ram_3_1_24)) + (portRef DIA15 (instanceRef pdp_ram_3_1_24)) + (portRef DIB14 (instanceRef pdp_ram_3_1_24)) + (portRef DIA14 (instanceRef pdp_ram_3_1_24)) + (portRef DIB13 (instanceRef pdp_ram_3_1_24)) + (portRef DIA13 (instanceRef pdp_ram_3_1_24)) + (portRef DIB12 (instanceRef pdp_ram_3_1_24)) + (portRef DIA12 (instanceRef pdp_ram_3_1_24)) + (portRef DIB11 (instanceRef pdp_ram_3_1_24)) + (portRef DIA11 (instanceRef pdp_ram_3_1_24)) + (portRef DIB10 (instanceRef pdp_ram_3_1_24)) + (portRef DIA10 (instanceRef pdp_ram_3_1_24)) + (portRef DIB9 (instanceRef pdp_ram_3_1_24)) + (portRef DIA9 (instanceRef pdp_ram_3_1_24)) + (portRef DIB8 (instanceRef pdp_ram_3_1_24)) + (portRef DIB7 (instanceRef pdp_ram_3_1_24)) + (portRef DIB6 (instanceRef pdp_ram_3_1_24)) + (portRef DIB5 (instanceRef pdp_ram_3_1_24)) + (portRef DIB4 (instanceRef pdp_ram_3_1_24)) + (portRef DIB3 (instanceRef pdp_ram_3_1_24)) + (portRef DIB2 (instanceRef pdp_ram_3_1_24)) + (portRef DIB1 (instanceRef pdp_ram_3_1_24)) + (portRef DIB0 (instanceRef pdp_ram_3_1_24)) + (portRef CSB2 (instanceRef pdp_ram_4_0_23)) + (portRef CSA2 (instanceRef pdp_ram_4_0_23)) + (portRef CSB1 (instanceRef pdp_ram_4_0_23)) + (portRef CSA1 (instanceRef pdp_ram_4_0_23)) + (portRef WEB (instanceRef pdp_ram_4_0_23)) + (portRef ADB2 (instanceRef pdp_ram_4_0_23)) + (portRef ADA2 (instanceRef pdp_ram_4_0_23)) + (portRef ADB1 (instanceRef pdp_ram_4_0_23)) + (portRef ADA1 (instanceRef pdp_ram_4_0_23)) + (portRef ADB0 (instanceRef pdp_ram_4_0_23)) + (portRef ADA0 (instanceRef pdp_ram_4_0_23)) + (portRef DIB17 (instanceRef pdp_ram_4_0_23)) + (portRef DIA17 (instanceRef pdp_ram_4_0_23)) + (portRef DIB16 (instanceRef pdp_ram_4_0_23)) + (portRef DIA16 (instanceRef pdp_ram_4_0_23)) + (portRef DIB15 (instanceRef pdp_ram_4_0_23)) + (portRef DIA15 (instanceRef pdp_ram_4_0_23)) + (portRef DIB14 (instanceRef pdp_ram_4_0_23)) + (portRef DIA14 (instanceRef pdp_ram_4_0_23)) + (portRef DIB13 (instanceRef pdp_ram_4_0_23)) + (portRef DIA13 (instanceRef pdp_ram_4_0_23)) + (portRef DIB12 (instanceRef pdp_ram_4_0_23)) + (portRef DIA12 (instanceRef pdp_ram_4_0_23)) + (portRef DIB11 (instanceRef pdp_ram_4_0_23)) + (portRef DIA11 (instanceRef pdp_ram_4_0_23)) + (portRef DIB10 (instanceRef pdp_ram_4_0_23)) + (portRef DIA10 (instanceRef pdp_ram_4_0_23)) + (portRef DIB9 (instanceRef pdp_ram_4_0_23)) + (portRef DIA9 (instanceRef pdp_ram_4_0_23)) + (portRef DIB8 (instanceRef pdp_ram_4_0_23)) + (portRef DIB7 (instanceRef pdp_ram_4_0_23)) + (portRef DIB6 (instanceRef pdp_ram_4_0_23)) + (portRef DIB5 (instanceRef pdp_ram_4_0_23)) + (portRef DIB4 (instanceRef pdp_ram_4_0_23)) + (portRef DIB3 (instanceRef pdp_ram_4_0_23)) + (portRef DIB2 (instanceRef pdp_ram_4_0_23)) + (portRef DIB1 (instanceRef pdp_ram_4_0_23)) + (portRef DIB0 (instanceRef pdp_ram_4_0_23)) + (portRef CSB2 (instanceRef pdp_ram_4_1_22)) + (portRef CSA2 (instanceRef pdp_ram_4_1_22)) + (portRef CSB1 (instanceRef pdp_ram_4_1_22)) + (portRef CSA1 (instanceRef pdp_ram_4_1_22)) + (portRef WEB (instanceRef pdp_ram_4_1_22)) + (portRef ADB2 (instanceRef pdp_ram_4_1_22)) + (portRef ADA2 (instanceRef pdp_ram_4_1_22)) + (portRef ADB1 (instanceRef pdp_ram_4_1_22)) + (portRef ADA1 (instanceRef pdp_ram_4_1_22)) + (portRef ADB0 (instanceRef pdp_ram_4_1_22)) + (portRef ADA0 (instanceRef pdp_ram_4_1_22)) + (portRef DIB17 (instanceRef pdp_ram_4_1_22)) + (portRef DIA17 (instanceRef pdp_ram_4_1_22)) + (portRef DIB16 (instanceRef pdp_ram_4_1_22)) + (portRef DIA16 (instanceRef pdp_ram_4_1_22)) + (portRef DIB15 (instanceRef pdp_ram_4_1_22)) + (portRef DIA15 (instanceRef pdp_ram_4_1_22)) + (portRef DIB14 (instanceRef pdp_ram_4_1_22)) + (portRef DIA14 (instanceRef pdp_ram_4_1_22)) + (portRef DIB13 (instanceRef pdp_ram_4_1_22)) + (portRef DIA13 (instanceRef pdp_ram_4_1_22)) + (portRef DIB12 (instanceRef pdp_ram_4_1_22)) + (portRef DIA12 (instanceRef pdp_ram_4_1_22)) + (portRef DIB11 (instanceRef pdp_ram_4_1_22)) + (portRef DIA11 (instanceRef pdp_ram_4_1_22)) + (portRef DIB10 (instanceRef pdp_ram_4_1_22)) + (portRef DIA10 (instanceRef pdp_ram_4_1_22)) + (portRef DIB9 (instanceRef pdp_ram_4_1_22)) + (portRef DIA9 (instanceRef pdp_ram_4_1_22)) + (portRef DIB8 (instanceRef pdp_ram_4_1_22)) + (portRef DIB7 (instanceRef pdp_ram_4_1_22)) + (portRef DIB6 (instanceRef pdp_ram_4_1_22)) + (portRef DIB5 (instanceRef pdp_ram_4_1_22)) + (portRef DIB4 (instanceRef pdp_ram_4_1_22)) + (portRef DIB3 (instanceRef pdp_ram_4_1_22)) + (portRef DIB2 (instanceRef pdp_ram_4_1_22)) + (portRef DIB1 (instanceRef pdp_ram_4_1_22)) + (portRef DIB0 (instanceRef pdp_ram_4_1_22)) + (portRef CSB2 (instanceRef pdp_ram_5_0_21)) + (portRef CSA2 (instanceRef pdp_ram_5_0_21)) + (portRef CSB1 (instanceRef pdp_ram_5_0_21)) + (portRef CSA1 (instanceRef pdp_ram_5_0_21)) + (portRef WEB (instanceRef pdp_ram_5_0_21)) + (portRef ADB2 (instanceRef pdp_ram_5_0_21)) + (portRef ADA2 (instanceRef pdp_ram_5_0_21)) + (portRef ADB1 (instanceRef pdp_ram_5_0_21)) + (portRef ADA1 (instanceRef pdp_ram_5_0_21)) + (portRef ADB0 (instanceRef pdp_ram_5_0_21)) + (portRef ADA0 (instanceRef pdp_ram_5_0_21)) + (portRef DIB17 (instanceRef pdp_ram_5_0_21)) + (portRef DIA17 (instanceRef pdp_ram_5_0_21)) + (portRef DIB16 (instanceRef pdp_ram_5_0_21)) + (portRef DIA16 (instanceRef pdp_ram_5_0_21)) + (portRef DIB15 (instanceRef pdp_ram_5_0_21)) + (portRef DIA15 (instanceRef pdp_ram_5_0_21)) + (portRef DIB14 (instanceRef pdp_ram_5_0_21)) + (portRef DIA14 (instanceRef pdp_ram_5_0_21)) + (portRef DIB13 (instanceRef pdp_ram_5_0_21)) + (portRef DIA13 (instanceRef pdp_ram_5_0_21)) + (portRef DIB12 (instanceRef pdp_ram_5_0_21)) + (portRef DIA12 (instanceRef pdp_ram_5_0_21)) + (portRef DIB11 (instanceRef pdp_ram_5_0_21)) + (portRef DIA11 (instanceRef pdp_ram_5_0_21)) + (portRef DIB10 (instanceRef pdp_ram_5_0_21)) + (portRef DIA10 (instanceRef pdp_ram_5_0_21)) + (portRef DIB9 (instanceRef pdp_ram_5_0_21)) + (portRef DIA9 (instanceRef pdp_ram_5_0_21)) + (portRef DIB8 (instanceRef pdp_ram_5_0_21)) + (portRef DIB7 (instanceRef pdp_ram_5_0_21)) + (portRef DIB6 (instanceRef pdp_ram_5_0_21)) + (portRef DIB5 (instanceRef pdp_ram_5_0_21)) + (portRef DIB4 (instanceRef pdp_ram_5_0_21)) + (portRef DIB3 (instanceRef pdp_ram_5_0_21)) + (portRef DIB2 (instanceRef pdp_ram_5_0_21)) + (portRef DIB1 (instanceRef pdp_ram_5_0_21)) + (portRef DIB0 (instanceRef pdp_ram_5_0_21)) + (portRef CSB2 (instanceRef pdp_ram_5_1_20)) + (portRef CSA2 (instanceRef pdp_ram_5_1_20)) + (portRef CSB1 (instanceRef pdp_ram_5_1_20)) + (portRef CSA1 (instanceRef pdp_ram_5_1_20)) + (portRef WEB (instanceRef pdp_ram_5_1_20)) + (portRef ADB2 (instanceRef pdp_ram_5_1_20)) + (portRef ADA2 (instanceRef pdp_ram_5_1_20)) + (portRef ADB1 (instanceRef pdp_ram_5_1_20)) + (portRef ADA1 (instanceRef pdp_ram_5_1_20)) + (portRef ADB0 (instanceRef pdp_ram_5_1_20)) + (portRef ADA0 (instanceRef pdp_ram_5_1_20)) + (portRef DIB17 (instanceRef pdp_ram_5_1_20)) + (portRef DIA17 (instanceRef pdp_ram_5_1_20)) + (portRef DIB16 (instanceRef pdp_ram_5_1_20)) + (portRef DIA16 (instanceRef pdp_ram_5_1_20)) + (portRef DIB15 (instanceRef pdp_ram_5_1_20)) + (portRef DIA15 (instanceRef pdp_ram_5_1_20)) + (portRef DIB14 (instanceRef pdp_ram_5_1_20)) + (portRef DIA14 (instanceRef pdp_ram_5_1_20)) + (portRef DIB13 (instanceRef pdp_ram_5_1_20)) + (portRef DIA13 (instanceRef pdp_ram_5_1_20)) + (portRef DIB12 (instanceRef pdp_ram_5_1_20)) + (portRef DIA12 (instanceRef pdp_ram_5_1_20)) + (portRef DIB11 (instanceRef pdp_ram_5_1_20)) + (portRef DIA11 (instanceRef pdp_ram_5_1_20)) + (portRef DIB10 (instanceRef pdp_ram_5_1_20)) + (portRef DIA10 (instanceRef pdp_ram_5_1_20)) + (portRef DIB9 (instanceRef pdp_ram_5_1_20)) + (portRef DIA9 (instanceRef pdp_ram_5_1_20)) + (portRef DIB8 (instanceRef pdp_ram_5_1_20)) + (portRef DIB7 (instanceRef pdp_ram_5_1_20)) + (portRef DIB6 (instanceRef pdp_ram_5_1_20)) + (portRef DIB5 (instanceRef pdp_ram_5_1_20)) + (portRef DIB4 (instanceRef pdp_ram_5_1_20)) + (portRef DIB3 (instanceRef pdp_ram_5_1_20)) + (portRef DIB2 (instanceRef pdp_ram_5_1_20)) + (portRef DIB1 (instanceRef pdp_ram_5_1_20)) + (portRef DIB0 (instanceRef pdp_ram_5_1_20)) + (portRef CSB2 (instanceRef pdp_ram_6_0_19)) + (portRef CSA2 (instanceRef pdp_ram_6_0_19)) + (portRef CSB1 (instanceRef pdp_ram_6_0_19)) + (portRef CSA1 (instanceRef pdp_ram_6_0_19)) + (portRef WEB (instanceRef pdp_ram_6_0_19)) + (portRef ADB2 (instanceRef pdp_ram_6_0_19)) + (portRef ADA2 (instanceRef pdp_ram_6_0_19)) + (portRef ADB1 (instanceRef pdp_ram_6_0_19)) + (portRef ADA1 (instanceRef pdp_ram_6_0_19)) + (portRef ADB0 (instanceRef pdp_ram_6_0_19)) + (portRef ADA0 (instanceRef pdp_ram_6_0_19)) + (portRef DIB17 (instanceRef pdp_ram_6_0_19)) + (portRef DIA17 (instanceRef pdp_ram_6_0_19)) + (portRef DIB16 (instanceRef pdp_ram_6_0_19)) + (portRef DIA16 (instanceRef pdp_ram_6_0_19)) + (portRef DIB15 (instanceRef pdp_ram_6_0_19)) + (portRef DIA15 (instanceRef pdp_ram_6_0_19)) + (portRef DIB14 (instanceRef pdp_ram_6_0_19)) + (portRef DIA14 (instanceRef pdp_ram_6_0_19)) + (portRef DIB13 (instanceRef pdp_ram_6_0_19)) + (portRef DIA13 (instanceRef pdp_ram_6_0_19)) + (portRef DIB12 (instanceRef pdp_ram_6_0_19)) + (portRef DIA12 (instanceRef pdp_ram_6_0_19)) + (portRef DIB11 (instanceRef pdp_ram_6_0_19)) + (portRef DIA11 (instanceRef pdp_ram_6_0_19)) + (portRef DIB10 (instanceRef pdp_ram_6_0_19)) + (portRef DIA10 (instanceRef pdp_ram_6_0_19)) + (portRef DIB9 (instanceRef pdp_ram_6_0_19)) + (portRef DIA9 (instanceRef pdp_ram_6_0_19)) + (portRef DIB8 (instanceRef pdp_ram_6_0_19)) + (portRef DIB7 (instanceRef pdp_ram_6_0_19)) + (portRef DIB6 (instanceRef pdp_ram_6_0_19)) + (portRef DIB5 (instanceRef pdp_ram_6_0_19)) + (portRef DIB4 (instanceRef pdp_ram_6_0_19)) + (portRef DIB3 (instanceRef pdp_ram_6_0_19)) + (portRef DIB2 (instanceRef pdp_ram_6_0_19)) + (portRef DIB1 (instanceRef pdp_ram_6_0_19)) + (portRef DIB0 (instanceRef pdp_ram_6_0_19)) + (portRef CSB2 (instanceRef pdp_ram_6_1_18)) + (portRef CSA2 (instanceRef pdp_ram_6_1_18)) + (portRef CSB1 (instanceRef pdp_ram_6_1_18)) + (portRef CSA1 (instanceRef pdp_ram_6_1_18)) + (portRef WEB (instanceRef pdp_ram_6_1_18)) + (portRef ADB2 (instanceRef pdp_ram_6_1_18)) + (portRef ADA2 (instanceRef pdp_ram_6_1_18)) + (portRef ADB1 (instanceRef pdp_ram_6_1_18)) + (portRef ADA1 (instanceRef pdp_ram_6_1_18)) + (portRef ADB0 (instanceRef pdp_ram_6_1_18)) + (portRef ADA0 (instanceRef pdp_ram_6_1_18)) + (portRef DIB17 (instanceRef pdp_ram_6_1_18)) + (portRef DIA17 (instanceRef pdp_ram_6_1_18)) + (portRef DIB16 (instanceRef pdp_ram_6_1_18)) + (portRef DIA16 (instanceRef pdp_ram_6_1_18)) + (portRef DIB15 (instanceRef pdp_ram_6_1_18)) + (portRef DIA15 (instanceRef pdp_ram_6_1_18)) + (portRef DIB14 (instanceRef pdp_ram_6_1_18)) + (portRef DIA14 (instanceRef pdp_ram_6_1_18)) + (portRef DIB13 (instanceRef pdp_ram_6_1_18)) + (portRef DIA13 (instanceRef pdp_ram_6_1_18)) + (portRef DIB12 (instanceRef pdp_ram_6_1_18)) + (portRef DIA12 (instanceRef pdp_ram_6_1_18)) + (portRef DIB11 (instanceRef pdp_ram_6_1_18)) + (portRef DIA11 (instanceRef pdp_ram_6_1_18)) + (portRef DIB10 (instanceRef pdp_ram_6_1_18)) + (portRef DIA10 (instanceRef pdp_ram_6_1_18)) + (portRef DIB9 (instanceRef pdp_ram_6_1_18)) + (portRef DIA9 (instanceRef pdp_ram_6_1_18)) + (portRef DIB8 (instanceRef pdp_ram_6_1_18)) + (portRef DIB7 (instanceRef pdp_ram_6_1_18)) + (portRef DIB6 (instanceRef pdp_ram_6_1_18)) + (portRef DIB5 (instanceRef pdp_ram_6_1_18)) + (portRef DIB4 (instanceRef pdp_ram_6_1_18)) + (portRef DIB3 (instanceRef pdp_ram_6_1_18)) + (portRef DIB2 (instanceRef pdp_ram_6_1_18)) + (portRef DIB1 (instanceRef pdp_ram_6_1_18)) + (portRef DIB0 (instanceRef pdp_ram_6_1_18)) + (portRef CSB2 (instanceRef pdp_ram_7_0_17)) + (portRef CSA2 (instanceRef pdp_ram_7_0_17)) + (portRef CSB1 (instanceRef pdp_ram_7_0_17)) + (portRef CSA1 (instanceRef pdp_ram_7_0_17)) + (portRef WEB (instanceRef pdp_ram_7_0_17)) + (portRef ADB2 (instanceRef pdp_ram_7_0_17)) + (portRef ADA2 (instanceRef pdp_ram_7_0_17)) + (portRef ADB1 (instanceRef pdp_ram_7_0_17)) + (portRef ADA1 (instanceRef pdp_ram_7_0_17)) + (portRef ADB0 (instanceRef pdp_ram_7_0_17)) + (portRef ADA0 (instanceRef pdp_ram_7_0_17)) + (portRef DIB17 (instanceRef pdp_ram_7_0_17)) + (portRef DIA17 (instanceRef pdp_ram_7_0_17)) + (portRef DIB16 (instanceRef pdp_ram_7_0_17)) + (portRef DIA16 (instanceRef pdp_ram_7_0_17)) + (portRef DIB15 (instanceRef pdp_ram_7_0_17)) + (portRef DIA15 (instanceRef pdp_ram_7_0_17)) + (portRef DIB14 (instanceRef pdp_ram_7_0_17)) + (portRef DIA14 (instanceRef pdp_ram_7_0_17)) + (portRef DIB13 (instanceRef pdp_ram_7_0_17)) + (portRef DIA13 (instanceRef pdp_ram_7_0_17)) + (portRef DIB12 (instanceRef pdp_ram_7_0_17)) + (portRef DIA12 (instanceRef pdp_ram_7_0_17)) + (portRef DIB11 (instanceRef pdp_ram_7_0_17)) + (portRef DIA11 (instanceRef pdp_ram_7_0_17)) + (portRef DIB10 (instanceRef pdp_ram_7_0_17)) + (portRef DIA10 (instanceRef pdp_ram_7_0_17)) + (portRef DIB9 (instanceRef pdp_ram_7_0_17)) + (portRef DIA9 (instanceRef pdp_ram_7_0_17)) + (portRef DIB8 (instanceRef pdp_ram_7_0_17)) + (portRef DIB7 (instanceRef pdp_ram_7_0_17)) + (portRef DIB6 (instanceRef pdp_ram_7_0_17)) + (portRef DIB5 (instanceRef pdp_ram_7_0_17)) + (portRef DIB4 (instanceRef pdp_ram_7_0_17)) + (portRef DIB3 (instanceRef pdp_ram_7_0_17)) + (portRef DIB2 (instanceRef pdp_ram_7_0_17)) + (portRef DIB1 (instanceRef pdp_ram_7_0_17)) + (portRef DIB0 (instanceRef pdp_ram_7_0_17)) + (portRef CSB2 (instanceRef pdp_ram_7_1_16)) + (portRef CSA2 (instanceRef pdp_ram_7_1_16)) + (portRef CSB1 (instanceRef pdp_ram_7_1_16)) + (portRef CSA1 (instanceRef pdp_ram_7_1_16)) + (portRef WEB (instanceRef pdp_ram_7_1_16)) + (portRef ADB2 (instanceRef pdp_ram_7_1_16)) + (portRef ADA2 (instanceRef pdp_ram_7_1_16)) + (portRef ADB1 (instanceRef pdp_ram_7_1_16)) + (portRef ADA1 (instanceRef pdp_ram_7_1_16)) + (portRef ADB0 (instanceRef pdp_ram_7_1_16)) + (portRef ADA0 (instanceRef pdp_ram_7_1_16)) + (portRef DIB17 (instanceRef pdp_ram_7_1_16)) + (portRef DIA17 (instanceRef pdp_ram_7_1_16)) + (portRef DIB16 (instanceRef pdp_ram_7_1_16)) + (portRef DIA16 (instanceRef pdp_ram_7_1_16)) + (portRef DIB15 (instanceRef pdp_ram_7_1_16)) + (portRef DIA15 (instanceRef pdp_ram_7_1_16)) + (portRef DIB14 (instanceRef pdp_ram_7_1_16)) + (portRef DIA14 (instanceRef pdp_ram_7_1_16)) + (portRef DIB13 (instanceRef pdp_ram_7_1_16)) + (portRef DIA13 (instanceRef pdp_ram_7_1_16)) + (portRef DIB12 (instanceRef pdp_ram_7_1_16)) + (portRef DIA12 (instanceRef pdp_ram_7_1_16)) + (portRef DIB11 (instanceRef pdp_ram_7_1_16)) + (portRef DIA11 (instanceRef pdp_ram_7_1_16)) + (portRef DIB10 (instanceRef pdp_ram_7_1_16)) + (portRef DIA10 (instanceRef pdp_ram_7_1_16)) + (portRef DIB9 (instanceRef pdp_ram_7_1_16)) + (portRef DIA9 (instanceRef pdp_ram_7_1_16)) + (portRef DIB8 (instanceRef pdp_ram_7_1_16)) + (portRef DIB7 (instanceRef pdp_ram_7_1_16)) + (portRef DIB6 (instanceRef pdp_ram_7_1_16)) + (portRef DIB5 (instanceRef pdp_ram_7_1_16)) + (portRef DIB4 (instanceRef pdp_ram_7_1_16)) + (portRef DIB3 (instanceRef pdp_ram_7_1_16)) + (portRef DIB2 (instanceRef pdp_ram_7_1_16)) + (portRef DIB1 (instanceRef pdp_ram_7_1_16)) + (portRef DIB0 (instanceRef pdp_ram_7_1_16)) + (portRef CSB2 (instanceRef pdp_ram_8_0_15)) + (portRef CSA2 (instanceRef pdp_ram_8_0_15)) + (portRef CSB1 (instanceRef pdp_ram_8_0_15)) + (portRef CSA1 (instanceRef pdp_ram_8_0_15)) + (portRef WEB (instanceRef pdp_ram_8_0_15)) + (portRef ADB2 (instanceRef pdp_ram_8_0_15)) + (portRef ADA2 (instanceRef pdp_ram_8_0_15)) + (portRef ADB1 (instanceRef pdp_ram_8_0_15)) + (portRef ADA1 (instanceRef pdp_ram_8_0_15)) + (portRef ADB0 (instanceRef pdp_ram_8_0_15)) + (portRef ADA0 (instanceRef pdp_ram_8_0_15)) + (portRef DIB17 (instanceRef pdp_ram_8_0_15)) + (portRef DIA17 (instanceRef pdp_ram_8_0_15)) + (portRef DIB16 (instanceRef pdp_ram_8_0_15)) + (portRef DIA16 (instanceRef pdp_ram_8_0_15)) + (portRef DIB15 (instanceRef pdp_ram_8_0_15)) + (portRef DIA15 (instanceRef pdp_ram_8_0_15)) + (portRef DIB14 (instanceRef pdp_ram_8_0_15)) + (portRef DIA14 (instanceRef pdp_ram_8_0_15)) + (portRef DIB13 (instanceRef pdp_ram_8_0_15)) + (portRef DIA13 (instanceRef pdp_ram_8_0_15)) + (portRef DIB12 (instanceRef pdp_ram_8_0_15)) + (portRef DIA12 (instanceRef pdp_ram_8_0_15)) + (portRef DIB11 (instanceRef pdp_ram_8_0_15)) + (portRef DIA11 (instanceRef pdp_ram_8_0_15)) + (portRef DIB10 (instanceRef pdp_ram_8_0_15)) + (portRef DIA10 (instanceRef pdp_ram_8_0_15)) + (portRef DIB9 (instanceRef pdp_ram_8_0_15)) + (portRef DIA9 (instanceRef pdp_ram_8_0_15)) + (portRef DIB8 (instanceRef pdp_ram_8_0_15)) + (portRef DIB7 (instanceRef pdp_ram_8_0_15)) + (portRef DIB6 (instanceRef pdp_ram_8_0_15)) + (portRef DIB5 (instanceRef pdp_ram_8_0_15)) + (portRef DIB4 (instanceRef pdp_ram_8_0_15)) + (portRef DIB3 (instanceRef pdp_ram_8_0_15)) + (portRef DIB2 (instanceRef pdp_ram_8_0_15)) + (portRef DIB1 (instanceRef pdp_ram_8_0_15)) + (portRef DIB0 (instanceRef pdp_ram_8_0_15)) + (portRef CSB2 (instanceRef pdp_ram_8_1_14)) + (portRef CSA2 (instanceRef pdp_ram_8_1_14)) + (portRef CSB1 (instanceRef pdp_ram_8_1_14)) + (portRef CSA1 (instanceRef pdp_ram_8_1_14)) + (portRef WEB (instanceRef pdp_ram_8_1_14)) + (portRef ADB2 (instanceRef pdp_ram_8_1_14)) + (portRef ADA2 (instanceRef pdp_ram_8_1_14)) + (portRef ADB1 (instanceRef pdp_ram_8_1_14)) + (portRef ADA1 (instanceRef pdp_ram_8_1_14)) + (portRef ADB0 (instanceRef pdp_ram_8_1_14)) + (portRef ADA0 (instanceRef pdp_ram_8_1_14)) + (portRef DIB17 (instanceRef pdp_ram_8_1_14)) + (portRef DIA17 (instanceRef pdp_ram_8_1_14)) + (portRef DIB16 (instanceRef pdp_ram_8_1_14)) + (portRef DIA16 (instanceRef pdp_ram_8_1_14)) + (portRef DIB15 (instanceRef pdp_ram_8_1_14)) + (portRef DIA15 (instanceRef pdp_ram_8_1_14)) + (portRef DIB14 (instanceRef pdp_ram_8_1_14)) + (portRef DIA14 (instanceRef pdp_ram_8_1_14)) + (portRef DIB13 (instanceRef pdp_ram_8_1_14)) + (portRef DIA13 (instanceRef pdp_ram_8_1_14)) + (portRef DIB12 (instanceRef pdp_ram_8_1_14)) + (portRef DIA12 (instanceRef pdp_ram_8_1_14)) + (portRef DIB11 (instanceRef pdp_ram_8_1_14)) + (portRef DIA11 (instanceRef pdp_ram_8_1_14)) + (portRef DIB10 (instanceRef pdp_ram_8_1_14)) + (portRef DIA10 (instanceRef pdp_ram_8_1_14)) + (portRef DIB9 (instanceRef pdp_ram_8_1_14)) + (portRef DIA9 (instanceRef pdp_ram_8_1_14)) + (portRef DIB8 (instanceRef pdp_ram_8_1_14)) + (portRef DIB7 (instanceRef pdp_ram_8_1_14)) + (portRef DIB6 (instanceRef pdp_ram_8_1_14)) + (portRef DIB5 (instanceRef pdp_ram_8_1_14)) + (portRef DIB4 (instanceRef pdp_ram_8_1_14)) + (portRef DIB3 (instanceRef pdp_ram_8_1_14)) + (portRef DIB2 (instanceRef pdp_ram_8_1_14)) + (portRef DIB1 (instanceRef pdp_ram_8_1_14)) + (portRef DIB0 (instanceRef pdp_ram_8_1_14)) + (portRef CSB2 (instanceRef pdp_ram_9_0_13)) + (portRef CSA2 (instanceRef pdp_ram_9_0_13)) + (portRef CSB1 (instanceRef pdp_ram_9_0_13)) + (portRef CSA1 (instanceRef pdp_ram_9_0_13)) + (portRef WEB (instanceRef pdp_ram_9_0_13)) + (portRef ADB2 (instanceRef pdp_ram_9_0_13)) + (portRef ADA2 (instanceRef pdp_ram_9_0_13)) + (portRef ADB1 (instanceRef pdp_ram_9_0_13)) + (portRef ADA1 (instanceRef pdp_ram_9_0_13)) + (portRef ADB0 (instanceRef pdp_ram_9_0_13)) + (portRef ADA0 (instanceRef pdp_ram_9_0_13)) + (portRef DIB17 (instanceRef pdp_ram_9_0_13)) + (portRef DIA17 (instanceRef pdp_ram_9_0_13)) + (portRef DIB16 (instanceRef pdp_ram_9_0_13)) + (portRef DIA16 (instanceRef pdp_ram_9_0_13)) + (portRef DIB15 (instanceRef pdp_ram_9_0_13)) + (portRef DIA15 (instanceRef pdp_ram_9_0_13)) + (portRef DIB14 (instanceRef pdp_ram_9_0_13)) + (portRef DIA14 (instanceRef pdp_ram_9_0_13)) + (portRef DIB13 (instanceRef pdp_ram_9_0_13)) + (portRef DIA13 (instanceRef pdp_ram_9_0_13)) + (portRef DIB12 (instanceRef pdp_ram_9_0_13)) + (portRef DIA12 (instanceRef pdp_ram_9_0_13)) + (portRef DIB11 (instanceRef pdp_ram_9_0_13)) + (portRef DIA11 (instanceRef pdp_ram_9_0_13)) + (portRef DIB10 (instanceRef pdp_ram_9_0_13)) + (portRef DIA10 (instanceRef pdp_ram_9_0_13)) + (portRef DIB9 (instanceRef pdp_ram_9_0_13)) + (portRef DIA9 (instanceRef pdp_ram_9_0_13)) + (portRef DIB8 (instanceRef pdp_ram_9_0_13)) + (portRef DIB7 (instanceRef pdp_ram_9_0_13)) + (portRef DIB6 (instanceRef pdp_ram_9_0_13)) + (portRef DIB5 (instanceRef pdp_ram_9_0_13)) + (portRef DIB4 (instanceRef pdp_ram_9_0_13)) + (portRef DIB3 (instanceRef pdp_ram_9_0_13)) + (portRef DIB2 (instanceRef pdp_ram_9_0_13)) + (portRef DIB1 (instanceRef pdp_ram_9_0_13)) + (portRef DIB0 (instanceRef pdp_ram_9_0_13)) + (portRef CSB2 (instanceRef pdp_ram_9_1_12)) + (portRef CSA2 (instanceRef pdp_ram_9_1_12)) + (portRef CSB1 (instanceRef pdp_ram_9_1_12)) + (portRef CSA1 (instanceRef pdp_ram_9_1_12)) + (portRef WEB (instanceRef pdp_ram_9_1_12)) + (portRef ADB2 (instanceRef pdp_ram_9_1_12)) + (portRef ADA2 (instanceRef pdp_ram_9_1_12)) + (portRef ADB1 (instanceRef pdp_ram_9_1_12)) + (portRef ADA1 (instanceRef pdp_ram_9_1_12)) + (portRef ADB0 (instanceRef pdp_ram_9_1_12)) + (portRef ADA0 (instanceRef pdp_ram_9_1_12)) + (portRef DIB17 (instanceRef pdp_ram_9_1_12)) + (portRef DIA17 (instanceRef pdp_ram_9_1_12)) + (portRef DIB16 (instanceRef pdp_ram_9_1_12)) + (portRef DIA16 (instanceRef pdp_ram_9_1_12)) + (portRef DIB15 (instanceRef pdp_ram_9_1_12)) + (portRef DIA15 (instanceRef pdp_ram_9_1_12)) + (portRef DIB14 (instanceRef pdp_ram_9_1_12)) + (portRef DIA14 (instanceRef pdp_ram_9_1_12)) + (portRef DIB13 (instanceRef pdp_ram_9_1_12)) + (portRef DIA13 (instanceRef pdp_ram_9_1_12)) + (portRef DIB12 (instanceRef pdp_ram_9_1_12)) + (portRef DIA12 (instanceRef pdp_ram_9_1_12)) + (portRef DIB11 (instanceRef pdp_ram_9_1_12)) + (portRef DIA11 (instanceRef pdp_ram_9_1_12)) + (portRef DIB10 (instanceRef pdp_ram_9_1_12)) + (portRef DIA10 (instanceRef pdp_ram_9_1_12)) + (portRef DIB9 (instanceRef pdp_ram_9_1_12)) + (portRef DIA9 (instanceRef pdp_ram_9_1_12)) + (portRef DIB8 (instanceRef pdp_ram_9_1_12)) + (portRef DIB7 (instanceRef pdp_ram_9_1_12)) + (portRef DIB6 (instanceRef pdp_ram_9_1_12)) + (portRef DIB5 (instanceRef pdp_ram_9_1_12)) + (portRef DIB4 (instanceRef pdp_ram_9_1_12)) + (portRef DIB3 (instanceRef pdp_ram_9_1_12)) + (portRef DIB2 (instanceRef pdp_ram_9_1_12)) + (portRef DIB1 (instanceRef pdp_ram_9_1_12)) + (portRef DIB0 (instanceRef pdp_ram_9_1_12)) + (portRef CSB2 (instanceRef pdp_ram_10_0_11)) + (portRef CSA2 (instanceRef pdp_ram_10_0_11)) + (portRef CSB1 (instanceRef pdp_ram_10_0_11)) + (portRef CSA1 (instanceRef pdp_ram_10_0_11)) + (portRef WEB (instanceRef pdp_ram_10_0_11)) + (portRef ADB2 (instanceRef pdp_ram_10_0_11)) + (portRef ADA2 (instanceRef pdp_ram_10_0_11)) + (portRef ADB1 (instanceRef pdp_ram_10_0_11)) + (portRef ADA1 (instanceRef pdp_ram_10_0_11)) + (portRef ADB0 (instanceRef pdp_ram_10_0_11)) + (portRef ADA0 (instanceRef pdp_ram_10_0_11)) + (portRef DIB17 (instanceRef pdp_ram_10_0_11)) + (portRef DIA17 (instanceRef pdp_ram_10_0_11)) + (portRef DIB16 (instanceRef pdp_ram_10_0_11)) + (portRef DIA16 (instanceRef pdp_ram_10_0_11)) + (portRef DIB15 (instanceRef pdp_ram_10_0_11)) + (portRef DIA15 (instanceRef pdp_ram_10_0_11)) + (portRef DIB14 (instanceRef pdp_ram_10_0_11)) + (portRef DIA14 (instanceRef pdp_ram_10_0_11)) + (portRef DIB13 (instanceRef pdp_ram_10_0_11)) + (portRef DIA13 (instanceRef pdp_ram_10_0_11)) + (portRef DIB12 (instanceRef pdp_ram_10_0_11)) + (portRef DIA12 (instanceRef pdp_ram_10_0_11)) + (portRef DIB11 (instanceRef pdp_ram_10_0_11)) + (portRef DIA11 (instanceRef pdp_ram_10_0_11)) + (portRef DIB10 (instanceRef pdp_ram_10_0_11)) + (portRef DIA10 (instanceRef pdp_ram_10_0_11)) + (portRef DIB9 (instanceRef pdp_ram_10_0_11)) + (portRef DIA9 (instanceRef pdp_ram_10_0_11)) + (portRef DIB8 (instanceRef pdp_ram_10_0_11)) + (portRef DIB7 (instanceRef pdp_ram_10_0_11)) + (portRef DIB6 (instanceRef pdp_ram_10_0_11)) + (portRef DIB5 (instanceRef pdp_ram_10_0_11)) + (portRef DIB4 (instanceRef pdp_ram_10_0_11)) + (portRef DIB3 (instanceRef pdp_ram_10_0_11)) + (portRef DIB2 (instanceRef pdp_ram_10_0_11)) + (portRef DIB1 (instanceRef pdp_ram_10_0_11)) + (portRef DIB0 (instanceRef pdp_ram_10_0_11)) + (portRef CSB2 (instanceRef pdp_ram_10_1_10)) + (portRef CSA2 (instanceRef pdp_ram_10_1_10)) + (portRef CSB1 (instanceRef pdp_ram_10_1_10)) + (portRef CSA1 (instanceRef pdp_ram_10_1_10)) + (portRef WEB (instanceRef pdp_ram_10_1_10)) + (portRef ADB2 (instanceRef pdp_ram_10_1_10)) + (portRef ADA2 (instanceRef pdp_ram_10_1_10)) + (portRef ADB1 (instanceRef pdp_ram_10_1_10)) + (portRef ADA1 (instanceRef pdp_ram_10_1_10)) + (portRef ADB0 (instanceRef pdp_ram_10_1_10)) + (portRef ADA0 (instanceRef pdp_ram_10_1_10)) + (portRef DIB17 (instanceRef pdp_ram_10_1_10)) + (portRef DIA17 (instanceRef pdp_ram_10_1_10)) + (portRef DIB16 (instanceRef pdp_ram_10_1_10)) + (portRef DIA16 (instanceRef pdp_ram_10_1_10)) + (portRef DIB15 (instanceRef pdp_ram_10_1_10)) + (portRef DIA15 (instanceRef pdp_ram_10_1_10)) + (portRef DIB14 (instanceRef pdp_ram_10_1_10)) + (portRef DIA14 (instanceRef pdp_ram_10_1_10)) + (portRef DIB13 (instanceRef pdp_ram_10_1_10)) + (portRef DIA13 (instanceRef pdp_ram_10_1_10)) + (portRef DIB12 (instanceRef pdp_ram_10_1_10)) + (portRef DIA12 (instanceRef pdp_ram_10_1_10)) + (portRef DIB11 (instanceRef pdp_ram_10_1_10)) + (portRef DIA11 (instanceRef pdp_ram_10_1_10)) + (portRef DIB10 (instanceRef pdp_ram_10_1_10)) + (portRef DIA10 (instanceRef pdp_ram_10_1_10)) + (portRef DIB9 (instanceRef pdp_ram_10_1_10)) + (portRef DIA9 (instanceRef pdp_ram_10_1_10)) + (portRef DIB8 (instanceRef pdp_ram_10_1_10)) + (portRef DIB7 (instanceRef pdp_ram_10_1_10)) + (portRef DIB6 (instanceRef pdp_ram_10_1_10)) + (portRef DIB5 (instanceRef pdp_ram_10_1_10)) + (portRef DIB4 (instanceRef pdp_ram_10_1_10)) + (portRef DIB3 (instanceRef pdp_ram_10_1_10)) + (portRef DIB2 (instanceRef pdp_ram_10_1_10)) + (portRef DIB1 (instanceRef pdp_ram_10_1_10)) + (portRef DIB0 (instanceRef pdp_ram_10_1_10)) + (portRef CSB2 (instanceRef pdp_ram_11_0_9)) + (portRef CSA2 (instanceRef pdp_ram_11_0_9)) + (portRef CSB1 (instanceRef pdp_ram_11_0_9)) + (portRef CSA1 (instanceRef pdp_ram_11_0_9)) + (portRef WEB (instanceRef pdp_ram_11_0_9)) + (portRef ADB2 (instanceRef pdp_ram_11_0_9)) + (portRef ADA2 (instanceRef pdp_ram_11_0_9)) + (portRef ADB1 (instanceRef pdp_ram_11_0_9)) + (portRef ADA1 (instanceRef pdp_ram_11_0_9)) + (portRef ADB0 (instanceRef pdp_ram_11_0_9)) + (portRef ADA0 (instanceRef pdp_ram_11_0_9)) + (portRef DIB17 (instanceRef pdp_ram_11_0_9)) + (portRef DIA17 (instanceRef pdp_ram_11_0_9)) + (portRef DIB16 (instanceRef pdp_ram_11_0_9)) + (portRef DIA16 (instanceRef pdp_ram_11_0_9)) + (portRef DIB15 (instanceRef pdp_ram_11_0_9)) + (portRef DIA15 (instanceRef pdp_ram_11_0_9)) + (portRef DIB14 (instanceRef pdp_ram_11_0_9)) + (portRef DIA14 (instanceRef pdp_ram_11_0_9)) + (portRef DIB13 (instanceRef pdp_ram_11_0_9)) + (portRef DIA13 (instanceRef pdp_ram_11_0_9)) + (portRef DIB12 (instanceRef pdp_ram_11_0_9)) + (portRef DIA12 (instanceRef pdp_ram_11_0_9)) + (portRef DIB11 (instanceRef pdp_ram_11_0_9)) + (portRef DIA11 (instanceRef pdp_ram_11_0_9)) + (portRef DIB10 (instanceRef pdp_ram_11_0_9)) + (portRef DIA10 (instanceRef pdp_ram_11_0_9)) + (portRef DIB9 (instanceRef pdp_ram_11_0_9)) + (portRef DIA9 (instanceRef pdp_ram_11_0_9)) + (portRef DIB8 (instanceRef pdp_ram_11_0_9)) + (portRef DIB7 (instanceRef pdp_ram_11_0_9)) + (portRef DIB6 (instanceRef pdp_ram_11_0_9)) + (portRef DIB5 (instanceRef pdp_ram_11_0_9)) + (portRef DIB4 (instanceRef pdp_ram_11_0_9)) + (portRef DIB3 (instanceRef pdp_ram_11_0_9)) + (portRef DIB2 (instanceRef pdp_ram_11_0_9)) + (portRef DIB1 (instanceRef pdp_ram_11_0_9)) + (portRef DIB0 (instanceRef pdp_ram_11_0_9)) + (portRef CSB2 (instanceRef pdp_ram_11_1_8)) + (portRef CSA2 (instanceRef pdp_ram_11_1_8)) + (portRef CSB1 (instanceRef pdp_ram_11_1_8)) + (portRef CSA1 (instanceRef pdp_ram_11_1_8)) + (portRef WEB (instanceRef pdp_ram_11_1_8)) + (portRef ADB2 (instanceRef pdp_ram_11_1_8)) + (portRef ADA2 (instanceRef pdp_ram_11_1_8)) + (portRef ADB1 (instanceRef pdp_ram_11_1_8)) + (portRef ADA1 (instanceRef pdp_ram_11_1_8)) + (portRef ADB0 (instanceRef pdp_ram_11_1_8)) + (portRef ADA0 (instanceRef pdp_ram_11_1_8)) + (portRef DIB17 (instanceRef pdp_ram_11_1_8)) + (portRef DIA17 (instanceRef pdp_ram_11_1_8)) + (portRef DIB16 (instanceRef pdp_ram_11_1_8)) + (portRef DIA16 (instanceRef pdp_ram_11_1_8)) + (portRef DIB15 (instanceRef pdp_ram_11_1_8)) + (portRef DIA15 (instanceRef pdp_ram_11_1_8)) + (portRef DIB14 (instanceRef pdp_ram_11_1_8)) + (portRef DIA14 (instanceRef pdp_ram_11_1_8)) + (portRef DIB13 (instanceRef pdp_ram_11_1_8)) + (portRef DIA13 (instanceRef pdp_ram_11_1_8)) + (portRef DIB12 (instanceRef pdp_ram_11_1_8)) + (portRef DIA12 (instanceRef pdp_ram_11_1_8)) + (portRef DIB11 (instanceRef pdp_ram_11_1_8)) + (portRef DIA11 (instanceRef pdp_ram_11_1_8)) + (portRef DIB10 (instanceRef pdp_ram_11_1_8)) + (portRef DIA10 (instanceRef pdp_ram_11_1_8)) + (portRef DIB9 (instanceRef pdp_ram_11_1_8)) + (portRef DIA9 (instanceRef pdp_ram_11_1_8)) + (portRef DIB8 (instanceRef pdp_ram_11_1_8)) + (portRef DIB7 (instanceRef pdp_ram_11_1_8)) + (portRef DIB6 (instanceRef pdp_ram_11_1_8)) + (portRef DIB5 (instanceRef pdp_ram_11_1_8)) + (portRef DIB4 (instanceRef pdp_ram_11_1_8)) + (portRef DIB3 (instanceRef pdp_ram_11_1_8)) + (portRef DIB2 (instanceRef pdp_ram_11_1_8)) + (portRef DIB1 (instanceRef pdp_ram_11_1_8)) + (portRef DIB0 (instanceRef pdp_ram_11_1_8)) + (portRef CSB2 (instanceRef pdp_ram_12_0_7)) + (portRef CSA2 (instanceRef pdp_ram_12_0_7)) + (portRef CSB1 (instanceRef pdp_ram_12_0_7)) + (portRef CSA1 (instanceRef pdp_ram_12_0_7)) + (portRef WEB (instanceRef pdp_ram_12_0_7)) + (portRef ADB2 (instanceRef pdp_ram_12_0_7)) + (portRef ADA2 (instanceRef pdp_ram_12_0_7)) + (portRef ADB1 (instanceRef pdp_ram_12_0_7)) + (portRef ADA1 (instanceRef pdp_ram_12_0_7)) + (portRef ADB0 (instanceRef pdp_ram_12_0_7)) + (portRef ADA0 (instanceRef pdp_ram_12_0_7)) + (portRef DIB17 (instanceRef pdp_ram_12_0_7)) + (portRef DIA17 (instanceRef pdp_ram_12_0_7)) + (portRef DIB16 (instanceRef pdp_ram_12_0_7)) + (portRef DIA16 (instanceRef pdp_ram_12_0_7)) + (portRef DIB15 (instanceRef pdp_ram_12_0_7)) + (portRef DIA15 (instanceRef pdp_ram_12_0_7)) + (portRef DIB14 (instanceRef pdp_ram_12_0_7)) + (portRef DIA14 (instanceRef pdp_ram_12_0_7)) + (portRef DIB13 (instanceRef pdp_ram_12_0_7)) + (portRef DIA13 (instanceRef pdp_ram_12_0_7)) + (portRef DIB12 (instanceRef pdp_ram_12_0_7)) + (portRef DIA12 (instanceRef pdp_ram_12_0_7)) + (portRef DIB11 (instanceRef pdp_ram_12_0_7)) + (portRef DIA11 (instanceRef pdp_ram_12_0_7)) + (portRef DIB10 (instanceRef pdp_ram_12_0_7)) + (portRef DIA10 (instanceRef pdp_ram_12_0_7)) + (portRef DIB9 (instanceRef pdp_ram_12_0_7)) + (portRef DIA9 (instanceRef pdp_ram_12_0_7)) + (portRef DIB8 (instanceRef pdp_ram_12_0_7)) + (portRef DIB7 (instanceRef pdp_ram_12_0_7)) + (portRef DIB6 (instanceRef pdp_ram_12_0_7)) + (portRef DIB5 (instanceRef pdp_ram_12_0_7)) + (portRef DIB4 (instanceRef pdp_ram_12_0_7)) + (portRef DIB3 (instanceRef pdp_ram_12_0_7)) + (portRef DIB2 (instanceRef pdp_ram_12_0_7)) + (portRef DIB1 (instanceRef pdp_ram_12_0_7)) + (portRef DIB0 (instanceRef pdp_ram_12_0_7)) + (portRef CSB2 (instanceRef pdp_ram_12_1_6)) + (portRef CSA2 (instanceRef pdp_ram_12_1_6)) + (portRef CSB1 (instanceRef pdp_ram_12_1_6)) + (portRef CSA1 (instanceRef pdp_ram_12_1_6)) + (portRef WEB (instanceRef pdp_ram_12_1_6)) + (portRef ADB2 (instanceRef pdp_ram_12_1_6)) + (portRef ADA2 (instanceRef pdp_ram_12_1_6)) + (portRef ADB1 (instanceRef pdp_ram_12_1_6)) + (portRef ADA1 (instanceRef pdp_ram_12_1_6)) + (portRef ADB0 (instanceRef pdp_ram_12_1_6)) + (portRef ADA0 (instanceRef pdp_ram_12_1_6)) + (portRef DIB17 (instanceRef pdp_ram_12_1_6)) + (portRef DIA17 (instanceRef pdp_ram_12_1_6)) + (portRef DIB16 (instanceRef pdp_ram_12_1_6)) + (portRef DIA16 (instanceRef pdp_ram_12_1_6)) + (portRef DIB15 (instanceRef pdp_ram_12_1_6)) + (portRef DIA15 (instanceRef pdp_ram_12_1_6)) + (portRef DIB14 (instanceRef pdp_ram_12_1_6)) + (portRef DIA14 (instanceRef pdp_ram_12_1_6)) + (portRef DIB13 (instanceRef pdp_ram_12_1_6)) + (portRef DIA13 (instanceRef pdp_ram_12_1_6)) + (portRef DIB12 (instanceRef pdp_ram_12_1_6)) + (portRef DIA12 (instanceRef pdp_ram_12_1_6)) + (portRef DIB11 (instanceRef pdp_ram_12_1_6)) + (portRef DIA11 (instanceRef pdp_ram_12_1_6)) + (portRef DIB10 (instanceRef pdp_ram_12_1_6)) + (portRef DIA10 (instanceRef pdp_ram_12_1_6)) + (portRef DIB9 (instanceRef pdp_ram_12_1_6)) + (portRef DIA9 (instanceRef pdp_ram_12_1_6)) + (portRef DIB8 (instanceRef pdp_ram_12_1_6)) + (portRef DIB7 (instanceRef pdp_ram_12_1_6)) + (portRef DIB6 (instanceRef pdp_ram_12_1_6)) + (portRef DIB5 (instanceRef pdp_ram_12_1_6)) + (portRef DIB4 (instanceRef pdp_ram_12_1_6)) + (portRef DIB3 (instanceRef pdp_ram_12_1_6)) + (portRef DIB2 (instanceRef pdp_ram_12_1_6)) + (portRef DIB1 (instanceRef pdp_ram_12_1_6)) + (portRef DIB0 (instanceRef pdp_ram_12_1_6)) + (portRef CSB2 (instanceRef pdp_ram_13_0_5)) + (portRef CSA2 (instanceRef pdp_ram_13_0_5)) + (portRef CSB1 (instanceRef pdp_ram_13_0_5)) + (portRef CSA1 (instanceRef pdp_ram_13_0_5)) + (portRef WEB (instanceRef pdp_ram_13_0_5)) + (portRef ADB2 (instanceRef pdp_ram_13_0_5)) + (portRef ADA2 (instanceRef pdp_ram_13_0_5)) + (portRef ADB1 (instanceRef pdp_ram_13_0_5)) + (portRef ADA1 (instanceRef pdp_ram_13_0_5)) + (portRef ADB0 (instanceRef pdp_ram_13_0_5)) + (portRef ADA0 (instanceRef pdp_ram_13_0_5)) + (portRef DIB17 (instanceRef pdp_ram_13_0_5)) + (portRef DIA17 (instanceRef pdp_ram_13_0_5)) + (portRef DIB16 (instanceRef pdp_ram_13_0_5)) + (portRef DIA16 (instanceRef pdp_ram_13_0_5)) + (portRef DIB15 (instanceRef pdp_ram_13_0_5)) + (portRef DIA15 (instanceRef pdp_ram_13_0_5)) + (portRef DIB14 (instanceRef pdp_ram_13_0_5)) + (portRef DIA14 (instanceRef pdp_ram_13_0_5)) + (portRef DIB13 (instanceRef pdp_ram_13_0_5)) + (portRef DIA13 (instanceRef pdp_ram_13_0_5)) + (portRef DIB12 (instanceRef pdp_ram_13_0_5)) + (portRef DIA12 (instanceRef pdp_ram_13_0_5)) + (portRef DIB11 (instanceRef pdp_ram_13_0_5)) + (portRef DIA11 (instanceRef pdp_ram_13_0_5)) + (portRef DIB10 (instanceRef pdp_ram_13_0_5)) + (portRef DIA10 (instanceRef pdp_ram_13_0_5)) + (portRef DIB9 (instanceRef pdp_ram_13_0_5)) + (portRef DIA9 (instanceRef pdp_ram_13_0_5)) + (portRef DIB8 (instanceRef pdp_ram_13_0_5)) + (portRef DIB7 (instanceRef pdp_ram_13_0_5)) + (portRef DIB6 (instanceRef pdp_ram_13_0_5)) + (portRef DIB5 (instanceRef pdp_ram_13_0_5)) + (portRef DIB4 (instanceRef pdp_ram_13_0_5)) + (portRef DIB3 (instanceRef pdp_ram_13_0_5)) + (portRef DIB2 (instanceRef pdp_ram_13_0_5)) + (portRef DIB1 (instanceRef pdp_ram_13_0_5)) + (portRef DIB0 (instanceRef pdp_ram_13_0_5)) + (portRef CSB2 (instanceRef pdp_ram_13_1_4)) + (portRef CSA2 (instanceRef pdp_ram_13_1_4)) + (portRef CSB1 (instanceRef pdp_ram_13_1_4)) + (portRef CSA1 (instanceRef pdp_ram_13_1_4)) + (portRef WEB (instanceRef pdp_ram_13_1_4)) + (portRef ADB2 (instanceRef pdp_ram_13_1_4)) + (portRef ADA2 (instanceRef pdp_ram_13_1_4)) + (portRef ADB1 (instanceRef pdp_ram_13_1_4)) + (portRef ADA1 (instanceRef pdp_ram_13_1_4)) + (portRef ADB0 (instanceRef pdp_ram_13_1_4)) + (portRef ADA0 (instanceRef pdp_ram_13_1_4)) + (portRef DIB17 (instanceRef pdp_ram_13_1_4)) + (portRef DIA17 (instanceRef pdp_ram_13_1_4)) + (portRef DIB16 (instanceRef pdp_ram_13_1_4)) + (portRef DIA16 (instanceRef pdp_ram_13_1_4)) + (portRef DIB15 (instanceRef pdp_ram_13_1_4)) + (portRef DIA15 (instanceRef pdp_ram_13_1_4)) + (portRef DIB14 (instanceRef pdp_ram_13_1_4)) + (portRef DIA14 (instanceRef pdp_ram_13_1_4)) + (portRef DIB13 (instanceRef pdp_ram_13_1_4)) + (portRef DIA13 (instanceRef pdp_ram_13_1_4)) + (portRef DIB12 (instanceRef pdp_ram_13_1_4)) + (portRef DIA12 (instanceRef pdp_ram_13_1_4)) + (portRef DIB11 (instanceRef pdp_ram_13_1_4)) + (portRef DIA11 (instanceRef pdp_ram_13_1_4)) + (portRef DIB10 (instanceRef pdp_ram_13_1_4)) + (portRef DIA10 (instanceRef pdp_ram_13_1_4)) + (portRef DIB9 (instanceRef pdp_ram_13_1_4)) + (portRef DIA9 (instanceRef pdp_ram_13_1_4)) + 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(portRef DIA1 (instanceRef pdp_ram_6_0_19)) + (portRef DIA1 (instanceRef pdp_ram_7_0_17)) + (portRef DIA1 (instanceRef pdp_ram_8_0_15)) + (portRef DIA1 (instanceRef pdp_ram_9_0_13)) + (portRef DIA1 (instanceRef pdp_ram_10_0_11)) + (portRef DIA1 (instanceRef pdp_ram_11_0_9)) + (portRef DIA1 (instanceRef pdp_ram_12_0_7)) + (portRef DIA1 (instanceRef pdp_ram_13_0_5)) + (portRef DIA1 (instanceRef pdp_ram_14_0_3)) + (portRef DIA1 (instanceRef pdp_ram_15_0_1)))) + (net datain0 + (joined + (portRef (member Data 17)) + (portRef DIA0 (instanceRef pdp_ram_0_0_31)) + (portRef DIA0 (instanceRef pdp_ram_1_0_29)) + (portRef DIA0 (instanceRef pdp_ram_2_0_27)) + (portRef DIA0 (instanceRef pdp_ram_3_0_25)) + (portRef DIA0 (instanceRef pdp_ram_4_0_23)) + (portRef DIA0 (instanceRef pdp_ram_5_0_21)) + (portRef DIA0 (instanceRef pdp_ram_6_0_19)) + (portRef DIA0 (instanceRef pdp_ram_7_0_17)) + (portRef DIA0 (instanceRef pdp_ram_8_0_15)) + (portRef DIA0 (instanceRef pdp_ram_9_0_13)) + (portRef DIA0 (instanceRef pdp_ram_10_0_11)) + (portRef DIA0 (instanceRef pdp_ram_11_0_9)) + (portRef DIA0 (instanceRef pdp_ram_12_0_7)) + (portRef DIA0 (instanceRef pdp_ram_13_0_5)) + (portRef DIA0 (instanceRef pdp_ram_14_0_3)) + (portRef DIA0 (instanceRef pdp_ram_15_0_1)))))))) + (design cbmnet_fifo_18x32k_dp + (cellRef cbmnet_fifo_18x32k_dp + (libraryRef ORCLIB))) +) diff --git a/cbmnet/cores/cbmnet_fifo_18x32k_dp.ipx b/cbmnet/cores/cbmnet_fifo_18x32k_dp.ipx new file mode 100644 index 0000000..fc51bd1 --- /dev/null +++ b/cbmnet/cores/cbmnet_fifo_18x32k_dp.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/cbmnet/cores/cbmnet_fifo_18x32k_dp.lpc b/cbmnet/cores/cbmnet_fifo_18x32k_dp.lpc new file mode 100644 index 0000000..72ed0ea --- /dev/null +++ b/cbmnet/cores/cbmnet_fifo_18x32k_dp.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=cbmnet_fifo_18x32k_dp +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/15/2014 +Time=12:28:36 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=18 +RDepth=32768 +RWidth=18 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=32760 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n cbmnet_fifo_18x32k_dp -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 18 -outdata REGISTERED -no_enable -pe -1 -pf 32760 -pf2 506 diff --git a/cbmnet/cores/cbmnet_fifo_18x32k_dp.vhd b/cbmnet/cores/cbmnet_fifo_18x32k_dp.vhd new file mode 100644 index 0000000..34ab5bf --- /dev/null +++ b/cbmnet/cores/cbmnet_fifo_18x32k_dp.vhd @@ -0,0 +1,4529 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n cbmnet_fifo_18x32k_dp -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 18 -regout -no_enable -pe -1 -pf 32760 -pf2 506 + +-- Wed Oct 15 12:28:36 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity cbmnet_fifo_18x32k_dp is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end cbmnet_fifo_18x32k_dp; + +architecture Structure of cbmnet_fifo_18x32k_dp is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal wptr_14_inv: std_logic; + signal rptr_14_inv: std_logic; + signal wptr_13_inv: std_logic; + signal rptr_13_inv: std_logic; + signal wptr_12_inv: std_logic; + signal rptr_12_inv: std_logic; + signal wptr_11_inv: std_logic; + signal rptr_11_inv: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r10: std_logic; + signal dec2_p00: std_logic; + signal dec5_r11: std_logic; + signal dec4_p01: std_logic; + signal dec7_r11: std_logic; + signal dec6_p01: std_logic; + signal dec9_r12: std_logic; + signal dec8_p02: std_logic; + signal dec11_r12: std_logic; + signal dec10_p02: std_logic; + signal dec13_r13: std_logic; + signal dec12_p03: std_logic; + signal dec15_r13: std_logic; + signal dec14_p03: std_logic; + signal dec17_r14: std_logic; + signal dec16_p04: std_logic; + signal dec19_r14: std_logic; + signal dec18_p04: std_logic; + signal dec21_r15: std_logic; + signal dec20_p05: std_logic; + signal dec23_r15: std_logic; + signal dec22_p05: std_logic; + signal dec25_r16: std_logic; + signal dec24_p06: std_logic; + signal dec27_r16: std_logic; + signal dec26_p06: std_logic; + signal dec29_r17: std_logic; + signal dec28_p07: std_logic; + signal dec31_r17: std_logic; + signal dec30_p07: std_logic; + signal dec33_r18: std_logic; + signal dec32_p08: std_logic; + signal dec35_r18: std_logic; + signal dec34_p08: std_logic; + signal dec37_r19: std_logic; + signal dec36_p09: std_logic; + signal dec39_r19: std_logic; + signal dec38_p09: std_logic; + signal dec41_r110: std_logic; + signal dec40_p010: std_logic; + signal dec43_r110: std_logic; + signal dec42_p010: std_logic; + signal dec45_r111: std_logic; + signal dec44_p011: std_logic; + signal dec47_r111: std_logic; + signal dec46_p011: std_logic; + signal dec49_r112: std_logic; + signal dec48_p012: std_logic; + signal dec51_r112: std_logic; + signal dec50_p012: std_logic; + signal dec53_r113: std_logic; + signal dec52_p013: std_logic; + signal dec55_r113: std_logic; + signal dec54_p013: std_logic; + signal dec57_r114: std_logic; + signal dec56_p014: std_logic; + signal dec59_r114: std_logic; + signal dec58_p014: std_logic; + signal dec61_r115: std_logic; + signal dec60_p015: std_logic; + signal dec63_r115: std_logic; + signal dec62_p015: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_15: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_11_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_14_ff: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal wcount_15: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co7_1: std_logic; + signal co6_1: std_logic; + signal rcount_15: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal mdout1_15_9: std_logic; + signal mdout1_14_9: std_logic; + signal mdout1_13_9: std_logic; + signal mdout1_12_9: std_logic; + signal mdout1_11_9: std_logic; + signal mdout1_10_9: std_logic; + signal mdout1_9_9: std_logic; + signal mdout1_8_9: std_logic; + signal mdout1_7_9: std_logic; + signal mdout1_6_9: std_logic; + signal mdout1_5_9: std_logic; + signal mdout1_4_9: std_logic; + signal mdout1_3_9: std_logic; + signal mdout1_2_9: std_logic; + signal mdout1_1_9: std_logic; + signal mdout1_0_9: std_logic; + signal mdout1_15_10: std_logic; + signal mdout1_14_10: std_logic; + signal mdout1_13_10: std_logic; + signal mdout1_12_10: std_logic; + signal mdout1_11_10: std_logic; + signal mdout1_10_10: std_logic; + signal mdout1_9_10: std_logic; + signal mdout1_8_10: std_logic; + signal mdout1_7_10: std_logic; + signal mdout1_6_10: std_logic; + signal mdout1_5_10: std_logic; + signal mdout1_4_10: std_logic; + signal mdout1_3_10: std_logic; + signal mdout1_2_10: std_logic; + signal mdout1_1_10: std_logic; + signal mdout1_0_10: std_logic; + signal mdout1_15_11: std_logic; + signal mdout1_14_11: std_logic; + signal mdout1_13_11: std_logic; + signal mdout1_12_11: std_logic; + signal mdout1_11_11: std_logic; + signal mdout1_10_11: std_logic; + signal mdout1_9_11: std_logic; + signal mdout1_8_11: std_logic; + signal mdout1_7_11: std_logic; + signal mdout1_6_11: std_logic; + signal mdout1_5_11: std_logic; + signal mdout1_4_11: std_logic; + signal mdout1_3_11: std_logic; + signal mdout1_2_11: std_logic; + signal mdout1_1_11: std_logic; + signal mdout1_0_11: std_logic; + signal mdout1_15_12: std_logic; + signal mdout1_14_12: std_logic; + signal mdout1_13_12: std_logic; + signal mdout1_12_12: std_logic; + signal mdout1_11_12: std_logic; + signal mdout1_10_12: std_logic; + signal mdout1_9_12: std_logic; + signal mdout1_8_12: std_logic; + signal mdout1_7_12: std_logic; + signal mdout1_6_12: std_logic; + signal mdout1_5_12: std_logic; + signal mdout1_4_12: std_logic; + signal mdout1_3_12: std_logic; + signal mdout1_2_12: std_logic; + signal mdout1_1_12: std_logic; + signal mdout1_0_12: std_logic; + signal mdout1_15_13: std_logic; + signal mdout1_14_13: std_logic; + signal mdout1_13_13: std_logic; + signal mdout1_12_13: std_logic; + signal mdout1_11_13: std_logic; + signal mdout1_10_13: std_logic; + signal mdout1_9_13: std_logic; + signal mdout1_8_13: std_logic; + signal mdout1_7_13: std_logic; + signal mdout1_6_13: std_logic; + signal mdout1_5_13: std_logic; + signal mdout1_4_13: std_logic; + signal mdout1_3_13: std_logic; + signal mdout1_2_13: std_logic; + signal mdout1_1_13: std_logic; + signal mdout1_0_13: std_logic; + signal mdout1_15_14: std_logic; + signal mdout1_14_14: std_logic; + signal mdout1_13_14: std_logic; + signal mdout1_12_14: std_logic; + signal mdout1_11_14: std_logic; + signal mdout1_10_14: std_logic; + signal mdout1_9_14: std_logic; + signal mdout1_8_14: std_logic; + signal mdout1_7_14: std_logic; + signal mdout1_6_14: std_logic; + signal mdout1_5_14: std_logic; + signal mdout1_4_14: std_logic; + signal mdout1_3_14: std_logic; + signal mdout1_2_14: std_logic; + signal mdout1_1_14: std_logic; + signal mdout1_0_14: std_logic; + signal mdout1_15_15: std_logic; + signal mdout1_14_15: std_logic; + signal mdout1_13_15: std_logic; + signal mdout1_12_15: std_logic; + signal mdout1_11_15: std_logic; + signal mdout1_10_15: std_logic; + signal mdout1_9_15: std_logic; + signal mdout1_8_15: std_logic; + signal mdout1_7_15: std_logic; + signal mdout1_6_15: std_logic; + signal mdout1_5_15: std_logic; + signal mdout1_4_15: std_logic; + signal mdout1_3_15: std_logic; + signal mdout1_2_15: std_logic; + signal mdout1_1_15: std_logic; + signal mdout1_0_15: std_logic; + signal mdout1_15_16: std_logic; + signal mdout1_14_16: std_logic; + signal mdout1_13_16: std_logic; + signal mdout1_12_16: std_logic; + signal mdout1_11_16: std_logic; + signal mdout1_10_16: std_logic; + signal mdout1_9_16: std_logic; + signal mdout1_8_16: std_logic; + signal mdout1_7_16: std_logic; + signal mdout1_6_16: std_logic; + signal mdout1_5_16: std_logic; + signal mdout1_4_16: std_logic; + signal mdout1_3_16: std_logic; + signal mdout1_2_16: std_logic; + signal mdout1_1_16: std_logic; + signal mdout1_0_16: std_logic; + signal rptr_14_ff2: std_logic; + signal rptr_13_ff2: std_logic; + signal rptr_12_ff2: std_logic; + signal rptr_11_ff2: std_logic; + signal mdout1_15_17: std_logic; + signal mdout1_14_17: std_logic; + signal mdout1_13_17: std_logic; + signal mdout1_12_17: std_logic; + signal mdout1_11_17: std_logic; + signal mdout1_10_17: std_logic; + signal mdout1_9_17: std_logic; + signal mdout1_8_17: std_logic; + signal mdout1_7_17: std_logic; + signal mdout1_6_17: std_logic; + signal mdout1_5_17: std_logic; + signal mdout1_4_17: std_logic; + signal mdout1_3_17: std_logic; + signal mdout1_2_17: std_logic; + signal mdout1_1_17: std_logic; + signal mdout1_0_17: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r13: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r14: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_14: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_4: std_logic; + signal iaf_setcount_6: std_logic; + signal iaf_setcount_7: std_logic; + signal co2_4: std_logic; + signal iaf_setcount_8: std_logic; + signal iaf_setcount_9: std_logic; + signal co3_4: std_logic; + signal iaf_setcount_10: std_logic; + signal iaf_setcount_11: std_logic; + signal co4_4: std_logic; + signal iaf_setcount_12: std_logic; + signal iaf_setcount_13: std_logic; + signal co5_4: std_logic; + signal iaf_setcount_14: std_logic; + signal iaf_setcount_15: std_logic; + signal co7_2: std_logic; + signal co6_4: std_logic; + signal af_setcount_15: std_logic; + signal cmp_ci_2: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_5: std_logic; + signal af_setcount_6: std_logic; + signal af_setcount_7: std_logic; + signal co3_5: std_logic; + signal af_setcount_8: std_logic; + signal af_setcount_9: std_logic; + signal co4_5: std_logic; + signal af_setcount_10: std_logic; + signal af_setcount_11: std_logic; + signal co5_5: std_logic; + signal af_setcount_12: std_logic; + signal af_setcount_13: std_logic; + signal co6_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_setcount_14: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_clrcount_0: std_logic; + signal iaf_clrcount_1: std_logic; + signal af_clr_ctr_ci: std_logic; + signal iaf_clrcount_2: std_logic; + signal iaf_clrcount_3: std_logic; + signal co0_6: std_logic; + signal iaf_clrcount_4: std_logic; + signal iaf_clrcount_5: std_logic; + signal co1_6: std_logic; + signal iaf_clrcount_6: std_logic; + signal iaf_clrcount_7: std_logic; + signal co2_6: std_logic; + signal iaf_clrcount_8: std_logic; + signal iaf_clrcount_9: std_logic; + signal co3_6: std_logic; + signal iaf_clrcount_10: std_logic; + signal iaf_clrcount_11: std_logic; + signal co4_6: std_logic; + signal iaf_clrcount_12: std_logic; + signal iaf_clrcount_13: std_logic; + signal co5_6: std_logic; + signal iaf_clrcount_14: std_logic; + signal iaf_clrcount_15: std_logic; + signal co7_3: std_logic; + signal co6_6: std_logic; + signal af_clrcount_15: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_clrcount_0: std_logic; + signal af_clrcount_1: std_logic; + signal co0_7: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_clrcount_2: std_logic; + signal af_clrcount_3: std_logic; + signal co1_7: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal af_clrcount_4: std_logic; + signal af_clrcount_5: std_logic; + signal co2_7: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal af_clrcount_6: std_logic; + signal af_clrcount_7: std_logic; + signal co3_7: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal af_clrcount_8: std_logic; + signal af_clrcount_9: std_logic; + signal co4_7: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal af_clrcount_10: std_logic; + signal af_clrcount_11: std_logic; + signal co5_7: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w13: std_logic; + signal af_clrcount_12: std_logic; + signal af_clrcount_13: std_logic; + signal co6_7: std_logic; + signal rcount_w14: std_logic; + signal af_clr_cmp_clr: std_logic; + signal af_clrcount_14: std_logic; + signal af_clr_cmp_set: std_logic; + signal af_clr: std_logic; + signal af_clr_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX161 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; SD1: in std_logic; SD2: in std_logic; + SD3: in std_logic; SD4: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; + attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_29 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_29 : label is ""; + attribute RESETMODE of pdp_ram_1_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_1_28 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_28 : label is ""; + attribute RESETMODE of pdp_ram_1_1_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_27 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_27 : label is ""; + attribute RESETMODE of pdp_ram_2_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_1_26 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_26 : label is ""; + attribute RESETMODE of pdp_ram_2_1_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_25 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_25 : label is ""; + attribute RESETMODE of pdp_ram_3_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_1_24 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_24 : label is ""; + attribute RESETMODE of pdp_ram_3_1_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_23 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_23 : label is ""; + attribute RESETMODE of pdp_ram_4_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_1_22 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_1_22 : label is ""; + attribute RESETMODE of pdp_ram_4_1_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_21 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_21 : label is ""; + attribute RESETMODE of pdp_ram_5_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_1_20 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_1_20 : label is ""; + attribute RESETMODE of pdp_ram_5_1_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_19 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_19 : label is ""; + attribute RESETMODE of pdp_ram_6_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_1_18 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_1_18 : label is ""; + attribute RESETMODE of pdp_ram_6_1_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_17 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_17 : label is ""; + attribute RESETMODE of pdp_ram_7_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_1_16 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_1_16 : label is ""; + attribute RESETMODE of pdp_ram_7_1_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_15 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_15 : label is ""; + attribute RESETMODE of pdp_ram_8_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_1_14 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_1_14 : label is ""; + attribute RESETMODE of pdp_ram_8_1_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_13 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_13 : label is ""; + attribute RESETMODE of pdp_ram_9_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_1_12 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_1_12 : label is ""; + attribute RESETMODE of pdp_ram_9_1_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_11 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_11 : label is ""; + attribute RESETMODE of pdp_ram_10_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_1_10 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_1_10 : label is ""; + attribute RESETMODE of pdp_ram_10_1_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_9 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_9 : label is ""; + attribute RESETMODE of pdp_ram_11_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_1_8 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_1_8 : label is ""; + attribute RESETMODE of pdp_ram_11_1_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_7 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_7 : label is ""; + attribute RESETMODE of pdp_ram_12_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_1_6 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_1_6 : label is ""; + attribute RESETMODE of pdp_ram_12_1_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_5 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_5 : label is ""; + attribute RESETMODE of pdp_ram_13_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_1_4 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_1_4 : label is ""; + attribute RESETMODE of pdp_ram_13_1_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_3 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_3 : label is ""; + attribute RESETMODE of pdp_ram_14_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_1_2 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_1_2 : label is ""; + attribute RESETMODE of pdp_ram_14_1_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_1 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_1 : label is ""; + attribute RESETMODE of pdp_ram_15_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_1_0 : label is "cbmnet_fifo_18x32k_dp.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_1_0 : label is ""; + attribute RESETMODE of pdp_ram_15_1_0 : label is "SYNC"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t32: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_9: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t31: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_8: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t30: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t29: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t28: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t27: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t26: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t25: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t24: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t23: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t22: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t21: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t20: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t19: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t18: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t17: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t16: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t15: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t14: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t13: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t12: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t11: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t10: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t9: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t8: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t7: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t6: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t5: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t4: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t3: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t2: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t1: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t0: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + INV_7: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_6: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_5: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_4: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec0_p00); + + INV_3: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_2: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_1: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_0: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec1_r10); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec2_p00); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec3_r10); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec4_p01); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec5_r11); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec6_p01); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec7_r11); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec8_p02); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec9_r12); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec10_p02); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec11_r12); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec12_p03); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec13_r13); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec14_p03); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec15_r13); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec16_p04); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec17_r14); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec18_p04); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec19_r14); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec20_p05); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec21_r15); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec22_p05); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec23_r15); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec24_p06); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec25_r16); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec26_p06); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec27_r16); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec28_p07); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec29_r17); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec30_p07); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec31_r17); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec32_p08); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec33_r18); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec34_p08); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec35_r18); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec36_p09); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec37_r19); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec38_p09); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec39_r19); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec40_p010); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec41_r110); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec42_p010); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec43_r110); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec44_p011); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec45_r111); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec46_p011); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec47_r111); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec48_p012); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec49_r112); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec50_p012); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec51_r112); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec52_p013); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec53_r113); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec54_p013); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec55_r113); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec56_p014); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec57_r114); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec58_p014); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec59_r114); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>dec60_p015); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>dec61_r115); + + LUT4_52: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>dec62_p015); + + LUT4_51: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>dec63_r115); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, + DO0=>r_g2b_xor_cluster_0); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_3); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>scuba_vlo, DO0=>rcount_w13); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w9); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w23, DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w1); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w0); + + LUT4_8: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_7: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_6: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_5: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_4: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_set); + + LUT4_3: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_clr); + + LUT4_2: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_clrcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_set); + + LUT4_1: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_clrcount_15, AD2=>wcount_15, + AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_clr); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_1_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec2_p00, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec3_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, + DOB2=>mdout1_0_11, DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, + DOB5=>mdout1_0_14, DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, + DOB8=>mdout1_0_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec4_p01, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec5_r11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_1_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec6_p01, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec7_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, + DOB2=>mdout1_1_11, DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, + DOB5=>mdout1_1_14, DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, + DOB8=>mdout1_1_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec8_p02, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec9_r12, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_1_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec10_p02, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec11_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, + DOB2=>mdout1_2_11, DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, + DOB5=>mdout1_2_14, DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, + DOB8=>mdout1_2_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec12_p03, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec13_r13, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_1_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec14_p03, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec15_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, + DOB2=>mdout1_3_11, DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, + DOB5=>mdout1_3_14, DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, + DOB8=>mdout1_3_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec16_p04, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec17_r14, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_1_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec18_p04, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec19_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_4_9, DOB1=>mdout1_4_10, + DOB2=>mdout1_4_11, DOB3=>mdout1_4_12, DOB4=>mdout1_4_13, + DOB5=>mdout1_4_14, DOB6=>mdout1_4_15, DOB7=>mdout1_4_16, + DOB8=>mdout1_4_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec20_p05, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec21_r15, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_1_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec22_p05, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec23_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_5_9, DOB1=>mdout1_5_10, + DOB2=>mdout1_5_11, DOB3=>mdout1_5_12, DOB4=>mdout1_5_13, + DOB5=>mdout1_5_14, DOB6=>mdout1_5_15, DOB7=>mdout1_5_16, + DOB8=>mdout1_5_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec24_p06, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec25_r16, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_1_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec26_p06, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec27_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_6_9, DOB1=>mdout1_6_10, + DOB2=>mdout1_6_11, DOB3=>mdout1_6_12, DOB4=>mdout1_6_13, + DOB5=>mdout1_6_14, DOB6=>mdout1_6_15, DOB7=>mdout1_6_16, + DOB8=>mdout1_6_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec28_p07, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec29_r17, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_1_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec30_p07, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec31_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_7_9, DOB1=>mdout1_7_10, + DOB2=>mdout1_7_11, DOB3=>mdout1_7_12, DOB4=>mdout1_7_13, + DOB5=>mdout1_7_14, DOB6=>mdout1_7_15, DOB7=>mdout1_7_16, + DOB8=>mdout1_7_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec32_p08, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec33_r18, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_1_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec34_p08, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec35_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_8_9, DOB1=>mdout1_8_10, + DOB2=>mdout1_8_11, DOB3=>mdout1_8_12, DOB4=>mdout1_8_13, + DOB5=>mdout1_8_14, DOB6=>mdout1_8_15, DOB7=>mdout1_8_16, + DOB8=>mdout1_8_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec36_p09, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec37_r19, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_1_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>dec38_p09, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec39_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_9_9, DOB1=>mdout1_9_10, + DOB2=>mdout1_9_11, DOB3=>mdout1_9_12, DOB4=>mdout1_9_13, + DOB5=>mdout1_9_14, DOB6=>mdout1_9_15, DOB7=>mdout1_9_16, + DOB8=>mdout1_9_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec40_p010, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec41_r110, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, + DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, + DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, + DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_10_1_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec42_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec43_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_10_9, DOB1=>mdout1_10_10, + DOB2=>mdout1_10_11, DOB3=>mdout1_10_12, DOB4=>mdout1_10_13, + DOB5=>mdout1_10_14, DOB6=>mdout1_10_15, DOB7=>mdout1_10_16, + DOB8=>mdout1_10_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_11_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec44_p011, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec45_r111, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, + DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, + DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, + DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_11_1_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec46_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec47_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_11_9, DOB1=>mdout1_11_10, + DOB2=>mdout1_11_11, DOB3=>mdout1_11_12, DOB4=>mdout1_11_13, + DOB5=>mdout1_11_14, DOB6=>mdout1_11_15, DOB7=>mdout1_11_16, + DOB8=>mdout1_11_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_12_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec48_p012, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec49_r112, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, + DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, + DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, + DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_12_1_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec50_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec51_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_12_9, DOB1=>mdout1_12_10, + DOB2=>mdout1_12_11, DOB3=>mdout1_12_12, DOB4=>mdout1_12_13, + DOB5=>mdout1_12_14, DOB6=>mdout1_12_15, DOB7=>mdout1_12_16, + DOB8=>mdout1_12_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_13_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec52_p013, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec53_r113, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, + DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, + DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, + DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_13_1_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec54_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec55_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_13_9, DOB1=>mdout1_13_10, + DOB2=>mdout1_13_11, DOB3=>mdout1_13_12, DOB4=>mdout1_13_13, + DOB5=>mdout1_13_14, DOB6=>mdout1_13_15, DOB7=>mdout1_13_16, + DOB8=>mdout1_13_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_14_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec56_p014, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec57_r114, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, + DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, + DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, + DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_14_1_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec58_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec59_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_14_9, DOB1=>mdout1_14_10, + DOB2=>mdout1_14_11, DOB3=>mdout1_14_12, DOB4=>mdout1_14_13, + DOB5=>mdout1_14_14, DOB6=>mdout1_14_15, DOB7=>mdout1_14_16, + DOB8=>mdout1_14_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_15_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec60_p015, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>dec61_r115, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, + DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, + DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, + DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_15_1_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec62_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>dec63_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_15_9, DOB1=>mdout1_15_10, + DOB2=>mdout1_15_11, DOB3=>mdout1_15_12, DOB4=>mdout1_15_13, + DOB5=>mdout1_15_14, DOB6=>mdout1_15_15, DOB7=>mdout1_15_16, + DOB8=>mdout1_15_17, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_202: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_201: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_200: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_199: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_198: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_197: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_196: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_195: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_194: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_193: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_192: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_191: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_190: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_189: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_188: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_187: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_186: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_185: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_184: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_183: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_182: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_181: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_180: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_179: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_178: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_177: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_176: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_175: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_174: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_173: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_172: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_171: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_170: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_169: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_168: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_167: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_166: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_165: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_164: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_163: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_162: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_161: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_160: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_159: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_158: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_157: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_156: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_155: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_154: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_153: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_152: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_151: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_150: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_149: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_148: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_147: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_146: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_145: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_144: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_143: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_142: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_141: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_140: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_139: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_138: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_137: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_136: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_135: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_134: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_133: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_132: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_131: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_130: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_129: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_128: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_127: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_126: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_125: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_124: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_123: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_122: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_121: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_120: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_119: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_118: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_117: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_116: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_115: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_114: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_113: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_112: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_111: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_110: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_109: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_108: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_107: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_106: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_105: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_104: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_103: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_102: FD1P3DX + port map (D=>rptr_11_ff, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff2); + + FF_101: FD1P3DX + port map (D=>rptr_12_ff, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff2); + + FF_100: FD1P3DX + port map (D=>rptr_13_ff, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff2); + + FF_99: FD1P3DX + port map (D=>rptr_14_ff, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff2); + + FF_98: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_97: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_96: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_95: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_94: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_93: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_92: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_91: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_90: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_89: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_88: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_87: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_86: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_85: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_84: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_83: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_82: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_81: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_80: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_79: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_78: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_77: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_76: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_75: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_74: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_73: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_72: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_71: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_70: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_69: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_68: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_67: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_66: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_65: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_64: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_63: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_62: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_61: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_60: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_59: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_58: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_57: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_56: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_55: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_54: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_53: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_52: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_51: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_50: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_49: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_48: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_47: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_46: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_45: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_44: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_43: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_42: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_41: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_40: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_39: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_38: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_37: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_36: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_35: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_34: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_33: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_32: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_31: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_30: FD1P3DX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_29: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_28: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_27: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); + + FF_26: FD1P3DX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_6); + + FF_25: FD1P3DX + port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_7); + + FF_24: FD1P3DX + port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_8); + + FF_23: FD1P3DX + port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_9); + + FF_22: FD1P3DX + port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_10); + + FF_21: FD1P3DX + port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_11); + + FF_20: FD1P3DX + port map (D=>iaf_setcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_12); + + FF_19: FD1P3DX + port map (D=>iaf_setcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_13); + + FF_18: FD1P3DX + port map (D=>iaf_setcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_14); + + FF_17: FD1P3DX + port map (D=>iaf_setcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_15); + + FF_16: FD1P3BX + port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_0); + + FF_15: FD1P3BX + port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_1); + + FF_14: FD1P3BX + port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_2); + + FF_13: FD1P3DX + port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_3); + + FF_12: FD1P3DX + port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_4); + + FF_11: FD1P3DX + port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_5); + + FF_10: FD1P3DX + port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_6); + + FF_9: FD1P3DX + port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_7); + + FF_8: FD1P3DX + port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_8); + + FF_7: FD1P3BX + port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_9); + + FF_6: FD1P3BX + port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_10); + + FF_5: FD1P3BX + port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_11); + + FF_4: FD1P3BX + port map (D=>iaf_clrcount_12, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_12); + + FF_3: FD1P3BX + port map (D=>iaf_clrcount_13, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_13); + + FF_2: FD1P3BX + port map (D=>iaf_clrcount_14, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_14); + + FF_1: FD1P3DX + port map (D=>iaf_clrcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_15); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + mux_17: MUX161 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(0)); + + mux_16: MUX161 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(1)); + + mux_15: MUX161 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(2)); + + mux_14: MUX161 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(3)); + + mux_13: MUX161 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(4)); + + mux_12: MUX161 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(5)); + + mux_11: MUX161 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(6)); + + mux_10: MUX161 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(7)); + + mux_9: MUX161 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(8)); + + mux_8: MUX161 + port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, + D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9, + D6=>mdout1_6_9, D7=>mdout1_7_9, D8=>mdout1_8_9, + D9=>mdout1_9_9, D10=>mdout1_10_9, D11=>mdout1_11_9, + D12=>mdout1_12_9, D13=>mdout1_13_9, D14=>mdout1_14_9, + D15=>mdout1_15_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(9)); + + mux_7: MUX161 + port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, + D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10, + D6=>mdout1_6_10, D7=>mdout1_7_10, D8=>mdout1_8_10, + D9=>mdout1_9_10, D10=>mdout1_10_10, D11=>mdout1_11_10, + D12=>mdout1_12_10, D13=>mdout1_13_10, D14=>mdout1_14_10, + D15=>mdout1_15_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(10)); + + mux_6: MUX161 + port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, + D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11, + D6=>mdout1_6_11, D7=>mdout1_7_11, D8=>mdout1_8_11, + D9=>mdout1_9_11, D10=>mdout1_10_11, D11=>mdout1_11_11, + D12=>mdout1_12_11, D13=>mdout1_13_11, D14=>mdout1_14_11, + D15=>mdout1_15_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(11)); + + mux_5: MUX161 + port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, + D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12, + D6=>mdout1_6_12, D7=>mdout1_7_12, D8=>mdout1_8_12, + D9=>mdout1_9_12, D10=>mdout1_10_12, D11=>mdout1_11_12, + D12=>mdout1_12_12, D13=>mdout1_13_12, D14=>mdout1_14_12, + D15=>mdout1_15_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(12)); + + mux_4: MUX161 + port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, + D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13, + D6=>mdout1_6_13, D7=>mdout1_7_13, D8=>mdout1_8_13, + D9=>mdout1_9_13, D10=>mdout1_10_13, D11=>mdout1_11_13, + D12=>mdout1_12_13, D13=>mdout1_13_13, D14=>mdout1_14_13, + D15=>mdout1_15_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(13)); + + mux_3: MUX161 + port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, + D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14, + D6=>mdout1_6_14, D7=>mdout1_7_14, D8=>mdout1_8_14, + D9=>mdout1_9_14, D10=>mdout1_10_14, D11=>mdout1_11_14, + D12=>mdout1_12_14, D13=>mdout1_13_14, D14=>mdout1_14_14, + D15=>mdout1_15_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(14)); + + mux_2: MUX161 + port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, + D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15, + D6=>mdout1_6_15, D7=>mdout1_7_15, D8=>mdout1_8_15, + D9=>mdout1_9_15, D10=>mdout1_10_15, D11=>mdout1_11_15, + D12=>mdout1_12_15, D13=>mdout1_13_15, D14=>mdout1_14_15, + D15=>mdout1_15_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(15)); + + mux_1: MUX161 + port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, + D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16, + D6=>mdout1_6_16, D7=>mdout1_7_16, D8=>mdout1_8_16, + D9=>mdout1_9_16, D10=>mdout1_10_16, D11=>mdout1_11_16, + D12=>mdout1_12_16, D13=>mdout1_13_16, D14=>mdout1_14_16, + D15=>mdout1_15_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(16)); + + mux_0: MUX161 + port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, + D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17, + D6=>mdout1_6_17, D7=>mdout1_7_17, D8=>mdout1_8_17, + D9=>mdout1_9_17, D10=>mdout1_10_17, D11=>mdout1_11_17, + D12=>mdout1_12_17, D13=>mdout1_13_17, D14=>mdout1_14_17, + D15=>mdout1_15_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(17)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r13, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>empty_cmp_set, B0=>wcount_r14, + B1=>empty_cmp_clr, CI=>co6_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w13, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w14, + B1=>full_cmp_clr, CI=>co6_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_ctr_3: CU2 + port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7, + CO=>co3_4, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); + + af_set_ctr_4: CU2 + port map (CI=>co3_4, PC0=>af_setcount_8, PC1=>af_setcount_9, + CO=>co4_4, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9); + + af_set_ctr_5: CU2 + port map (CI=>co4_4, PC0=>af_setcount_10, PC1=>af_setcount_11, + CO=>co5_4, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11); + + af_set_ctr_6: CU2 + port map (CI=>co5_4, PC0=>af_setcount_12, PC1=>af_setcount_13, + CO=>co6_4, NC0=>iaf_setcount_12, NC1=>iaf_setcount_13); + + af_set_ctr_7: CU2 + port map (CI=>co6_4, PC0=>af_setcount_14, PC1=>af_setcount_15, + CO=>co7_2, NC0=>iaf_setcount_14, NC1=>iaf_setcount_15); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_5, GE=>co2_5); + + af_set_cmp_3: AGEB2 + port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_5, GE=>co3_5); + + af_set_cmp_4: AGEB2 + port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_5, GE=>co4_5); + + af_set_cmp_5: AGEB2 + port map (A0=>af_setcount_10, A1=>af_setcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_5, GE=>co5_5); + + af_set_cmp_6: AGEB2 + port map (A0=>af_setcount_12, A1=>af_setcount_13, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_5, + GE=>co6_5); + + af_set_cmp_7: AGEB2 + port map (A0=>af_setcount_14, A1=>af_set_cmp_set, B0=>rcount_w14, + B1=>af_set_cmp_clr, CI=>co6_5, GE=>af_set_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_clr_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open, + S1=>open); + + af_clr_ctr_0: CU2 + port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0, + PC1=>af_clrcount_1, CO=>co0_6, NC0=>iaf_clrcount_0, + NC1=>iaf_clrcount_1); + + af_clr_ctr_1: CU2 + port map (CI=>co0_6, PC0=>af_clrcount_2, PC1=>af_clrcount_3, + CO=>co1_6, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3); + + af_clr_ctr_2: CU2 + port map (CI=>co1_6, PC0=>af_clrcount_4, PC1=>af_clrcount_5, + CO=>co2_6, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5); + + af_clr_ctr_3: CU2 + port map (CI=>co2_6, PC0=>af_clrcount_6, PC1=>af_clrcount_7, + CO=>co3_6, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7); + + af_clr_ctr_4: CU2 + port map (CI=>co3_6, PC0=>af_clrcount_8, PC1=>af_clrcount_9, + CO=>co4_6, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9); + + af_clr_ctr_5: CU2 + port map (CI=>co4_6, PC0=>af_clrcount_10, PC1=>af_clrcount_11, + CO=>co5_6, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11); + + af_clr_ctr_6: CU2 + port map (CI=>co5_6, PC0=>af_clrcount_12, PC1=>af_clrcount_13, + CO=>co6_6, NC0=>iaf_clrcount_12, NC1=>iaf_clrcount_13); + + af_clr_ctr_7: CU2 + port map (CI=>co6_6, PC0=>af_clrcount_14, PC1=>af_clrcount_15, + CO=>co7_3, NC0=>iaf_clrcount_14, NC1=>iaf_clrcount_15); + + af_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_clr_cmp_0: AGEB2 + port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7); + + af_clr_cmp_1: AGEB2 + port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_7, GE=>co1_7); + + af_clr_cmp_2: AGEB2 + port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_7, GE=>co2_7); + + af_clr_cmp_3: AGEB2 + port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_7, GE=>co3_7); + + af_clr_cmp_4: AGEB2 + port map (A0=>af_clrcount_8, A1=>af_clrcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_7, GE=>co4_7); + + af_clr_cmp_5: AGEB2 + port map (A0=>af_clrcount_10, A1=>af_clrcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_7, GE=>co5_7); + + af_clr_cmp_6: AGEB2 + port map (A0=>af_clrcount_12, A1=>af_clrcount_13, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_7, + GE=>co6_7); + + af_clr_cmp_7: AGEB2 + port map (A0=>af_clrcount_14, A1=>af_clr_cmp_set, B0=>rcount_w14, + B1=>af_clr_cmp_clr, CI=>co6_7, GE=>af_clr_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr, + S1=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostFull <= af; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of cbmnet_fifo_18x32k_dp is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX161 use entity ecp3.MUX161(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on