From: Jan Michel Date: Fri, 28 Jul 2017 06:47:40 +0000 (+0200) Subject: add Munich Skyroc board to docu X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=df3ed79c26ca7099671d11a2461d6ec81b3c8741;p=daqdocu.git add Munich Skyroc board to docu --- diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex index 23eab85..a16f64a 100644 --- a/trb3/Trb3GeneralRemarks.tex +++ b/trb3/Trb3GeneralRemarks.tex @@ -101,7 +101,9 @@ Second, the upper 16 Bit of the Hardware Version register as described below is \end{warning} \subsection{Design Identification} -The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (register 0x42) that has to be set according to the following rules: The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and have to contain one of the following values: +The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (register 0x42) that has to be set according to the following rules: +The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and +have to contain one of the following values. The last digit should be used to denote the hardware revision. \begin{description*} \item[9000] design is for the central FPGA \item[9100] design is for either of the peripheral FPGAs @@ -114,6 +116,7 @@ The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (reg \item[9500] design for Trb3sc \item[9600] design for DiRich \item[9700] design for DiRich Combiner module + \item[9900] design for Munich Skyroc boards \end{description*} The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine