From: Cahit <c.ugur@gsi.de>
Date: Wed, 3 Dec 2014 08:25:49 +0000 (+0100)
Subject: conflict fix
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e0391661d3df22e0ba400afa856e178a6cb38229;p=trb3.git

conflict fix
---

e0391661d3df22e0ba400afa856e178a6cb38229
diff --cc tdc_releases/tdc_v1.6.3/tdc_components.vhd
index f5d30b8,720eeed..a0a0822
--- a/tdc_releases/tdc_v1.6.3/tdc_components.vhd
+++ b/tdc_releases/tdc_v1.6.3/tdc_components.vhd
@@@ -3,11 -3,10 +3,12 @@@ use ieee.std_logic_1164.all
  use ieee.numeric_std.all;
  library work;
  use work.trb_net_std.all;
+ use work.trb3_components.all;
  
  package tdc_components is
 -  
 +
 +  type unsigned_array_8 is array (integer range <>) of unsigned(7 downto 0);
 +    
    component TDC is
      generic (
        CHANNEL_NUMBER : integer range 2 to 65;
@@@ -386,60 -569,64 +571,110 @@@
        Q          : out std_logic_vector(7 downto 0));
    end component;
  
 -  component ROM4_Encoder is
 +  component bit_sync
 +    generic (
 +      DEPTH : integer);
      port (
 -      Address    : in  std_logic_vector(9 downto 0);
 -      OutClock   : in  std_logic;
 -      OutClockEn : in  std_logic;
 -      Reset      : in  std_logic;
 -      Q          : out std_logic_vector(7 downto 0));
 -  end component ROM4_Encoder;
 +      RESET : in  std_logic;
 +      CLK0  : in  std_logic;
 +      CLK1  : in  std_logic;
 +      D_IN  : in  std_logic;
 +      D_OUT : out std_logic);
 +  end component;
 +
 +  component edge_to_pulse
 +    port (
 +      clock     : in  std_logic;
 +      en_clk    : in  std_logic;
 +      signal_in : in  std_logic;
 +      pulse     : out std_logic);
 +  end component;
 +
 +  component risingEdgeDetect is
 +    port (
 +      CLK       : in  std_logic;
 +      SIGNAL_IN : in  std_logic;
 +      PULSE_OUT : out std_logic);
 +  end component risingEdgeDetect;
 +
 +  component fallingEdgeDetect is
 +    port (
 +      CLK       : in  std_logic;
 +      SIGNAL_IN : in  std_logic;
 +      PULSE_OUT : out std_logic);
 +  end component fallingEdgeDetect;
 +
 +  component ShiftRegisterSISO
 +    generic (
 +      DEPTH : integer range 1 to 32;
 +      WIDTH : integer range 1 to 32);
 +    port (
 +      CLK   : in  std_logic;
 +      D_IN  : in  std_logic_vector(WIDTH-1 downto 0);
 +      D_OUT : out std_logic_vector(WIDTH-1 downto 0));
 +  end component;
 +
 +  component Stretcher
 +    port (
 +      PULSE_IN  : in  std_logic;
 +      PULSE_OUT : out std_logic);
 +  end component;
 +
 +  component WaveLauncher is
 +    port (
 +      HIT_IN  : in  std_logic;
 +      HIT_OUT : out std_logic);
 +  end component WaveLauncher;
  
+   component bit_sync
+     generic (
+       DEPTH : integer);
+     port (
+       RESET : in  std_logic;
+       CLK0  : in  std_logic;
+       CLK1  : in  std_logic;
+       D_IN  : in  std_logic;
+       D_OUT : out std_logic);
+   end component;
+ 
+   component edge_to_pulse
+     port (
+       clock     : in  std_logic;
+       en_clk    : in  std_logic;
+       signal_in : in  std_logic;
+       pulse     : out std_logic);
+   end component;
+ 
+   component risingEdgeDetect is
+     port (
+       CLK       : in  std_logic;
+       SIGNAL_IN : in  std_logic;
+       PULSE_OUT : out std_logic);
+   end component risingEdgeDetect;
+ 
+   component fallingEdgeDetect is
+     port (
+       CLK       : in  std_logic;
+       SIGNAL_IN : in  std_logic;
+       PULSE_OUT : out std_logic);
+   end component fallingEdgeDetect;
+ 
+   component ShiftRegisterSISO
+     generic (
+       DEPTH : integer range 1 to 32;
+       WIDTH : integer range 1 to 32);
+     port (
+       CLK   : in  std_logic;
+       D_IN  : in  std_logic_vector(WIDTH-1 downto 0);
+       D_OUT : out std_logic_vector(WIDTH-1 downto 0));
+   end component;
+ 
+   component Stretcher
+     port (
+       PULSE_IN  : in  std_logic;
+       PULSE_OUT : out std_logic);
+   end component;
+ 
  
+   
  end package tdc_components;