From: Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Date: Fri, 7 Aug 2020 14:50:38 +0000 (+0200)
Subject: endpoint_test: Remove outdated testbenches
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e057616f5fc7c0e5517b7a71ed2c22c3867aefe5;p=cri.git

endpoint_test: Remove outdated testbenches
---

diff --git a/endpoint_test/endpoint_test.xpr b/endpoint_test/endpoint_test.xpr
index a3be410..afb4a2d 100644
--- a/endpoint_test/endpoint_test.xpr
+++ b/endpoint_test/endpoint_test.xpr
@@ -566,20 +566,9 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/sim/testbench_endpoint_hades_full_handler.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/sim/testbench_read_dna_address.vhd">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="tb"/>
+        <Option Name="TopModule" Val="endpoint_test"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
diff --git a/endpoint_test/sim/testbench_endpoint_hades_full_handler.vhd b/endpoint_test/sim/testbench_endpoint_hades_full_handler.vhd
deleted file mode 100644
index 53dbc97..0000000
--- a/endpoint_test/sim/testbench_endpoint_hades_full_handler.vhd
+++ /dev/null
@@ -1,535 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-
-entity tb is
-
-end entity;
-
-
-architecture tb_arch of tb is
-  constant NUMBER_OF_ADC         : integer := 1;
-
-  signal clk                     : std_logic                        := '1';
-  signal reset                   : std_logic                        := '1';
-
-  signal med_data_in             : std_logic_vector (16-1 downto 0) := (others => '0');
-  signal med_packet_num_in       : std_logic_vector (3-1  downto 0) := (others => '0');
-  signal med_dataready_in        : std_logic                        := '0';
-  signal med_read_in             : std_logic                        := '0';
-  signal med_data_out            : std_logic_vector (16-1 downto 0) := (others => '0');
-  signal med_packet_num_out      : std_logic_vector (3-1  downto 0) := (others => '0');
-  signal med_dataready_out       : std_logic                        := '0';
-  signal med_read_out            : std_logic                        := '0';
-  signal med_stat_op             : std_logic_vector (16-1 downto 0) := (others => '0');
-  signal med_ctrl_op             : std_logic_vector (16-1 downto 0) := (others => '0');
-  signal med_stat_debug          : std_logic_vector (64-1 downto 0) := (others => '0');
-
-
-  --endpoint LVL1 trigger
-  signal trg_type                : std_logic_vector (3  downto 0)   := (others => '0');
-  signal trg_valid_timing        : std_logic                        := '0';
-  signal trg_valid_notiming      : std_logic                        := '0';
-  signal trg_invalid             : std_logic                        := '0';
-  signal trg_data_valid          : std_logic                        := '0';
-  signal trg_number              : std_logic_vector (15 downto 0)   := (others => '0');
-  signal trg_code                : std_logic_vector (7  downto 0)   := (others => '0');
-  signal trg_information         : std_logic_vector (23 downto 0)   := (others => '0');
-  signal trg_error_pattern       : std_logic_vector (31 downto 0)   := (others => '0');
-  signal trg_release             : std_logic                        := '0';
-  signal trg_int_trg_number      : std_logic_vector (15 downto 0)   := (others => '0');
-
-  --FEE
-  signal fee_trg_release         : std_logic_vector (NUMBER_OF_ADC-1 downto 0)     := (others => '0');
-  signal fee_trg_statusbits      : std_logic_vector (NUMBER_OF_ADC*32-1 downto 0)  := (others => '0');
-  signal fee_data                : std_logic_vector (NUMBER_OF_ADC*32-1 downto 0)  := (others => '0');
-  signal fee_data_write          : std_logic_vector (NUMBER_OF_ADC-1 downto 0)     := (others => '0');
-  signal fee_data_finished       : std_logic_vector (NUMBER_OF_ADC-1 downto 0)     := (others => '0');
-  signal fee_data_almost_full    : std_logic_vector (NUMBER_OF_ADC-1 downto 0)     := (others => '0');
-
-  signal timing_trg              : std_logic                        := '0';
-
-  signal timer                   : unsigned(31 downto 0)            := (others => '0');
-  signal event                   : unsigned(15 downto 0)            := (others => '0');
-  signal eventvec                : std_logic_vector(15 downto 0)    := (others => '0');
-  signal readoutevent            : unsigned(15 downto 0)            := (others => '0');
-
-begin
-
- UUT : trb_net16_endpoint_hades_full
- generic map(
-    ADDRESS_MASK                 => x"FFFF",
-    BROADCAST_BITMASK            => x"FF",
-    BROADCAST_SPECIAL_ADDR       => x"81",
-    REGIO_INIT_ENDPOINT_ID       => x"0001",
-    REGIO_USE_VAR_ENDPOINT_ID    => c_YES,
-    REGIO_USE_1WIRE_INTERFACE    => c_XDNA,
-    REGIO_INIT_ADDRESS           => x"F352",
-    TIMING_TRIGGER_RAW           => c_YES
-      )
-    port map(
-      CLK                        => CLK,
-      RESET                      => RESET,
-      CLK_EN                     => '1',
-
-      MED_DATAREADY_OUT          => med_dataready_out,
-      MED_DATA_OUT               => med_data_out,
-      MED_PACKET_NUM_OUT         => med_packet_num_out,
-      MED_READ_IN                => med_read_in,
-      MED_DATAREADY_IN           => med_dataready_in,
-      MED_DATA_IN                => med_data_in,
-      MED_PACKET_NUM_IN          => med_packet_num_in,
-      MED_READ_OUT               => med_read_out,
-      MED_STAT_OP_IN             => med_stat_op,
-      MED_CTRL_OP_OUT            => med_ctrl_op,
-
-      -- LVL1 trigger APL
-      TRG_TIMING_TRG_RECEIVED_IN => timing_trg,
-      LVL1_TRG_DATA_VALID_OUT    => trg_data_valid,
-      LVL1_TRG_VALID_TIMING_OUT  => trg_valid_timing,
-      LVL1_TRG_VALID_NOTIMING_OUT=> trg_valid_notiming,
-      LVL1_TRG_INVALID_OUT       => trg_invalid,
-      
-      LVL1_TRG_TYPE_OUT          => trg_type,
-      LVL1_TRG_NUMBER_OUT        => trg_number,
-      LVL1_TRG_CODE_OUT          => trg_code,
-      LVL1_TRG_INFORMATION_OUT   => trg_information,
-      LVL1_ERROR_PATTERN_IN      => x"00000000",
-      LVL1_TRG_RELEASE_IN        => '0',
-      LVL1_INT_TRG_NUMBER_OUT    => trg_int_trg_number,
-
-      --Information about trigger handler errors
-      TRG_SPIKE_DETECTED_OUT     => open,
-      TRG_SPURIOUS_TRG_OUT       => open,
-      TRG_TIMEOUT_DETECTED_OUT   => open,
-      TRG_MULTIPLE_TRG_OUT       => open,
-      TRG_MISSING_TMG_TRG_OUT    => open,
-      TRG_LONG_TRG_OUT           => open,
-      --Data Port
-      IPU_NUMBER_OUT             => open,
-      IPU_READOUT_TYPE_OUT       => open,
-      IPU_INFORMATION_OUT        => open,
-      IPU_START_READOUT_OUT      => open,
-      IPU_DATA_IN                => x"00000000",
-      IPU_DATAREADY_IN           => '0',
-      IPU_READOUT_FINISHED_IN    => '1',
-      IPU_READ_OUT               => open,
-      IPU_LENGTH_IN              => x"0000",
-      IPU_ERROR_PATTERN_IN       => x"00000000",
-
-      -- Slow Control Data Port
-      REGIO_COMMON_STAT_REG_IN   => (others => '0'), --REGIO_COMMON_STAT_REG_IN,
-      REGIO_COMMON_CTRL_REG_OUT  => open,
-      REGIO_REGISTERS_IN         => (others => '0'),
-      REGIO_REGISTERS_OUT        => open,
-      COMMON_STAT_REG_STROBE     => open,
-      COMMON_CTRL_REG_STROBE     => open,
-      STAT_REG_STROBE            => open,
-      CTRL_REG_STROBE            => open,
-      
-      REGIO_ADDR_OUT         =>  open, 
-      REGIO_READ_ENABLE_OUT  =>  open, 
-      REGIO_WRITE_ENABLE_OUT =>  open,
-      REGIO_DATA_OUT         =>  open, 
-      REGIO_DATA_IN          =>  (others => '0'), 
-      REGIO_DATAREADY_IN     =>  '0',
-      REGIO_NO_MORE_DATA_IN  =>  '0', 
-      REGIO_WRITE_ACK_IN     =>  '0',
-      REGIO_UNKNOWN_ADDR_IN  =>  '0',
-      REGIO_TIMEOUT_OUT      =>  open,
-
-      REGIO_ONEWIRE_INOUT        => open,
-      REGIO_ONEWIRE_MONITOR_IN   => '0',
-      REGIO_ONEWIRE_MONITOR_OUT  => open,
-      I2C_SCL                    => open,
-      I2C_SDA                    => open,
-      REGIO_VAR_ENDPOINT_ID      => (others => '0'),
-      MY_ADDRESS_OUT             => open,
-
-      GLOBAL_TIME_OUT            => open,
-      LOCAL_TIME_OUT             => open,
-      TIME_SINCE_LAST_TRG_OUT    => open,
-      TIMER_TICKS_OUT            => open,
-      TEMPERATURE_OUT            => open,
-      UNIQUE_ID_OUT              => open,
-
-      STAT_DEBUG_IPU             => open,
-      STAT_DEBUG_1               => open,
-      STAT_DEBUG_2               => open,
-      MED_STAT_OP                => open,
-      CTRL_MPLEX                 => (others => '0'),
-      IOBUF_CTRL_GEN             => (others => '0'),
-      STAT_ONEWIRE               => open,
-      STAT_ADDR_DEBUG            => open,
-      STAT_TRIGGER_OUT           => open,      
-      DEBUG_LVL1_HANDLER_OUT     => open
-      );
-
-
-
-proc_clk : process
-  begin
-    wait for 5 ns;
-    clk <= not clk;
-  end process;
-
-proc_reset : process
-  begin
-    reset <= '1';
-    wait for 50 ns; --30
-    reset <= '0';
-    wait;
-  end process;
-
-eventvec <= std_logic_vector(event);
-
-proc_media_interface : process
-  begin
-    med_stat_op <= (others => '0');
-    event       <= x"FFFF";
-    readoutevent<= x"0000";
-    wait for 159 ns;
-    med_read_in <= '1';
--- first timing trigger
-
-
-
-   -- while 1 = 1 loop
-
-     --send timing trigger
-    --  if timer = 20 or timer = 100 then
-     --   timing_trg        <= '1';
-     --   event             <= event + to_unsigned(1,1);
-     --   wait for 50 ns;
-        timing_trg        <= '0';
-     -- end if;
-
-    --ack in IPU channel
-      --if (med_data_out = x"001A" or med_data_out = x"001B") and med_dataready_out = '1' and med_packet_num_out = c_H0  then
-        med_data_in       <= x"0000";
-        med_packet_num_in <= "100";
-        med_dataready_in  <= '0';
-        wait until falling_edge(clk);
-      
-        wait for 1000 ns;
-        wait until falling_edge(clk);
-        med_data_in       <= x"0031";
-        med_packet_num_in <= "100";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-
-        med_data_in       <= x"5555";
-        med_packet_num_in <= "000";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"ffff";
-        med_packet_num_in <= "001";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"0000";
-        med_packet_num_in <= "010";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-------
-        med_data_in       <= x"000F";
-        med_packet_num_in <= "011";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-
-        med_data_in       <= x"0030";
-        med_packet_num_in <= "100";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"5e1d";
-        med_packet_num_in <= "000";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"0000";
-        med_packet_num_in <= "001";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        ------
-        med_data_in       <= x"0000";
-        med_packet_num_in <= "010";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-
-        med_data_in       <= x"0000";
-        med_packet_num_in <= "011";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"0033";
-        med_packet_num_in <= "100";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"23af";
-        med_packet_num_in <= "000";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"0000";
-        med_packet_num_in <= "001";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"0000";
-        med_packet_num_in <= "010";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_data_in       <= x"000f";
-        med_packet_num_in <= "011";
-        med_dataready_in  <= '1';
-        wait until falling_edge(clk);
-        
-        med_dataready_in  <= '0';
-      --end if;--
-
-      wait until falling_edge(clk);
-    --end loop;
-
---    wait for 100ns;
-    
---    med_data_in       <= x"0000";
---        med_packet_num_in <= "100";
---        med_dataready_in  <= '0';
---        wait until falling_edge(clk);
-      
---        med_data_in       <= x"0031";
---        med_packet_num_in <= "100";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-
---        med_data_in       <= x"5555";
---        med_packet_num_in <= "000";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"ffff";
---        med_packet_num_in <= "001";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"0000";
---        med_packet_num_in <= "010";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
---------
---        med_data_in       <= x"000F";
---        med_packet_num_in <= "011";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-
---        med_data_in       <= x"0030";
---        med_packet_num_in <= "100";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"5e1d";
---        med_packet_num_in <= "000";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"0000";
---        med_packet_num_in <= "001";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
---        ------
---        med_data_in       <= x"0000";
---        med_packet_num_in <= "010";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-
---        med_data_in       <= x"0000";
---        med_packet_num_in <= "011";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"0033";
---        med_packet_num_in <= "100";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"23af";
---        med_packet_num_in <= "000";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"0000";
---        med_packet_num_in <= "001";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"0000";
---        med_packet_num_in <= "010";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_data_in       <= x"000f";
---        med_packet_num_in <= "011";
---        med_dataready_in  <= '1';
---        wait until falling_edge(clk);
-        
---        med_dataready_in  <= '0';
---      --end if;--
-
---      wait until falling_edge(clk);
-    --end loop;
-
-    wait;
-  end process;
-
-
-
---proc_write_data_1 : process
---  begin
---    while 1 = 1 loop
---      wait until rising_edge(trg_valid_timing);
---      wait for 50 ns;
---      wait until falling_edge(clk);
---      fee_data(31 downto 0) <= x"11110001";
---      fee_data_write(0)     <= '1';
---      wait until falling_edge(clk);
---      fee_data(31 downto 0) <= x"11110002";
---      fee_data_write(0)     <= '1';
---      wait until falling_edge(clk);
---      fee_data(31 downto 0) <= x"11110003";
---      fee_data_write(0)     <= '1';
---      wait until falling_edge(clk);
---      fee_data(31 downto 0) <= x"11110004";
---      fee_data_write(0)     <= '1';
---      wait until falling_edge(clk);
---      fee_data_write(0)     <= '0';
---      wait until falling_edge(clk);
---      fee_data_write(0)     <= '0';
---      wait until falling_edge(clk);
---      fee_trg_release(0)    <= '1';
---      wait until falling_edge(clk);
---      fee_trg_release(0)    <= '0';
---      fee_data_finished(0)  <= '1';
---      wait until falling_edge(clk);
---      fee_data_finished(0)  <= '0';
---    end loop;
---  end process;
-
---
--- proc_write_data_2 : process
---   begin
---     while 1 = 1 loop
---       wait until rising_edge(trg_valid_timing);
---       wait for 700 ns;
---       wait until falling_edge(clk);
---       wait for 200 ns;
---       wait until falling_edge(clk);
---       fee_trg_release(1)    <= '1';
---       wait until falling_edge(clk);
---       fee_trg_release(1)    <= '0';
---       fee_data_finished(1)  <= '1';
---       wait until falling_edge(clk);
---       fee_data_finished(1)  <= '0';
---     end loop;
---   end process;
---
--- proc_write_data_3 : process
---   begin
---     while 1 = 1 loop
---       wait until rising_edge(trg_valid_timing);
---       wait for 700 ns;
---       wait until falling_edge(clk);
---       wait for 200 ns;
---       wait until falling_edge(clk);
---       fee_trg_release(2)    <= '1';
---       wait until falling_edge(clk);
---       fee_trg_release(2)    <= '0';
---       fee_data_finished(2)  <= '1';
---       wait until falling_edge(clk);
---       fee_data_finished(2)  <= '0';
---     end loop;
---   end process;
---
--- proc_write_data_4 : process
---   begin
---     while 1 = 1 loop
---       wait until rising_edge(trg_valid_timing);
---       wait for 700 ns;
---       wait until falling_edge(clk);
---       fee_data(127 downto 96) <= x"44440001";
---       fee_data_write(3)     <= '1';
---       wait until falling_edge(clk);
---       fee_data_write(3)     <= '0';
---       wait for 200 ns;
---       wait until falling_edge(clk);
---       fee_trg_release(3)    <= '1';
---       wait until falling_edge(clk);
---       fee_trg_release(3)    <= '0';
---       fee_data_finished(3)  <= '1';
---       wait until falling_edge(clk);
---       fee_data_finished(3)  <= '0';
---     end loop;
---   end process;
---
--- proc_write_data_5 : process
---   begin
---     while 1 = 1 loop
---       wait until rising_edge(trg_valid_timing);
---       wait for 700 ns;
---       wait until falling_edge(clk);
---       fee_data(159 downto 128) <= x"55550001";
---       fee_data_write(4)     <= '1';
---       wait until falling_edge(clk);
---       fee_data_write(4)     <= '0';
---       wait for 200 ns;
---       wait until falling_edge(clk);
---       fee_trg_release(4)    <= '1';
---       wait until falling_edge(clk);
---       fee_trg_release(4)    <= '0';
---       fee_data_finished(4)  <= '1';
---       wait until falling_edge(clk);
---       fee_data_finished(4)  <= '0';
---     end loop;
---   end process;
---
--- proc_write_data_6 : process
---   begin
---     while 1 = 1 loop
---       wait until rising_edge(trg_valid_timing);
---       wait for 700 ns;
---       wait until falling_edge(clk);
---       fee_data(191 downto 160) <= x"66660001";
---       fee_data_write(5)     <= '1';
---       wait until falling_edge(clk);
---       fee_data_write(5)     <= '0';
---       wait for 200 ns;
---       wait until falling_edge(clk);
---       fee_trg_release(5)    <= '1';
---       wait until falling_edge(clk);
---       fee_trg_release(5)    <= '0';
---       fee_data_finished(5)  <= '1';
---       wait until falling_edge(clk);
---       fee_data_finished(5)  <= '0';
---     end loop;
---   end process;
-
-proc_timer : process(CLK)
-  begin
-    if rising_edge(CLK) then
-      timer <= timer + to_unsigned(1,1);
-      if timer = 300 then
-        timer <= to_unsigned(0,32);
-      end if;
-    end if;
-  end process;
-
-
-end architecture;
\ No newline at end of file
diff --git a/endpoint_test/sim/testbench_read_dna_address.vhd b/endpoint_test/sim/testbench_read_dna_address.vhd
deleted file mode 100644
index f551139..0000000
--- a/endpoint_test/sim/testbench_read_dna_address.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-
-entity tb_read_dna_address is
-
-end entity;
-
-
-architecture tb_arch of tb_read_dna_address is
- 
-  signal clk_100, clk_200     : std_logic := '1';
-  signal reset                : std_logic := '0';
-  signal address              : std_logic_vector(95 downto 0);
-  signal dna_valid            : std_logic;
-  signal ds_out               : std_logic_vector(15 downto 0);
-  signal ds_addr              : std_logic_vector( 1 downto 0);
-  signal ds_wr                : std_logic;        
-
-begin
-
- UUT : entity work.read_dna_address
-  port map(
-	  SYSCLK    => clk_100,
-	  SYS_RESET => reset,
-	  SRL_O     => address,
-	  DNA_VALID => dna_valid,
-	  DS_OUT    => ds_out,
-	  DS_ADDR   => ds_addr,
-	  DS_WR     => ds_wr
-   );
---end entity;
-
-
-
-proc_clk100 : process
-  begin
-    wait for 5 ns;
-    clk_100 <= not clk_100;
-  end process;
-  
-proc_clk200 : process
-  begin
-    wait for 2.5 ns;
-    clk_200 <= not clk_200;
-  end process;  
-
---proc_reset : process
---  begin
---    reset <= '1';
---    wait for 30 ns; --30
---    reset <= '0';
---    wait;
---  end process;
-
-
-proc_media_interface : process
-  begin
-    reset <= '0';
-    wait for 10 ns;
-    reset <= '1';
-    wait for 40 ns;
-    reset <= '0';
-   
----- first timing trigger
---   rx_k_in    <= '1';
---   rx_data_in <= x"bc";
---   wait until falling_edge(clk_200);
---   rx_k_in    <= '0';
---   rx_data_in <= x"50";
---   wait until falling_edge(clk_200);
---   rx_k_in    <= '1';
---   rx_data_in <= x"bc";
---   wait until falling_edge(clk_200);
---   rx_k_in    <= '0';
---   rx_data_in <= x"50";
---   wait until falling_edge(clk_200);
-   
---   rx_k_in    <= '0';
---   rx_data_in <= x"fe";
---   wait for 300 ns;
-   
---   rx_k_in    <= '1';
---   rx_data_in <= x"bc";
---   wait until falling_edge(clk_200);
---   rx_k_in    <= '0';
---   rx_data_in <= x"50";
---   wait until falling_edge(clk_200);
---   rx_k_in    <= '1';
---   rx_data_in <= x"bc";
---   wait until falling_edge(clk_200);
---   rx_k_in    <= '0';
---   rx_data_in <= x"50";
---   wait until falling_edge(clk_200);
-end process;
-
-end architecture;
\ No newline at end of file
diff --git a/endpoint_test/sim/testbench_rx_control.vhd b/endpoint_test/sim/testbench_rx_control.vhd
deleted file mode 100644
index fcc5c6b..0000000
--- a/endpoint_test/sim/testbench_rx_control.vhd
+++ /dev/null
@@ -1,123 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-
-entity tb_RX_Control is
-
-end entity;
-
-
-architecture tb_arch of tb_RX_Control is
- 
-  signal clk_100, clk_200        : std_logic := '1';
-  signal reset                   : std_logic := '1';
-  signal rx_data_in              : std_logic_vector(7 downto 0);
-  signal rx_k_in              : std_logic;
-
-begin
-
- UUT : entity work.rx_control
-  generic map(
-   IS_SIMULATION => '1'
-  )
-  port map(
-    CLK_200                       => clk_200,
-    CLK_100                       => clk_100,
-    RESET_IN                      => '0',
-
---clk_sys signals
-    RX_DATA_OUT                   => open,
-    RX_PACKET_NUMBER_OUT          => open,
-    RX_WRITE_OUT                  => open,
-
--- clk_rx signals
-    RX_DATA_IN                    => rx_data_in,
-    RX_K_IN                       => rx_k_in,
-
-    REQUEST_RETRANSMIT_OUT        => open,
-    REQUEST_POSITION_OUT          => open,
-
-    START_RETRANSMIT_OUT          => open,
-    START_POSITION_OUT            => open,
-
-    --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-    RX_DLM                        => open,
-    RX_DLM_WORD                   => open,
-    
---other signals    
-    SEND_LINK_RESET_OUT           => open,
-    MAKE_RESET_OUT                => open,
-    RX_ALLOW_IN                   => '1',
-    RX_RESET_FINISHED             => open,
-    GOT_LINK_READY                => open,
-
-    DEBUG_OUT                     => open,
-    STAT_REG_OUT                  => open
-    );
---end entity;
-
-
-
-proc_clk100 : process
-  begin
-    wait for 5 ns;
-    clk_100 <= not clk_100;
-  end process;
-  
-proc_clk200 : process
-  begin
-    wait for 2.5 ns;
-    clk_200 <= not clk_200;
-  end process;  
-
---proc_reset : process
---  begin
---    reset <= '1';
---    wait for 30 ns; --30
---    reset <= '0';
---    wait;
---  end process;
-
-
-proc_media_interface : process
-  begin
-
-    wait for 20 ns;
--- first timing trigger
-   rx_k_in    <= '1';
-   rx_data_in <= x"bc";
-   wait until falling_edge(clk_200);
-   rx_k_in    <= '0';
-   rx_data_in <= x"50";
-   wait until falling_edge(clk_200);
-   rx_k_in    <= '1';
-   rx_data_in <= x"bc";
-   wait until falling_edge(clk_200);
-   rx_k_in    <= '0';
-   rx_data_in <= x"50";
-   wait until falling_edge(clk_200);
-   
-   rx_k_in    <= '0';
-   rx_data_in <= x"fe";
-   wait for 300 ns;
-   
-   rx_k_in    <= '1';
-   rx_data_in <= x"bc";
-   wait until falling_edge(clk_200);
-   rx_k_in    <= '0';
-   rx_data_in <= x"50";
-   wait until falling_edge(clk_200);
-   rx_k_in    <= '1';
-   rx_data_in <= x"bc";
-   wait until falling_edge(clk_200);
-   rx_k_in    <= '0';
-   rx_data_in <= x"50";
-   wait until falling_edge(clk_200);
-end process;
-
-end architecture;
\ No newline at end of file