From: Jan Michel <j.michel@gsi.de>
Date: Tue, 10 Jul 2018 12:17:06 +0000 (+0200)
Subject: adding testbench for one channel
X-Git-Tag: v2.3~7
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e152ddf336bee411b86a54d20b34683adfec37c1;p=tdc.git

adding testbench for one channel
---

diff --git a/testbench/tb_channel.vhd b/testbench/tb_channel.vhd
new file mode 100644
index 0000000..43daf04
--- /dev/null
+++ b/testbench/tb_channel.vhd
@@ -0,0 +1,94 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.trb_net_std.all;
+use work.tdc_components.all;
+
+entity tb is
+end entity;
+
+
+architecture test of tb is
+
+signal reset_i          : std_logic := '1';
+signal clk_200, clk_100 : std_logic := '1';
+signal hit_i            : std_logic := '0';
+signal win_end_rdo      : std_logic := '0';
+signal read_i           : std_logic := '0';
+
+signal coarse_i         : std_logic_vector(10 downto 0) := (others => '0');
+signal epoch_i          : std_logic_vector(27 downto 0) := (others => '0');
+signal epoch_wr         : std_logic := '0';
+begin
+
+CHAN :  Channel
+
+  generic map (
+    CHANNEL_ID => 1,
+    DEBUG      => 0,
+    SIMULATION => 1,
+    REFERENCE  => 0)
+  port map (
+    RESET_200                 => reset_i,
+    RESET_100                 => reset_i,
+    RESET_COUNTERS            => '0',
+    CLK_200                   => clk_200,
+    CLK_100                   => clk_100,
+--
+    HIT_IN                    => hit_i,
+    HIT_EDGE_IN               => '1',
+    TRG_WIN_END_TDC_IN        => win_end_rdo,
+    TRG_WIN_END_RDO_IN        => win_end_rdo,
+    READ_EN_IN                => read_i,
+    FIFO_DATA_OUT             => open,
+    FIFO_DATA_VALID_OUT       => open,
+    FIFO_ALMOST_FULL_OUT      => open,
+    FIFO_EMPTY_OUT            => open,
+    RING_BUFFER_FULL_THRES_IN => "0000111",
+    COARSE_COUNTER_IN         => coarse_i,
+    EPOCH_COUNTER_IN          => epoch_i,
+--
+    EPOCH_WRITE_EN_IN         => '1',
+    LOST_HIT_NUMBER           => open,
+    HIT_DETECT_NUMBER         => open,
+    ENCODER_START_NUMBER      => open,
+    ENCODER_FINISHED_NUMBER   => open,
+    FIFO_WRITE_NUMBER         => open,
+--
+    Channel_200_DEBUG_OUT     => open,
+    Channel_DEBUG_OUT         => open
+    );
+
+    
+  clk_200 <= not clk_200 after 2.5 ns;
+  clk_100 <= not clk_100 after 5 ns;
+  reset_i <= '0' after 100 ns;    
+    
+  coarse_i <= coarse_i + 1 after 5 ns;
+  
+  process begin
+    wait for 10230 ns;
+    epoch_i <= epoch_i + 1;
+  end process;  
+
+  
+  process begin
+    wait for 103 ns;
+    hit_i <= '1'; wait for 11 ns; hit_i <= '0';
+    wait for 93 ns;
+    hit_i <= '1'; wait for 11 ns; hit_i <= '0';
+  end process;
+    
+  process begin
+    wait for 2030 ns;
+    win_end_rdo <= '1'; wait for 10 ns; win_end_rdo <= '0';
+    wait for 100 ns;
+    read_i <= '1';
+    wait for 300 ns;
+    read_i <= '0';
+  end process;  
+  
+  
+end architecture;