From: hadeshyp <hadeshyp>
Date: Fri, 24 Oct 2008 16:42:11 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~523
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e25ea26bfe98b1c0174235cbafca2a704d385e87;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd
index 12195e1..652df26 100644
--- a/trb_net16_med_ecp_sfp.vhd
+++ b/trb_net16_med_ecp_sfp.vhd
@@ -14,7 +14,7 @@ use work.trb_net_std.all;
 entity trb_net16_med_ecp_sfp is
   port(
     CLK    : in  std_logic;
-    RESET  : in  std_logic;
+    RESET  : in  std_logic;   --must be applied for at least 2 clock cycles
     CLK_EN : in  std_logic;
     --Internal Connection
     MED_DATA_IN       : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
@@ -330,16 +330,17 @@ begin
 --link start-up state machine
 ----------------------
 
- medium_states : process(ff_rxhalfclk)
+ medium_states : process(ff_rxhalfclk, RESET)
     begin
-      if rising_edge(ff_rxhalfclk) then
-        if RESET = '0' then
-          counter <= counter + 1;
-          swap_bytes <= '0';
-          tx_allow <= '0';
-          rx_allow <= '0';
-        end if;
-        swap_bytes <= swap_bytes;
+      if RESET = '1' then
+        swap_bytes <= '0';
+        tx_allow <= '0';
+        rx_allow <= '0';
+        state <= start;
+        MED_ERROR_OUT <= ERROR_NC;
+        counter <= (others => '0');
+      elsif rising_edge(ff_rxhalfclk) then
+        counter <= counter + 1;
         case state is
           when start =>
             if counter(7 downto 0) = x"FF" then