From: hadeshyp Date: Fri, 23 Feb 2007 12:22:19 +0000 (+0000) Subject: In this version Etrax is running and is able to download the data with 10kHz and... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e26f894bb66b92122aec12b02c9148f1414b8839;p=trbv2.git In this version Etrax is running and is able to download the data with 10kHz and 80 words per event (with self triggering) --- diff --git a/etrax_interface.vhd b/etrax_interface.vhd index e21a5ca..d2d91fb 100755 --- a/etrax_interface.vhd +++ b/etrax_interface.vhd @@ -144,7 +144,7 @@ begin en_clk => '1', signal_in => ETRAX_DATA_BUS_C(16), pulse => etrax_trigger_pulse); - ETRAX_TRIGG_PULSER : edge_to_pulse + ETRAX_READY_PULSE : edge_to_pulse port map ( clock => CLK, en_clk => '1', diff --git a/lvl1_and_lvl2_busy.vhd b/lvl1_and_lvl2_busy.vhd index ac5e633..6a5a47b 100755 --- a/lvl1_and_lvl2_busy.vhd +++ b/lvl1_and_lvl2_busy.vhd @@ -19,7 +19,8 @@ entity lvl1_and_lvl2_busy is LVL2_TRIGG : in std_logic; TRIGGER_CODE : in std_logic_vector(3 downto 0); TDC_READOUT_COMPLETED : in std_logic; - TRIGGER_WITHOUT_HADES : in std_logic + TRIGGER_WITHOUT_HADES : in std_logic; + BUSY_REGISTER_00 : out std_logic_vector(31 downto 0) ); end lvl1_and_lvl2_busy; architecture lvl1_and_lvl2_busy of lvl1_and_lvl2_busy is @@ -93,6 +94,7 @@ begin DOWN => tdc_lvl2_busy_pulse,--lvl2_count_pulse, CLK => CLK, CLR => RESET); + BUSY_REGISTER_00(15 downto 0) <= count_lvl1_lvl2_diff; ----------------------------------------------------------------------------- -- LEVEL 1 BUSY LOGIC ----------------------------------------------------------------------------- diff --git a/tdc_interface.vhd b/tdc_interface.vhd index 494778d..9335588 100755 --- a/tdc_interface.vhd +++ b/tdc_interface.vhd @@ -62,7 +62,8 @@ entity tdc_interface is TDC_LVL2_BUSY : out std_logic; TDC_REGISTER_00 : out std_logic_vector(31 downto 0); BUNCH_RESET : out std_logic; - EVENT_RESET : out std_logic + EVENT_RESET : out std_logic; + READ_ADRESS_END_UP : in std_logic ); end tdc_interface; architecture tdc_interface of tdc_interface is @@ -414,7 +415,10 @@ begin how_many_words_in_event <= (others => '0'); elsif lvl2_trigger_pulse = '1' then how_many_words_in_event <= x"1" & doutb_i(15 downto 0); - elsif lvl2_trigger_pulse = '0' and how_many_words_in_event > x"0ffff" then + elsif lvl2_trigger_pulse = '0' and how_many_words_in_event > x"0ffff" and ETRAX_IS_READY_TO_READ = '1'then + --this should be without and ETRAX_IS_READY_TO_READ - this is simple + --version of readout - in next whole event has to be written without + --waiting for etrax - ifthere is no LVL2 busy from etrax how_many_words_in_event <= how_many_words_in_event - 1; end if; end if; @@ -440,7 +444,7 @@ begin end process MAKE_LVL2_PULSE; SYNCH_DATA_VALID: process (CLK, RESET) begin - if falling_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?) + if rising_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?) if RESET = '1' then TDC_DATA_VALID <= '0'; else @@ -454,7 +458,7 @@ begin if rising_edge(CLK) then if RESET = '1' then read_address <= (others => '0'); - elsif read_data_address_up = '1' then + elsif (read_data_address_up = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1' then read_address <= read_address + 1; else read_address <= read_address; @@ -476,12 +480,12 @@ begin end if; end if; end process WORD_ADD_TO_MEMORY; - WORD_SEND_FROM_MEMORY: process (CLK, RESET) + WORD_SEND_FROM_MEMORY: process (CLK, RESET,ETRAX_IS_READY_TO_READ) begin if rising_edge(CLK) then if RESET = '1' then word_ram_counter_down <= (others => '0'); - elsif read_data_address_up = '1' then + elsif (read_data_address_up = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1' then word_ram_counter_down <= word_ram_counter_down + 1; end if; end if; diff --git a/trb_v2a_fpga.vhd b/trb_v2a_fpga.vhd index 3cbd9a3..f50747f 100644 --- a/trb_v2a_fpga.vhd +++ b/trb_v2a_fpga.vhd @@ -285,7 +285,8 @@ architecture trb_v2a_fpga of trb_v2a_fpga is TDC_LVL2_BUSY : out std_logic; TDC_REGISTER_00 : out std_logic_vector(31 downto 0); BUNCH_RESET : out std_logic; - EVENT_RESET : out std_logic); + EVENT_RESET : out std_logic; + READ_ADRESS_END_UP : in std_logic); end component; component lvl1_and_lvl2_busy port ( @@ -301,7 +302,8 @@ architecture trb_v2a_fpga of trb_v2a_fpga is LVL2_TRIGG : in std_logic; TRIGGER_CODE : in std_logic_vector(3 downto 0); TDC_READOUT_COMPLETED : in std_logic; - TRIGGER_WITHOUT_HADES : in std_logic + TRIGGER_WITHOUT_HADES : in std_logic; + BUSY_REGISTER_00 : out std_logic_vector(31 downto 0) ); end component; component trigger_logic @@ -324,7 +326,8 @@ architecture trb_v2a_fpga of trb_v2a_fpga is LVL2_BUSY : in std_logic; TRB_ACK_LVL1 : out std_logic; TRB_ACK_LVL2 : out std_logic; - TRIGGER_TO_TDC : out std_logic + TRIGGER_TO_TDC : out std_logic; + TRIGGER_REGISTER_00 : out std_logic_vector(31 downto 0) ); end component; component etrax_interface @@ -523,6 +526,9 @@ architecture trb_v2a_fpga of trb_v2a_fpga is signal token_out_i : std_logic; signal test_en_tdc_clk : std_logic; signal test_en : std_logic; + signal busy_register_00_i : std_logic_vector(31 downto 0); + signal trigger_register_00_i : std_logic_vector(31 downto 0); + begin ----------------------------------------------------------------------------- @@ -670,7 +676,8 @@ begin TDC_LVL2_BUSY => tdc_lvl2_busy_i, TDC_REGISTER_00 => tdc_register_00_i, BUNCH_RESET => bunch_reset_i, - EVENT_RESET => event_reset_i); + EVENT_RESET => event_reset_i, + READ_ADRESS_END_UP => trb_ack_lvl2_i); -- ------------------------------------------------------------------------------- -- -- sim -- ------------------------------------------------------------------------------- @@ -692,12 +699,13 @@ begin TDC_LVL1_BUSY => tdc_lvl1_busy_i, TDC_LVL2_BUSY => tdc_lvl2_busy_i, ETRAX_BUS_BUSY => etrax_bus_busy_i, - ETRAX_BUSY => FS_PC(17), + ETRAX_BUSY => FS_PC(16), LVL1_TRIGG => lvl1_trigger_i, LVL2_TRIGG => lvl2_trigger_i(0), TRIGGER_CODE => lvl1_trigger_code_i, TDC_READOUT_COMPLETED => tdc_readout_completed_i, - TRIGGER_WITHOUT_HADES => trigg_without_hades_i + TRIGGER_WITHOUT_HADES => trigg_without_hades_i, + BUSY_REGISTER_00 => busy_register_00_i ); -- trigg_without_hades_i <= TDC_CLK; SYNCH_EXT_TRIGG: process (CLK, external_reset_i) @@ -706,7 +714,7 @@ begin if external_reset_i = '1' then -- asynchronous reset (active low) trigg_without_hades_i <= '0'; else - trigg_without_hades_i <= TDC_CLK and tdc_control_register_e(0) and (not lvl1_busy_i); + trigg_without_hades_i <= TDC_CLK and tdc_control_register_e(0) and (not lvl1_busy_i) and (not tdc_lvl2_busy_i) and (not busy_register_00_i(0)) and(not etrax_bus_busy_i); end if; end if; end process SYNCH_EXT_TRIGG; @@ -731,7 +739,8 @@ begin LVL2_BUSY => lvl2_busy_i, TRB_ACK_LVL1 => trb_ack_lvl1_i, TRB_ACK_LVL2 => trb_ack_lvl2_i, - TRIGGER_TO_TDC => trigger_to_tdc_i + TRIGGER_TO_TDC => trigger_to_tdc_i, + TRIGGER_REGISTER_00 => trigger_register_00_i ); a_trigg <= trigger_to_tdc_i; @@ -767,8 +776,8 @@ begin FPGA_REGISTER_01 => tlk_register_00_i, FPGA_REGISTER_02 => tlk_register_01_i, FPGA_REGISTER_03 => tdc_register_00_i,--x"abbaab02", - FPGA_REGISTER_04 => x"abbaab03", - FPGA_REGISTER_05 => x"abbaab04", + FPGA_REGISTER_04 => busy_register_00_i, + FPGA_REGISTER_05 => trigger_register_00_i, FPGA_REGISTER_06 => x"abbaab05", FPGA_REGISTER_07 => fpga_register_07_i, FPGA_REGISTER_08 => x"abbaab07", @@ -880,7 +889,7 @@ begin -- ADO_TTL <= "000" & x"0000000" & DSP_WRL_i & DSP_RD_i & "0" & -- dspdat_in_i(4 downto 0) & dspdat_out_i(4 downto 0) -- & CLK & fpga_register_07_i(2 downto 1); - ADO_TTL <= "000" & x"0000000" & tdc_register_00_i(20) & clk & bunch_reset_i & TOKEN_IN & trigger_to_tdc_i & token_out_i & lvl1_tdc_trigg_i & A_DATA_READY & B_DATA_READY & C_DATA_READY & D_DATA_READY & etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i; + ADO_TTL <= "000" & x"0000000" & trigg_without_hades_i & trb_ack_lvl1_i & busy_register_00_i(0) & tdc_data_valid_i & etrax_bus_busy_i & tdc_readout_completed_i&TOKEN_IN & A_DATA_READY & B_DATA_READY & C_DATA_READY & D_DATA_READY & etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i; -- trb_status_register_00 <= etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i; -- clk & tdc_clk & event_reset_i no & bunch_reset_i no & trigger_to_tdc_i yes & TOKEN_ -- OUT '1' & lvl1_tdc_trigg_i yes & A_DATA_READY no & B_DATA_READY no & C_DATA_ diff --git a/trb_v2a_fpga_tb.vhd b/trb_v2a_fpga_tb.vhd index 97a3d40..9e42565 100644 --- a/trb_v2a_fpga_tb.vhd +++ b/trb_v2a_fpga_tb.vhd @@ -393,6 +393,14 @@ BEGIN wait for 20 ns; FS_PC(16) <= '0'; wait on VIRT_CLK until FS_PB(16)= '1'; + loop + wait on VIRT_CLK until FS_PB(17) = '1'; + FS_PC(17) <= '1'; + wait for 50 ns; + FS_PC(17) <= '0'; + wait for 50 ns; + end loop; + wait; -- will wait forever end process; @@ -516,4 +524,5 @@ BEGIN -- C_TEMP <= '1'; -- wait for 30 ns; -- end process; + END; diff --git a/trigger_logic.vhd b/trigger_logic.vhd index bda0db2..d13165d 100755 --- a/trigger_logic.vhd +++ b/trigger_logic.vhd @@ -34,7 +34,8 @@ entity trigger_logic is LVL2_BUSY : in std_logic; TRB_ACK_LVL1 : out std_logic; TRB_ACK_LVL2 : out std_logic; - TRIGGER_TO_TDC : out std_logic + TRIGGER_TO_TDC : out std_logic; + TRIGGER_REGISTER_00 : out std_logic_vector(31 downto 0) ); end trigger_logic; @@ -80,9 +81,11 @@ architecture trigger_logic of trigger_logic is signal lvl1_trigger_pulse_delay : std_logic; signal lvl1_tdc_trigg_i : std_logic; signal not_tdc_clk : std_logic; + signal trigger_register_00_i : std_logic_vector(31 downto 0); begin + TRIGGER_REGISTER_00 <= trigger_register_00_i; ----------------------------------------------------------------------------- -- LVL1 trigger logic ----------------------------------------------------------------------------- @@ -121,6 +124,7 @@ begin begin -- process TO_DELAY_TRIGG case (delay_fsm_currentstate) is when IDLE => + trigger_register_00_i(1 downto 0) <= "00"; lvl1_trigger_pulse_delay <= '0'; delay_clr <= '1'; delay_up <= '0'; @@ -130,6 +134,7 @@ begin delay_fsm_nextstate <= IDLE; end if; when DELAY_1 => + trigger_register_00_i(1 downto 0) <= "01"; lvl1_trigger_pulse_delay <= '0'; delay_clr <= '0'; delay_up <= '1'; @@ -139,11 +144,13 @@ begin delay_fsm_nextstate <= DELAY_1; end if; when DELAY_2 => + trigger_register_00_i(1 downto 0) <= "10"; lvl1_trigger_pulse_delay <= '1'; delay_clr <= '1'; delay_up <= '0'; delay_fsm_nextstate <= IDLE; when others => + trigger_register_00_i(1 downto 0) <= "11"; lvl1_trigger_pulse_delay <= '0'; delay_clr <= '1'; delay_up <= '0'; @@ -182,6 +189,7 @@ begin begin case (LVL1_START_fsm_currentstate) is when IDLE => + trigger_register_00_i(4 downto 2) <= "000"; lvl1_tdc_trigg_i <= '0'; if (lvl1_trigger_pulse_start = '1' and LVL1_TRIGGER_CODE /= x"d") or (TRIGG_WITHOUT_HADES ='1' and TDC_CONTROL_REGISTER(0) = '1') then @@ -190,18 +198,23 @@ begin LVL1_START_fsm_nextstate <= IDLE; end if; when SEND_LVL1_TRIGG_1 => --4 clock of 100MHz - to generate token + trigger_register_00_i(4 downto 2) <= "001"; lvl1_tdc_trigg_i <= '1'; LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_2; when SEND_LVL1_TRIGG_2 => + trigger_register_00_i(4 downto 2) <= "010"; lvl1_tdc_trigg_i <= '1'; LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_3; when SEND_LVL1_TRIGG_3 => + trigger_register_00_i(4 downto 2) <= "011"; lvl1_tdc_trigg_i <= '1'; LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_4; when SEND_LVL1_TRIGG_4 => + trigger_register_00_i(4 downto 2) <= "100"; lvl1_tdc_trigg_i <= '0'; LVL1_START_fsm_nextstate <= WAIT_FOR_ACK; when WAIT_FOR_ACK => + trigger_register_00_i(4 downto 2) <= "101"; lvl1_tdc_trigg_i <= '0'; if ACK_LVL1_STATE = ACK_LVL1_pulse_1 then LVL1_START_fsm_nextstate <= IDLE; @@ -209,6 +222,7 @@ begin LVL1_START_fsm_nextstate <= WAIT_FOR_ACK; end if; when others => + trigger_register_00_i(4 downto 2) <= "111"; LVL1_START_fsm_nextstate <= IDLE; lvl1_tdc_trigg_i <= '0'; end case; @@ -222,6 +236,7 @@ begin else case (ACK_LVL1_STATE) is when IDLE => + trigger_register_00_i(6 downto 5) <= "00"; TRB_ACK_LVL1 <= '0'; if LVL1_BUSY = '1' then ACK_LVL1_STATE <= ACK_LVL1_CHECK_COMPLETION; @@ -231,6 +246,7 @@ begin ACK_LVL1_STATE <= IDLE; end if; when ACK_LVL1_CHECK_COMPLETION => + trigger_register_00_i(6 downto 5) <= "01"; TRB_ACK_LVL1 <= '0'; if LVL1_BUSY = '1'then ACK_LVL1_STATE <= ACK_LVL1_CHECK_COMPLETION; @@ -238,9 +254,11 @@ begin ACK_LVL1_STATE <= ACK_LVL1_PULSE_1; end if; when ACK_LVL1_PULSE_1 => + trigger_register_00_i(6 downto 5) <= "10"; TRB_ACK_LVL1 <= '1'; ACK_LVL1_STATE <= IDLE; when others => + trigger_register_00_i(6 downto 5) <= "11"; ACK_LVL1_STATE <= IDLE; end case; end if; @@ -277,6 +295,7 @@ begin begin case (LVL2_START_fsm_currentstate) is when IDLE => + trigger_register_00_i(9 downto 7) <= "000"; LVL2_TDC_TRIGG <= "00"; if (lvl2_trigger_pulse='1') or (ACK_LVL1_STATE = ACK_LVL1_PULSE_1 and TDC_CONTROL_REGISTER(0) = '1') then LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_1; @@ -284,12 +303,15 @@ begin LVL2_START_fsm_nextstate <= IDLE; end if; when SEND_LVL2_TRIGG_1 => + trigger_register_00_i(9 downto 7) <= "001"; LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1'; LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_2; when SEND_LVL2_TRIGG_2 => + trigger_register_00_i(9 downto 7) <= "010"; LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1'; LVL2_START_fsm_nextstate <= WAIT_FOR_ACK; when WAIT_FOR_ACK => + trigger_register_00_i(9 downto 7) <= "011"; LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1'; if ACK_LVL2_STATE = ACK_LVL2_PULSE_1 then LVL2_START_fsm_nextstate <= IDLE; @@ -297,6 +319,7 @@ begin LVL2_START_fsm_nextstate <= WAIT_FOR_ACK; end if; when others => + trigger_register_00_i(9 downto 7) <= "111"; LVL2_START_fsm_nextstate <= IDLE; LVL2_TDC_TRIGG <= "00"; end case; @@ -309,20 +332,24 @@ begin else case (ACK_LVL2_STATE) is when IDLE => + trigger_register_00_i(11 downto 10) <= "00"; if LVL2_BUSY = '1' and LVL2_START_fsm_currentstate /= IDLE then ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION; else ACK_LVL2_STATE <= IDLE; end if; when ACK_LVL2_CHECK_COMPLETION => + trigger_register_00_i(11 downto 10) <= "01"; if LVL2_BUSY = '1' then ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION; else ACK_LVL2_STATE <= ACK_LVL2_PULSE_1; end if; when ACK_LVL2_PULSE_1 => + trigger_register_00_i(11 downto 10) <= "10"; ACK_LVL2_STATE <= IDLE; when others => + trigger_register_00_i(11 downto 10) <= "11"; ACK_LVL2_STATE <= IDLE; end case; end if;