From: hadeshyp <hadeshyp>
Date: Thu, 24 Jun 2010 15:28:17 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~264
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e32982ea717ed70b86168014bd334069f85f7514;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd
index b810473..b4683db 100644
--- a/trb_net_sbuf5.vhd
+++ b/trb_net_sbuf5.vhd
@@ -89,24 +89,30 @@ signal fifo_almostfull       : std_logic;
 signal debug_x               : std_logic_vector(7 downto 0);
 
 attribute syn_preserve : boolean;
+attribute syn_noprune  : boolean;
 attribute syn_keep     : boolean;
+attribute syn_preserve of fifo_wcnt       : signal is true;
+attribute syn_keep of fifo_wcnt           : signal is true;
+attribute syn_noprune of fifo_wcnt        : signal is true;
+attribute syn_preserve of bsm             : signal is true;
+attribute syn_keep of bsm                 : signal is true;
+attribute syn_noprune of bsm              : signal is true;
+
+
 attribute syn_preserve of syn_data        : signal is true;
 attribute syn_keep of syn_data            : signal is true;
 attribute syn_preserve of syn_dataready   : signal is true;
 attribute syn_keep of syn_dataready       : signal is true;
 
-attribute syn_preserve of fifo_wcnt       : signal is true; 
-attribute syn_keep of fifo_wcnt           : signal is true; 
-attribute syn_preserve of bsm             : signal is true; 
-attribute syn_keep of bsm                 : signal is true; 
-
 attribute syn_hier : string;
 attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm";
 
+
 --attribute syn_noprune : boolean;
 --attribute syn_noprune of THE_DBG_REG : label is true;
 --signal my_debug                 : std_logic_vector(26 downto 0);
 
+
 begin
 
 
@@ -242,7 +248,8 @@ begin
 						else
 							NEXT_STATE      <= RD4;
 						end if;
-		when RD5    =>  syn_dataready_x <= '1'; 
+		when RD5    => 
+						syn_dataready_x <= '1';
 						if   ( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then
 							NEXT_STATE      <= WR5;
 							fifo_rd_en_x    <= '1';
@@ -251,15 +258,20 @@ begin
 						else
 							NEXT_STATE      <= RD5;
 						end if;
-		when WR5    =>  if( (SYN_READ_IN = '1') and (p_really_x = '1') ) then
+		when WR5    =>
+            if SYN_READ_IN = '0' and syn_dataready = '1' then
+							NEXT_STATE      <= WR5;
+              syn_dataready_x <= '1';
+            elsif ( (SYN_READ_IN = '1') and (p_really_x = '1')  ) then
 							NEXT_STATE      <= RD2;
 							fifo_rd_en_x    <= '1';
-							--syn_dataready_x <= '1';
-							syn_dataready_x <= COMB_DATAREADY_IN;
+              syn_dataready_x <= '1';
 						else
 							NEXT_STATE      <= WR5;
+              syn_dataready_x <= p_really_x;
 						end if;
-		when WT5    =>  if( SYN_READ_IN = '1' ) then
+		when WT5    =>  
+						if( SYN_READ_IN = '1' ) then
 							NEXT_STATE <= IDLE;
 						else
 							NEXT_STATE <= WT5;
@@ -299,7 +311,7 @@ end process THE_SYNC_PROC;
 -- DEBUG
 ---------------------------------------------------------------------
 debug_x(7 downto 4)  <= x"0";
-debug_x(3)           <= '0';
+debug_x(3)           <= COMB_DATAREADY_IN;
 debug_x(2)           <= fifo_rd_en_x;
 debug_x(1)           <= p_avail_x;
 debug_x(0)           <= p_wait_x;