From: Peter Lemmens Date: Thu, 22 May 2014 13:48:07 +0000 (+0200) Subject: Data clock added to code/med_ecp3_sfp_4_sync_down.vhd; this is synchronous with the... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e41c51bef2fd96ad8ce0f13f70f40bdc4ac2814b;p=soda.git Data clock added to code/med_ecp3_sfp_4_sync_down.vhd; this is synchronous with the data. Still no beef ! P2p works great but no connection when a hub is in between. The connection between source and hub is OK; there is no lock between hub and client; clock or reset problems!! --- diff --git a/code/ip/serdes_4_sync_downstream.ipx b/code/ip/serdes_4_sync_downstream.ipx index 752b576..9c4b2c1 100644 --- a/code/ip/serdes_4_sync_downstream.ipx +++ b/code/ip/serdes_4_sync_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_4_sync_downstream.lpc b/code/ip/serdes_4_sync_downstream.lpc index 7c4a1e5..62b6d65 100644 --- a/code/ip/serdes_4_sync_downstream.lpc +++ b/code/ip/serdes_4_sync_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_4_sync_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=02/25/2014 -Time=13:41:30 +Date=05/13/2014 +Time=16:08:01 [Parameters] Verilog=0 @@ -91,10 +91,10 @@ _rx_data_width0=8 _rx_data_width1=8 _rx_data_width2=8 _rx_data_width3=8 -_rx_fifo0=DISABLED -_rx_fifo1=DISABLED -_rx_fifo2=DISABLED -_rx_fifo3=DISABLED +_rx_fifo0=ENABLED +_rx_fifo1=ENABLED +_rx_fifo2=ENABLED +_rx_fifo3=ENABLED _rx_ficlk_rate0=200 _rx_ficlk_rate1=200 _rx_ficlk_rate2=200 @@ -190,10 +190,10 @@ _cc_match_mode0=1 _cc_match_mode1=1 _cc_match_mode2=1 _cc_match_mode3=1 -_k00=01 -_k01=01 -_k02=01 -_k03=01 +_k00=00 +_k01=00 +_k02=00 +_k03=00 _k10=00 _k11=00 _k12=00 diff --git a/code/ip/serdes_4_sync_downstream.txt b/code/ip/serdes_4_sync_downstream.txt index bf7c29c..8e076a7 100644 --- a/code/ip/serdes_4_sync_downstream.txt +++ b/code/ip/serdes_4_sync_downstream.txt @@ -44,10 +44,10 @@ CH0_TX_FIFO "DISABLED" CH1_TX_FIFO "DISABLED" CH2_TX_FIFO "DISABLED" CH3_TX_FIFO "DISABLED" -CH0_RX_FIFO "DISABLED" -CH1_RX_FIFO "DISABLED" -CH2_RX_FIFO "DISABLED" -CH3_RX_FIFO "DISABLED" +CH0_RX_FIFO "ENABLED" +CH1_RX_FIFO "ENABLED" +CH2_RX_FIFO "ENABLED" +CH3_RX_FIFO "ENABLED" CH0_TDRV "0" CH1_TDRV "0" CH2_TDRV "0" @@ -131,10 +131,10 @@ CH0_CTC "DISABLED" CH1_CTC "DISABLED" CH2_CTC "DISABLED" CH3_CTC "DISABLED" -CH0_CC_MATCH4 "0100011100" -CH1_CC_MATCH4 "0100011100" -CH2_CC_MATCH4 "0100011100" -CH3_CC_MATCH4 "0100011100" +CH0_CC_MATCH4 "0000011100" +CH1_CC_MATCH4 "0000011100" +CH2_CC_MATCH4 "0000011100" +CH3_CC_MATCH4 "0000011100" CH0_CC_MATCH_MODE "1" CH1_CC_MATCH_MODE "1" CH2_CC_MATCH_MODE "1" diff --git a/code/ip/serdes_4_sync_downstream.vhd b/code/ip/serdes_4_sync_downstream.vhd index d57d5b1..f772fcd 100644 --- a/code/ip/serdes_4_sync_downstream.vhd +++ b/code/ip/serdes_4_sync_downstream.vhd @@ -1538,6 +1538,7 @@ entity serdes_4_sync_downstream is hdinp_ch0, hdinn_ch0 : in std_logic; hdoutp_ch0, hdoutn_ch0 : out std_logic; sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; txiclk_ch0 : in std_logic; rx_full_clk_ch0 : out std_logic; rx_half_clk_ch0 : out std_logic; @@ -1568,6 +1569,7 @@ entity serdes_4_sync_downstream is hdinp_ch1, hdinn_ch1 : in std_logic; hdoutp_ch1, hdoutn_ch1 : out std_logic; sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; txiclk_ch1 : in std_logic; rx_full_clk_ch1 : out std_logic; rx_half_clk_ch1 : out std_logic; @@ -1598,6 +1600,7 @@ entity serdes_4_sync_downstream is hdinp_ch2, hdinn_ch2 : in std_logic; hdoutp_ch2, hdoutn_ch2 : out std_logic; sci_sel_ch2 : in std_logic; + rxiclk_ch2 : in std_logic; txiclk_ch2 : in std_logic; rx_full_clk_ch2 : out std_logic; rx_half_clk_ch2 : out std_logic; @@ -1628,6 +1631,7 @@ entity serdes_4_sync_downstream is hdinp_ch3, hdinn_ch3 : in std_logic; hdoutp_ch3, hdoutn_ch3 : out std_logic; sci_sel_ch3 : in std_logic; + rxiclk_ch3 : in std_logic; txiclk_ch3 : in std_logic; rx_full_clk_ch3 : out std_logic; rx_half_clk_ch3 : out std_logic; @@ -2310,7 +2314,7 @@ port map ( PCIE_PHYSTATUS_0 => open, SCISELCH0 => sci_sel_ch0, SCIENCH0 => fpsc_vhi, - FF_RXI_CLK_0 => fpsc_vlo, + FF_RXI_CLK_0 => rxiclk_ch0, FF_TXI_CLK_0 => txiclk_ch0, FF_EBRD_CLK_0 => fpsc_vlo, FF_RX_F_CLK_0 => rx_full_clk_ch0, @@ -2416,7 +2420,7 @@ port map ( PCIE_PHYSTATUS_1 => open, SCISELCH1 => sci_sel_ch1, SCIENCH1 => fpsc_vhi, - FF_RXI_CLK_1 => fpsc_vlo, + FF_RXI_CLK_1 => rxiclk_ch1, FF_TXI_CLK_1 => txiclk_ch1, FF_EBRD_CLK_1 => fpsc_vlo, FF_RX_F_CLK_1 => rx_full_clk_ch1, @@ -2522,7 +2526,7 @@ port map ( PCIE_PHYSTATUS_2 => open, SCISELCH2 => sci_sel_ch2, SCIENCH2 => fpsc_vhi, - FF_RXI_CLK_2 => fpsc_vlo, + FF_RXI_CLK_2 => rxiclk_ch2, FF_TXI_CLK_2 => txiclk_ch2, FF_EBRD_CLK_2 => fpsc_vlo, FF_RX_F_CLK_2 => rx_full_clk_ch2, @@ -2628,7 +2632,7 @@ port map ( PCIE_PHYSTATUS_3 => open, SCISELCH3 => sci_sel_ch3, SCIENCH3 => fpsc_vhi, - FF_RXI_CLK_3 => fpsc_vlo, + FF_RXI_CLK_3 => rxiclk_ch3, FF_TXI_CLK_3 => txiclk_ch3, FF_EBRD_CLK_3 => fpsc_vlo, FF_RX_F_CLK_3 => rx_full_clk_ch3, diff --git a/code/ip/serdes_4_sync_hub_downstream.ipx b/code/ip/serdes_4_sync_hub_downstream.ipx index 249341e..bd45581 100644 --- a/code/ip/serdes_4_sync_hub_downstream.ipx +++ b/code/ip/serdes_4_sync_hub_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_4_sync_hub_downstream.lpc b/code/ip/serdes_4_sync_hub_downstream.lpc index b087641..6e2c674 100644 --- a/code/ip/serdes_4_sync_hub_downstream.lpc +++ b/code/ip/serdes_4_sync_hub_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_4_sync_hub_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=05/06/2014 -Time=15:48:34 +Date=05/08/2014 +Time=13:39:51 [Parameters] Verilog=0 diff --git a/code/ip/serdes_4_sync_hub_downstream.txt b/code/ip/serdes_4_sync_hub_downstream.txt deleted file mode 100644 index e4dbb5d..0000000 --- a/code/ip/serdes_4_sync_hub_downstream.txt +++ /dev/null @@ -1,163 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "G8B10B" -CH1_PROTOCOL "G8B10B" -CH2_PROTOCOL "G8B10B" -CH3_PROTOCOL "G8B10B" -CH0_MODE "RXTX" -CH1_MODE "RXTX" -CH2_MODE "RXTX" -CH3_MODE "RXTX" -CH0_CDR_SRC "REFCLK_CORE" -CH1_CDR_SRC "REFCLK_CORE" -CH2_CDR_SRC "REFCLK_CORE" -CH3_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH0_RX_DATARATE_RANGE "MEDHIGH" -CH1_RX_DATARATE_RANGE "MEDHIGH" -CH2_RX_DATARATE_RANGE "MEDHIGH" -CH3_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200 -CH0_RX_DATA_RATE "FULL" -CH1_RX_DATA_RATE "FULL" -CH2_RX_DATA_RATE "FULL" -CH3_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH1_TX_DATA_RATE "FULL" -CH2_TX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH1_TX_DATA_WIDTH "8" -CH2_TX_DATA_WIDTH "8" -CH3_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH1_RX_DATA_WIDTH "8" -CH2_RX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" -CH0_TX_FIFO "DISABLED" -CH1_TX_FIFO "DISABLED" -CH2_TX_FIFO "DISABLED" -CH3_TX_FIFO "DISABLED" -CH0_RX_FIFO "DISABLED" -CH1_RX_FIFO "DISABLED" -CH2_RX_FIFO "DISABLED" -CH3_RX_FIFO "DISABLED" -CH0_TDRV "0" -CH1_TDRV "0" -CH2_TDRV "0" -CH3_TDRV "0" -#CH0_TX_FICLK_RATE 200 -#CH1_TX_FICLK_RATE 200 -#CH2_TX_FICLK_RATE 200 -#CH3_TX_FICLK_RATE 200 -#CH0_RXREFCLK_RATE "200" -#CH1_RXREFCLK_RATE "200" -#CH2_RXREFCLK_RATE "200" -#CH3_RXREFCLK_RATE "200" -#CH0_RX_FICLK_RATE 200 -#CH1_RX_FICLK_RATE 200 -#CH2_RX_FICLK_RATE 200 -#CH3_RX_FICLK_RATE 200 -CH0_TX_PRE "DISABLED" -CH1_TX_PRE "DISABLED" -CH2_TX_PRE "DISABLED" -CH3_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH1_RTERM_TX "50" -CH2_RTERM_TX "50" -CH3_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH1_RX_EQ "DISABLED" -CH2_RX_EQ "DISABLED" -CH3_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH1_RTERM_RX "50" -CH2_RTERM_RX "50" -CH3_RTERM_RX "50" -CH0_RX_DCC "DC" -CH1_RX_DCC "DC" -CH2_RX_DCC "DC" -CH3_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "2" -CH1_LOS_THRESHOLD_LO "2" -CH2_LOS_THRESHOLD_LO "2" -CH3_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH1_TX_SB "DISABLED" -CH2_TX_SB "DISABLED" -CH3_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH1_RX_SB "DISABLED" -CH2_RX_SB "DISABLED" -CH3_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH1_TX_8B10B "ENABLED" -CH2_TX_8B10B "ENABLED" -CH3_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH1_RX_8B10B "ENABLED" -CH2_RX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH1_COMMA_A "1100000101" -CH2_COMMA_A "1100000101" -CH3_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH1_COMMA_B "0011111010" -CH2_COMMA_B "0011111010" -CH3_COMMA_B "0011111010" -CH0_COMMA_M "1111111100" -CH1_COMMA_M "1111111100" -CH2_COMMA_M "1111111100" -CH3_COMMA_M "1111111100" -CH0_RXWA "ENABLED" -CH1_RXWA "ENABLED" -CH2_RXWA "ENABLED" -CH3_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH1_ILSM "ENABLED" -CH2_ILSM "ENABLED" -CH3_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH1_CTC "DISABLED" -CH2_CTC "DISABLED" -CH3_CTC "DISABLED" -CH0_CC_MATCH4 "0000011100" -CH1_CC_MATCH4 "0000011100" -CH2_CC_MATCH4 "0000011100" -CH3_CC_MATCH4 "0000011100" -CH0_CC_MATCH_MODE "1" -CH1_CC_MATCH_MODE "1" -CH2_CC_MATCH_MODE "1" -CH3_CC_MATCH_MODE "1" -CH0_CC_MIN_IPG "3" -CH1_CC_MIN_IPG "3" -CH2_CC_MIN_IPG "3" -CH3_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH1_SSLB "DISABLED" -CH2_SSLB "DISABLED" -CH3_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH1_SPLBPORTS "DISABLED" -CH2_SPLBPORTS "DISABLED" -CH3_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -CH1_PCSLBPORTS "DISABLED" -CH2_PCSLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "ENABLED" - - diff --git a/code/ip/serdes_sync_client_upstream.txt b/code/ip/serdes_sync_client_upstream.txt deleted file mode 100644 index 54e4aa3..0000000 --- a/code/ip/serdes_sync_client_upstream.txt +++ /dev/null @@ -1,58 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "G8B10B" -CH0_MODE "RXTX" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "DISABLED" -CH0_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH0_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200.0 -CH0_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH0_TX_FIFO "DISABLED" -CH0_RX_FIFO "DISABLED" -CH0_TDRV "0" -#CH0_TX_FICLK_RATE 200.0 -#CH0_RXREFCLK_RATE "200.0" -#CH0_RX_FICLK_RATE 200.0 -CH0_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH0_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH0_COMMA_M "1111111100" -CH0_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH0_CC_MATCH4 "0000000000" -CH0_CC_MATCH_MODE "1" -CH0_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -INT_ALL "ENABLED" -QD_REFCK2CORE "DISABLED" - - diff --git a/code/ip/serdes_sync_hub_upstream.txt b/code/ip/serdes_sync_hub_upstream.txt deleted file mode 100644 index a057cb3..0000000 --- a/code/ip/serdes_sync_hub_upstream.txt +++ /dev/null @@ -1,58 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH3_PROTOCOL "G8B10B" -CH0_MODE "DISABLED" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "RXTX" -CH3_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH3_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200 -CH3_RX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" -CH3_TX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" -CH3_TX_FIFO "DISABLED" -CH3_RX_FIFO "DISABLED" -CH3_TDRV "0" -#CH3_TX_FICLK_RATE 200 -#CH3_RXREFCLK_RATE "200" -#CH3_RX_FICLK_RATE 200 -CH3_TX_PRE "DISABLED" -CH3_RTERM_TX "50" -CH3_RX_EQ "DISABLED" -CH3_RTERM_RX "50" -CH3_RX_DCC "DC" -CH3_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH3_TX_SB "DISABLED" -CH3_RX_SB "DISABLED" -CH3_TX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" -CH3_COMMA_A "1100000101" -CH3_COMMA_B "0011111010" -CH3_COMMA_M "1111111100" -CH3_RXWA "ENABLED" -CH3_ILSM "ENABLED" -CH3_CTC "DISABLED" -CH3_CC_MATCH4 "0100011100" -CH3_CC_MATCH_MODE "1" -CH3_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH3_SSLB "DISABLED" -CH3_SPLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "ENABLED" - - diff --git a/code/ip/serdes_sync_source_downstream.ipx b/code/ip/serdes_sync_source_downstream.ipx index 1d162da..13ca784 100644 --- a/code/ip/serdes_sync_source_downstream.ipx +++ b/code/ip/serdes_sync_source_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_sync_source_downstream.lpc b/code/ip/serdes_sync_source_downstream.lpc index 666dd56..6a53c07 100644 --- a/code/ip/serdes_sync_source_downstream.lpc +++ b/code/ip/serdes_sync_source_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_source_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=04/29/2014 -Time=08:57:46 +Date=05/13/2014 +Time=08:58:11 [Parameters] Verilog=0 @@ -190,7 +190,7 @@ _cc_match_mode0=1 _cc_match_mode1=1 _cc_match_mode2=1 _cc_match_mode3=1 -_k00=01 +_k00=00 _k01=00 _k02=00 _k03=00 diff --git a/code/ip/serdes_sync_source_downstream.txt b/code/ip/serdes_sync_source_downstream.txt index fdbe384..400122b 100644 --- a/code/ip/serdes_sync_source_downstream.txt +++ b/code/ip/serdes_sync_source_downstream.txt @@ -30,7 +30,7 @@ CH0_RTERM_TX "50" CH0_RX_EQ "DISABLED" CH0_RTERM_RX "50" CH0_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "3" +CH0_LOS_THRESHOLD_LO "2" PLL_TERM "50" PLL_DCC "AC" PLL_LOL_SET "0" @@ -44,7 +44,7 @@ CH0_COMMA_M "1111111100" CH0_RXWA "ENABLED" CH0_ILSM "ENABLED" CH0_CTC "DISABLED" -CH0_CC_MATCH4 "0100011100" +CH0_CC_MATCH4 "0000011100" CH0_CC_MATCH_MODE "1" CH0_CC_MIN_IPG "3" CCHMARK "9" diff --git a/code/ip/serdes_sync_source_downstream.vhd b/code/ip/serdes_sync_source_downstream.vhd index 0c3024f..e0c6a6c 100644 --- a/code/ip/serdes_sync_source_downstream.vhd +++ b/code/ip/serdes_sync_source_downstream.vhd @@ -1534,7 +1534,6 @@ entity serdes_sync_source_downstream is GENERIC (USER_CONFIG_FILE : String := "serdes_sync_source_downstream.txt"); port ( ------------------ --- CH0 -- hdinp_ch0, hdinn_ch0 : in std_logic; hdoutp_ch0, hdoutn_ch0 : out std_logic; sci_sel_ch0 : in std_logic; @@ -1565,9 +1564,6 @@ entity serdes_sync_source_downstream is rx_cdr_lol_ch0_s : out std_logic; tx_div2_mode_ch0_c : in std_logic; rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ---- Miscillaneous ports sci_wrdata : in std_logic_vector (7 downto 0); sci_addr : in std_logic_vector (5 downto 0); diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index 28a10ac..120aabb 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -13,10 +13,11 @@ use work.soda_components.all; entity med_ecp3_sfp_4_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; - IS_SYNC_SLAVE : integer := c_NO); --select slave mode + IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + OSCCLK : in std_logic; -- 200 MHz reference clock + TX_DATACLK : in std_logic; -- 200 MHz data clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset --------------------------------------------------------------------------------------------------------------------------------------------------------- @@ -32,8 +33,10 @@ entity med_ecp3_sfp_4_sync_down is MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); MED_READ_IN : in std_logic_vector(3 downto 0); - + CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz --Sync operation RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); @@ -81,23 +84,9 @@ architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is -component DCS --- synthesis translate_off -generic - ( - DCSMODE : string :=“POS” - ); --- synthesis translate_on -port ( - CLK0 : in std_logic ; - CLK1 : in std_logic ; - SEL : in std_logic ; - DCSOUT : out std_logic) ; -end component; - - +signal clk_200_osc : std_logic; +signal clk_200_tx_data : std_logic; signal clk_200_i : std_logic_vector(3 downto 0); -signal clk_200_internal : std_logic_vector(3 downto 0); signal clk_rx_full : std_logic_vector(3 downto 0); signal clk_rx_half : std_logic_vector(3 downto 0); signal clk_tx_full : std_logic_vector(3 downto 0); @@ -109,7 +98,6 @@ signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0); signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0); - signal rst_n : t_HUB_BIT; signal rst : t_HUB_BIT; -- PL! signal rx_serdes_rst : t_HUB_BIT; @@ -128,6 +116,17 @@ signal rx_cdr_lol : t_HUB_BIT; signal tx_pll_lol : t_HUB_BIT; signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad +signal sci_ch_i : std_logic_vector(3 downto 0); +signal sci_qd_i : std_logic; +signal sci_reg_i : std_logic; +signal sci_addr_i : std_logic_vector(8 downto 0); +signal sci_data_in_i : std_logic_vector(7 downto 0); +signal sci_data_out_i : std_logic_vector(7 downto 0); +signal sci_read_i : std_logic; +signal sci_write_i : std_logic; +signal sci_write_shift_i : std_logic_vector(2 downto 0); +signal sci_read_shift_i : std_logic_vector(2 downto 0); + signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); @@ -151,18 +150,6 @@ signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_ve signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); - -signal sci_ch_i : std_logic_vector(3 downto 0); -signal sci_qd_i : std_logic; -signal sci_reg_i : std_logic; -signal sci_addr_i : std_logic_vector(8 downto 0); -signal sci_data_in_i : std_logic_vector(7 downto 0); -signal sci_data_out_i : std_logic_vector(7 downto 0); -signal sci_read_i : std_logic; -signal sci_write_i : std_logic; -signal sci_write_shift_i : std_logic_vector(2 downto 0); -signal sci_read_shift_i : std_logic_vector(2 downto 0); - signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); @@ -178,42 +165,44 @@ begin --SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready +clk_200_osc <= OSCCLK; -- This external clock is oscillator/pll generated !!! +clk_200_tx_data <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!! + gen_clocks : for i in 0 to 3 generate rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); - clk_200_internal(i) <= CLK; -- This external clock is the rx_fulll of the uplink !!! CLK_RX_FULL_OUT(i) <= clk_rx_full(i); --- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_200_i(i) <= CLK; --clk_rx_full(i); --- end generate; + gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate + clk_200_i(i) <= clk_rx_full(i); + end generate; --- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate --- clk_200_i(i) <= clk_200_internal(i); --- end generate; + gen_master_clock : if IS_SYNC_SLAVE = c_NO generate + clk_200_i(i) <= clk_200_tx_data; + end generate; end generate; - ------------------------------------------------- -- Serdes ------------------------------------------------- -THE_SERDES : entity work.serdes_4_sync_hub_downstream +THE_SERDES : entity work.serdes_4_sync_downstream port map( -- CHANNEL0 -- hdinp_ch0 => SD_RXD_P_IN(0), hdinn_ch0 => SD_RXD_N_IN(0), hdoutp_ch0 => SD_TXD_P_OUT(0), hdoutn_ch0 => SD_TXD_N_OUT(0), + rxiclk_ch0 => clk_200_i(0), sci_sel_ch0 => sci_ch_i(0), - txiclk_ch0 => clk_200_i(0), + txiclk_ch0 => clk_200_tx_data, rx_full_clk_ch0 => clk_rx_full(0), rx_half_clk_ch0 => clk_rx_half(0), tx_full_clk_ch0 => clk_tx_full(0), tx_half_clk_ch0 => clk_tx_half(0), - fpga_rxrefclk_ch0 => clk_200_internal(0), + fpga_rxrefclk_ch0 => clk_200_osc, txdata_ch0 => tx_data(0), tx_k_ch0 => tx_k(0), tx_force_disp_ch0 => '0', @@ -239,13 +228,14 @@ THE_SERDES : entity work.serdes_4_sync_hub_downstream hdinn_ch1 => SD_RXD_N_IN(1), hdoutp_ch1 => SD_TXD_P_OUT(1), hdoutn_ch1 => SD_TXD_N_OUT(1), + rxiclk_ch1 => clk_200_i(1), sci_sel_ch1 => sci_ch_i(1), - txiclk_ch1 => clk_200_i(1), + txiclk_ch1 => clk_200_tx_data, rx_full_clk_ch1 => clk_rx_full(1), rx_half_clk_ch1 => clk_rx_half(1), tx_full_clk_ch1 => clk_tx_full(1), tx_half_clk_ch1 => clk_tx_half(1), - fpga_rxrefclk_ch1 => clk_200_internal(1), + fpga_rxrefclk_ch1 => clk_200_osc, txdata_ch1 => tx_data(1), tx_k_ch1 => tx_k(1), tx_force_disp_ch1 => '0', @@ -271,13 +261,14 @@ THE_SERDES : entity work.serdes_4_sync_hub_downstream hdinn_ch2 => SD_RXD_N_IN(2), hdoutp_ch2 => SD_TXD_P_OUT(2), hdoutn_ch2 => SD_TXD_N_OUT(2), + rxiclk_ch2 => clk_200_i(2), sci_sel_ch2 => sci_ch_i(2), - txiclk_ch2 => clk_200_i(2), + txiclk_ch2 => clk_200_tx_data, rx_full_clk_ch2 => clk_rx_full(2), rx_half_clk_ch2 => clk_rx_half(2), tx_full_clk_ch2 => clk_tx_full(2), tx_half_clk_ch2 => clk_tx_half(2), - fpga_rxrefclk_ch2 => clk_200_internal(2), + fpga_rxrefclk_ch2 => clk_200_osc, txdata_ch2 => tx_data(2), tx_k_ch2 => tx_k(2), tx_force_disp_ch2 => '0', @@ -303,13 +294,14 @@ THE_SERDES : entity work.serdes_4_sync_hub_downstream hdinn_ch3 => SD_RXD_N_IN(3), hdoutp_ch3 => SD_TXD_P_OUT(3), hdoutn_ch3 => SD_TXD_N_OUT(3), + rxiclk_ch3 => clk_200_i(3), sci_sel_ch3 => sci_ch_i(3), - txiclk_ch3 => clk_200_i(3), + txiclk_ch3 => clk_200_tx_data, rx_full_clk_ch3 => clk_rx_full(3), rx_half_clk_ch3 => clk_rx_half(3), tx_full_clk_ch3 => clk_tx_full(3), tx_half_clk_ch3 => clk_tx_half(3), - fpga_rxrefclk_ch3 => clk_200_internal(3), + fpga_rxrefclk_ch3 => clk_200_osc, txdata_ch3 => tx_data(3), tx_k_ch3 => tx_k(3), tx_force_disp_ch3 => '0', @@ -338,7 +330,7 @@ THE_SERDES : entity work.serdes_4_sync_hub_downstream sci_rd => sci_read_i, sci_wrn => sci_write_i, - fpga_txrefclk => clk_200_i(0), + fpga_txrefclk => clk_200_osc, --clk_200_i(0), tx_serdes_rst_c => tx_serdes_rst(0), tx_pll_lol_qd_s => tx_pll_lol_quad, tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols @@ -364,7 +356,7 @@ generated_logic : for i in 0 to 3 generate THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n(i), - RX_REFCLK => clk_200_i(i), + RX_REFCLK => clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn TX_PLL_LOL_QD_S => tx_pll_lol(i), RX_SERDES_RST_CH_C => rx_serdes_rst(i), RX_CDR_LOL_CH_S => rx_cdr_lol(i), @@ -377,7 +369,7 @@ generated_logic : for i in 0 to 3 generate THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n(i), - TX_REFCLK => clk_200_internal(i), + TX_REFCLK => clk_200_osc, TX_PLL_LOL_QD_S => tx_pll_lol(i), RST_QD_C => rst_qd(i), TX_PCS_RST_CH_C => tx_pcs_rst(i), @@ -391,7 +383,7 @@ generated_logic : for i in 0 to 3 generate PROC_ALLOW : process(clk_200_i(i)) begin - if rising_edge(clk_200_i(i)) then + if rising_edge(clk_200_i(i)) then -- clk_200_tx_data ?? if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then rx_allow(i) <= '1'; tx_allow(i) <= '1'; @@ -406,7 +398,7 @@ generated_logic : for i in 0 to 3 generate tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK); - PROC_START_TIMER : process(clk_200_i(i)) + PROC_START_TIMER : process(clk_200_i(i)) --clk_200_tx_data?? begin if rising_edge(clk_200_i(i)) then if got_link_ready_i(i) = '1' then @@ -435,7 +427,7 @@ generated_logic : for i in 0 to 3 generate ------------------------------------------------- THE_TX : soda_tx_control port map( - CLK_200 => clk_200_i(i), + CLK_200 => clk_200_i(i), --clk_200_tx_data?? CLK_100 => SYSCLK, RESET_IN => rst(i), --CLEAR, PL! @@ -472,7 +464,7 @@ generated_logic : for i in 0 to 3 generate ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => clk_rx_full(i), --clk_200_i, PL! + CLK_200 => clk_200_i(i), --PL! CLK_100 => SYSCLK, RESET_IN => rst(i), --CLEAR, PL! @@ -656,7 +648,7 @@ end process; STAT_OP(i)(6) <= make_link_reset_i(i); STAT_OP(i)(5) <= request_retr_i(i); STAT_OP(i)(4) <= start_retr_i(i); - STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; + STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; end generate; end med_ecp3_sfp_4_sync_down_arch; \ No newline at end of file diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index 3b0abae..dabf48f 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -10,6 +10,7 @@ use work.trb_net_components.all; use work.med_sync_define.all; use work.soda_components.all; + entity med_ecp3_sfp_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); --select slave mode @@ -89,20 +90,14 @@ generic DCSMODE : string :=“POS” ); -- synthesis translate_on - port ( -CLK0 :in std_logic ; -CLK1 :in std_logic ; -SEL :in std_logic ; -DCSOUT :out std_logic) ; + CLK0 :in std_logic ; + CLK1 :in std_logic ; + SEL :in std_logic ; + DCSOUT :out std_logic) ; end component; - ---signal refclk_p_in_S : std_logic; --PL! ---signal refclk_n_in_S : std_logic; --PL! ---signal refclk2core_S : std_logic; --PL! - signal clk_200_i : std_logic; signal clk_200_internal : std_logic; signal clk_rx_full : std_logic; @@ -182,8 +177,6 @@ CLK_RX_FULL_OUT <= clk_rx_full; CLK_TX_HALF_OUT <= clk_tx_half; CLK_TX_FULL_OUT <= clk_tx_full; - - SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready @@ -193,7 +186,6 @@ SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches rst_n <= not(CLEAR or internal_make_link_reset_out); rst <= (CLEAR or internal_make_link_reset_out); - gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate clk_200_i <= clk_rx_full; end generate; @@ -208,8 +200,6 @@ end generate; ------------------------------------------------- THE_SERDES : entity work.serdes_sync_source_downstream port map( --- refclkp => PCSA_REFCLKP, -- external refclock straight into serdes PL! --- refclkn => PCSA_REFCLKN, -- external refclock straight into serdes PL! hdinp_ch0 => SD_RXD_P_IN, hdinn_ch0 => SD_RXD_N_IN, hdoutp_ch0 => SD_TXD_P_OUT, @@ -552,4 +542,4 @@ STAT_OP(6) <= make_link_reset_i; STAT_OP(5) <= request_retr_i; STAT_OP(4) <= start_retr_i; STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; -end med_ecp3_sfp_sync_down_arch; +end med_ecp3_sfp_sync_down_arch; \ No newline at end of file diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index a9a0745..3f0c78b 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -173,6 +173,11 @@ signal make_link_reset_i : std_logic; signal got_link_ready_i : std_logic; signal internal_make_link_reset_out : std_logic; +attribute syn_preserve of wa_position : signal is true; +attribute syn_keep of wa_position : signal is true; +attribute syn_preserve of wa_position_rx : signal is true; +attribute syn_keep of wa_position_rx : signal is true; + signal stat_rx_control_i : std_logic_vector(31 downto 0); signal stat_tx_control_i : std_logic_vector(31 downto 0); signal debug_rx_control_i : std_logic_vector(31 downto 0); diff --git a/code/soda_components.vhd b/code/soda_components.vhd index c0845e9..4fc1ea4 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -366,8 +366,9 @@ component med_ecp3_sfp_4_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); --select slave mode port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + OSCCLK : in std_logic; -- 200 MHz reference clock + TX_DATACLK : in std_logic; -- 200 MHz data clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset --------------------------------------------------------------------------------------------------------------------------------------------------------- @@ -383,8 +384,10 @@ component med_ecp3_sfp_4_sync_down is MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); MED_READ_IN : in std_logic_vector(3 downto 0); - + CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz --Sync operation RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); @@ -532,5 +535,19 @@ component soda_clockscaler is CLOCK_OUT : out std_logic ); end component; + +component DCS +-- synthesis translate_off +generic + ( + DCSMODE : string :=“POS” + ); +-- synthesis translate_on +port ( + CLK0 : in std_logic ; + CLK1 : in std_logic ; + SEL : in std_logic ; + DCSOUT : out std_logic) ; +end component; end package; \ No newline at end of file diff --git a/code/soda_hub_synconstraints.fdc b/code/soda_hub_synconstraints.fdc index 694b82b..c61076d 100644 --- a/code/soda_hub_synconstraints.fdc +++ b/code/soda_hub_synconstraints.fdc @@ -11,9 +11,9 @@ ###==== BEGIN Header # Synopsys, Inc. constraint file -# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc -# Written on Wed Dec 18 11:52:15 2013 -# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor +# /local/lemmens/lattice/soda/code/soda_hub_synconstraints.fdc +# Written on Tue May 20 15:36:03 2014 +# by Synplify Pro, I-2013.09L FDC Constraint Editor # Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. # These sections are generated from SCOPE spreadsheet tabs. @@ -37,17 +37,13 @@ define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable ###==== END Collections ###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0} -create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -create_clock -name {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5} - - -set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} } -set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} } +create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -add +create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -add +create_clock -name {THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add +create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -add +create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch1} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch1} -period {5.0} -waveform {0 2.5} -add +create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch2} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch2} -period {5.0} -waveform {0 2.5} -add +create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add ###==== END Clocks ###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) ###==== END "Generated Clocks" @@ -62,3 +58,10 @@ set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_ ###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) ###==== END "Compile Points" + + + + + + + diff --git a/code/trb3_periph_sodaclient.vhd b/code/trb3_periph_sodaclient.vhd index a8bba63..73784bd 100644 --- a/code/trb3_periph_sodaclient.vhd +++ b/code/trb3_periph_sodaclient.vhd @@ -219,10 +219,12 @@ signal link_phase_S : std_logic; --PL! signal soda_counter_i : unsigned(3 downto 0); attribute syn_keep of soda_counter_i : signal is true; -- fix signal names for constraining - attribute syn_preserve of soda_rx_clock_full : signal is true; - attribute syn_keep of soda_rx_clock_full : signal is true; - attribute syn_preserve of soda_rx_clock_half : signal is true; - attribute syn_keep of soda_rx_clock_half : signal is true; + attribute syn_preserve of clk_soda_i : signal is true; + attribute syn_keep of clk_soda_i : signal is true; +-- attribute syn_preserve of soda_rx_clock_full : signal is true; +-- attribute syn_keep of soda_rx_clock_full : signal is true; +-- attribute syn_preserve of soda_rx_clock_half : signal is true; +-- attribute syn_keep of soda_rx_clock_half : signal is true; attribute syn_preserve of clk_sys_internal : signal is true; attribute syn_keep of clk_sys_internal : signal is true; attribute syn_preserve of clk_raw_internal : signal is true; @@ -641,17 +643,17 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up soda_counter_i <= soda_counter_i+1; end if; end process; - - TEST_LINE(0) <= time_counter(1); + + TEST_LINE(0) <= time_counter(1); TEST_LINE(1) <= '0'; TEST_LINE(2) <= '0'; TEST_LINE(3) <= soda_counter_i(2); TEST_LINE(4) <= '0'; - TEST_LINE(5) <= '0'; + TEST_LINE(5) <= '0'; TEST_LINE(6) <= soda_rx_clock_half; TEST_LINE(7) <= '0'; TEST_LINE(8) <= '0'; - + TEST_LINE(15 downto 9) <= (others => '0'); -- otherwise it is floating diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index 103cfb4..a8ae655 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -234,25 +234,22 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is -- attribute syn_useioff of FLASH_DOUT : signal is true; -- attribute syn_useioff of FPGA5_COMM : signal is true; - attribute syn_keep of soda_counter_i : signal is true; + attribute syn_keep of soda_counter_i : signal is true; -- fix signal names for constraining - attribute syn_preserve of soda_rxup_clock_full : signal is true; - attribute syn_keep of soda_rxup_clock_full : signal is true; - attribute syn_preserve of clk_sys_internal : signal is true; attribute syn_keep of clk_sys_internal : signal is true; attribute syn_preserve of clk_raw_internal : signal is true; attribute syn_keep of clk_raw_internal : signal is true; - attribute syn_preserve of clk_soda_i : signal is true; - attribute syn_keep of clk_soda_i : signal is true; - attribute syn_preserve of txup_dlm_i : signal is true; - attribute syn_keep of txup_dlm_i : signal is true; - attribute syn_preserve of rxup_dlm_i : signal is true; - attribute syn_keep of rxup_dlm_i : signal is true; - attribute syn_preserve of txdn_dlm_i : signal is true; - attribute syn_keep of txdn_dlm_i : signal is true; - attribute syn_preserve of rxdn_dlm_i : signal is true; - attribute syn_keep of rxdn_dlm_i : signal is true; + attribute syn_preserve of clk_soda_i : signal is true; + attribute syn_keep of clk_soda_i : signal is true; + attribute syn_preserve of txup_dlm_i : signal is true; + attribute syn_keep of txup_dlm_i : signal is true; + attribute syn_preserve of rxup_dlm_i : signal is true; + attribute syn_keep of rxup_dlm_i : signal is true; + attribute syn_preserve of txdn_dlm_i : signal is true; + attribute syn_keep of txdn_dlm_i : signal is true; + attribute syn_preserve of rxdn_dlm_i : signal is true; + attribute syn_keep of rxdn_dlm_i : signal is true; begin @@ -541,7 +538,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up IS_SYNC_SLAVE => c_NO ) port map( - CLK => clk_soda_i, --clk_raw_internal, --clk_200_i, + OSCCLK => clk_raw_internal, + TX_DATACLK => clk_soda_i, --clk_raw_internal, --clk_200_i, SYSCLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, CLEAR => clear_i, @@ -592,17 +590,31 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up MED_READ_IN(2) => med_read_out(2), MED_READ_IN(3) => med_read_out(4), + CLK_RX_HALF_OUT(0) => open, + CLK_RX_HALF_OUT(1) => open, + CLK_RX_HALF_OUT(2) => open, + CLK_RX_HALF_OUT(3) => open, + CLK_RX_FULL_OUT(0) => soda_rxdn_clock_full(0), -- needed for sync replies i.e. calibration CLK_RX_FULL_OUT(1) => soda_rxdn_clock_full(1), -- needed for sync replies i.e. calibration CLK_RX_FULL_OUT(2) => soda_rxdn_clock_full(2), -- needed for sync replies i.e. calibration CLK_RX_FULL_OUT(3) => soda_rxdn_clock_full(3), -- needed for sync replies i.e. calibration + CLK_TX_HALF_OUT(0) => open, + CLK_TX_HALF_OUT(1) => open, + CLK_TX_HALF_OUT(2) => open, + CLK_TX_HALF_OUT(3) => open, + + CLK_TX_FULL_OUT(0) => open, + CLK_TX_FULL_OUT(1) => open, + CLK_TX_FULL_OUT(2) => open, + CLK_TX_FULL_OUT(3) => open, + RX_DLM(0) => rxdn_dlm_i(0), RX_DLM(1) => rxdn_dlm_i(1), RX_DLM(2) => rxdn_dlm_i(2), RX_DLM(3) => rxdn_dlm_i(3), --- RX_DLM_WORD(0*8+7 downto 0*8) => rxdn_dlm_word(1), RX_DLM_WORD(0) => rxdn_dlm_word(0), RX_DLM_WORD(1) => rxdn_dlm_word(1), RX_DLM_WORD(2) => rxdn_dlm_word(2), @@ -613,7 +625,6 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up TX_DLM(2) => txdn_dlm_i(2), TX_DLM(3) => txdn_dlm_i(3), --- TX_DLM_WORD(0*8+7 downto 0*8) => txdn_dlm_word(1), TX_DLM_WORD(0) => txdn_dlm_word(0), TX_DLM_WORD(1) => txdn_dlm_word(1), TX_DLM_WORD(2) => txdn_dlm_word(2), @@ -670,13 +681,11 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up SCI_NACK => sci2_nack, --Status and control port --- STAT_OP(0*16+15 downto 0*16) => med_stat_op(1*16+15 downto 1*16), STAT_OP(0) => med_stat_op(1*16+15 downto 1*16), STAT_OP(1) => med_stat_op(6*16+15 downto 6*16), STAT_OP(2) => med_stat_op(2*16+15 downto 2*16), STAT_OP(3) => med_stat_op(4*16+15 downto 4*16), --- CTRL_OP(0*16+15 downto 0*16) => med_ctrl_op(1*16+15 downto 1*16), CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16), CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16), CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16), diff --git a/soda_client.ldf b/soda_client.ldf index 93dc2c1..ab0653e 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -314,7 +314,7 @@ - + diff --git a/soda_client.lpf b/soda_client.lpf index b047079..e7b5264 100644 --- a/soda_client.lpf +++ b/soda_client.lpf @@ -1,5 +1,4 @@ -rvl_alias "clk_soda_i" "clk_soda_i"; -RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0"; +RVL_ALIAS "clk_soda_i" "clk_soda_i"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; @@ -9,16 +8,15 @@ BLOCK RD_DURING_WR_PATHS ; # SYSCONFIG MCCLK_FREQ = 2.5; # FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; # FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; # FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Clock I/O ################################################################# -LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; #LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; #LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; #LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ; #LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; DEFINE PORT GROUP "CLK_group" "CLK*" ; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; @@ -208,16 +206,11 @@ MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ; #MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; BLOCK JTAGPATHS ; ## IOBUF ALLPORTS ; -#USE SECONDARY NET "reveal_ist_260" ; -USE PRIMARY NET "clk_raw_internal" ; -USE PRIMARY NET "clk_sys_internal" ; -#USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ; -#USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ; -#USE PRIMARY PURE NET "CLK_PCLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; -USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; -USE PRIMARY NET "soda_rx_clock_full" ; -USE PRIMARY NET "soda_rx_clock_half" ; +USE PRIMARY NET "clk_raw_internal_c" ; +USE PRIMARY NET "clk_sys_internal_c" ; +USE PRIMARY NET "clk_soda_i" ; +MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl index 7d81ab7..eb571cc 100644 --- a/soda_hub_probe.rvl +++ b/soda_hub_probe.rvl @@ -1,9 +1,9 @@ - + - + - + @@ -11,25 +11,7 @@ - - - - - - - - - - - - - - - - - - - + @@ -40,282 +22,66 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - + + - - diff --git a/soda_source.ldf b/soda_source.ldf index 9114673..fa9f195 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -32,6 +32,9 @@ + + + @@ -44,6 +47,12 @@ + + + + + + diff --git a/soda_source.lpf b/soda_source.lpf index 1bb7ff1..b2ee04e 100644 --- a/soda_source.lpf +++ b/soda_source.lpf @@ -1,4 +1,4 @@ -rvl_alias "clk_raw_internal" "clk_raw_internal"; +RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; @@ -13,10 +13,10 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# # Clock I/O ################################################################# -LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; -LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? -LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; #LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; #LOCATE COMP "PCSA_REFCLKP" SITE "AC17"; #LOCATE COMP "PCSA_REFCLKN" SITE "AC18"; @@ -183,8 +183,7 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ=20 ; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +SYSCONFIG MCCLK_FREQ=20 ; # FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; # FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; # FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; @@ -212,20 +211,19 @@ MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ; -MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ; MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; -MULTICYCLE TO CELL "THE_SODA_SOURCE.packet_builder.soda_cmd_word_S*" 10.000000 ns ; BLOCK JTAGPATHS ; ## IOBUF ALLPORTS ; #USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; -USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; - -FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ; -FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ; -FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ; -FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ; -USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ; -USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ; -USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ; -USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ; - +#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; +#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ; +#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ; +#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ; +#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ; +#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ; +#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ; +#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ; +#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ; +USE PRIMARY NET "THE_SYNC_LINK/CLK_RX_FULL_OUT_c" ; +USE PRIMARY NET "clk_sys_internal_c" ; +MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl index 1cf260f..87566d1 100644 --- a/soda_source_probe.rvl +++ b/soda_source_probe.rvl @@ -1,10 +1,10 @@ - + - + - + diff --git a/trb3_soda_client.xcf b/trb3_soda_client.xcf index b9c0e70..ee24f3b 100644 --- a/trb3_soda_client.xcf +++ b/trb3_soda_client.xcf @@ -47,8 +47,8 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit - 05/06/14 09:58:37 + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140522.bit + 05/22/14 13:40:45 Fast Program