From: hadeshyp Date: Tue, 19 Dec 2006 16:48:18 +0000 (+0000) Subject: first simulation with api_apl_chain seems to be not so bad, Ingo X-Git-Tag: oldGBE~771 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e468eec899a6cf5ac1ba8083f3b45f7dc5e0eebd;p=trbnet.git first simulation with api_apl_chain seems to be not so bad, Ingo --- diff --git a/testbench/testsim.tcl b/testbench/testsim.tcl index fc5802c..4fc9f2a 100644 --- a/testbench/testsim.tcl +++ b/testbench/testsim.tcl @@ -1,5 +1,7 @@ -ntrace select -o on -m / -l this -ntrace select -o on -m /UUT/ -l this +#ntrace select -o on -m / -l this +#ntrace select -o on -m /UUT/ -l this +ntrace select -o on -m /APL1/ -l this +#ntrace select -o on -m /API1/ -l this ntrace start run 1000 ns quit \ No newline at end of file diff --git a/testbench/trb_net_dummy_apl.vhd b/testbench/trb_net_dummy_apl.vhd index c8f8c82..0f1f7c1 100644 --- a/testbench/trb_net_dummy_apl.vhd +++ b/testbench/trb_net_dummy_apl.vhd @@ -10,7 +10,7 @@ use work.trb_net_std.all; entity trb_net_dummy_apl is - generic (TARGET_ADDRESS : integer := x"ffff"; + generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"ffff"; PREFILL_LENGTH : integer := 3; TRANSFER_LENGTH : integer := 6); -- length of dummy data @@ -21,26 +21,26 @@ entity trb_net_dummy_apl is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_OUT: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_OUT: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_IN: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_OUT: in STD_LOGIC; -- - APL_DTYPE_OUT: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_OUT: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_OUT: in STD_LOGIC_VECTOR (15 downto 0); -- Address of + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_OUT: out STD_LOGIC; -- + APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of -- the target (only for active APIs) -- Receiver port - APL_DATA_IN: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_IN: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_IN: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_OUT: in STD_LOGIC; -- Read data word + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out + APL_READ_OUT: out STD_LOGIC; -- Read data word -- APL Control port - APL_RUN_IN: out STD_LOGIC; -- Data transfer is running + APL_RUN_IN: in STD_LOGIC; -- Data transfer is running -- APL_MY_ADDRESS_OUT: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_IN: out STD_LOGIC_VECTOR (7 downto 0); + APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0) ); END trb_net_dummy_apl; @@ -54,7 +54,7 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is begin APL_READ_OUT <= '1'; --just read, do not check - APL_DTYPE_OUT <= x"01"; + APL_DTYPE_OUT <= x"1"; APL_ERROR_PATTERN_OUT <= x"12345678"; APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; APL_DATA_OUT <= reg_counter; @@ -62,33 +62,33 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN) begin -- process - APL_SEND_OUT = '0'; - next_state = MY_ERROR; - next_counter = reg_counter; - APL_WRITE_OUT = '0'; + APL_SEND_OUT <= '0'; + next_state <= MY_ERROR; + next_counter <= reg_counter; + APL_WRITE_OUT <= '0'; ------------------------------------------------------------------------- -- IDLE ------------------------------------------------------------------------- if current_state = IDLE then if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then - next_state = RUNNING; + next_state <= RUNNING; else - next_state = IDLE; - next_counter = reg_counter +1; - APL_WRITE_OUT = '1'; + next_state <= IDLE; + next_counter <= reg_counter +1; + APL_WRITE_OUT <= '1'; end if; ----------------------------------------------------------------------- -- RUNNING ----------------------------------------------------------------------- elsif current_state = RUNNING then - APL_SEND_OUT = '1'; + APL_SEND_OUT <= '1'; if reg_counter = TRANSFER_LENGTH then - next_state = WAITING; + next_state <= WAITING; else - next_state = RUNNING; + next_state <= RUNNING; if APL_FIFO_FULL_IN = '0' then - next_counter = reg_counter +1; - APL_WRITE_OUT = '1'; + next_counter <= reg_counter +1; + APL_WRITE_OUT <= '1'; end if; end if; ----------------------------------------------------------------------- @@ -96,11 +96,31 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is ----------------------------------------------------------------------- elsif current_state = WAITING then if APL_RUN_IN = '1' then - next_state = WAITING; + next_state <= WAITING; else - next_state = IDLE; + next_state <= IDLE; + next_counter <= (others => '0'); end if; end if; -- end state switch end process; - + + + CLK_REG: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= IDLE; + reg_counter <= (others => '0'); + elsif CLK_EN = '1' then + reg_counter <= next_counter; + current_state <= next_state; + + else + reg_counter <= reg_counter; + current_state <= current_state; + + end if; + end if; + end process; + end trb_net_dummy_apl_arch; diff --git a/testbench/trb_net_dummy_apl_api_chain_real.vhd b/testbench/trb_net_dummy_apl_api_chain_real.vhd new file mode 100644 index 0000000..5870e9f --- /dev/null +++ b/testbench/trb_net_dummy_apl_api_chain_real.vhd @@ -0,0 +1,338 @@ +library ieee; + +use ieee.std_logic_1164.all; + +USE ieee.std_logic_signed.ALL; + +USE ieee.std_logic_arith.ALL; + + +entity trb_net_dummy_apl_api_chain_testbench is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + APL_RUN_OUT: out std_logic + + ); +end trb_net_dummy_apl_api_chain_testbench; + +architecture trb_net_dummy_apl_api_chain_testbench_arch of trb_net_dummy_apl_api_chain_testbench is + +component trb_net_active_api + + generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), + -- for the direction to + -- internal world + FIFO_TO_APL_DEPTH : integer := 3; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- + APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out + APL_READ_IN: in STD_LOGIC; -- Read data word + + -- APL Control port + APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running + APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); + + -- Internal direction port + -- This is just a clone from trb_net_iobuf + + INT_INIT_DATAREADY_OUT: out STD_LOGIC; + INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_IN: in STD_LOGIC; + INT_INIT_DATAREADY_IN: in STD_LOGIC; + INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_OUT: out STD_LOGIC; + + INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out STD_LOGIC; + INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_IN: in STD_LOGIC; + INT_REPLY_DATAREADY_IN: in STD_LOGIC; + INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_OUT: out STD_LOGIC + -- Status and control port + + -- not needed now, but later + + ); +END component; + +component trb_net_dummy_apl + generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"ffff"; + PREFILL_LENGTH : integer := 3; + TRANSFER_LENGTH : integer := 6); -- length of dummy data + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_OUT: out STD_LOGIC; -- + APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out + APL_READ_OUT: out STD_LOGIC; -- Read data word + + -- APL Control port + APL_RUN_IN: in STD_LOGIC; -- Data transfer is running + APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0) + ); +END component; + + +signal apl_data_out_apl1: STD_LOGIC_VECTOR (47 downto 0); +signal apl_write_apl1: STD_LOGIC; +signal apl_fifo_full_apl1: STD_LOGIC; +signal apl_short_transfer_apl1: STD_LOGIC; +signal apl_dtype_apl1: STD_LOGIC_VECTOR (3 downto 0); +signal apl_error_pattern_apl1: STD_LOGIC_VECTOR (31 downto 0); +signal apl_send_apl1: STD_LOGIC; +signal apl_target_adress_apl1: STD_LOGIC_VECTOR (15 downto 0); +signal apl_data_in_apl1: STD_LOGIC_VECTOR (47 downto 0); +signal apl_typ_apl1: STD_LOGIC_VECTOR (2 downto 0); +signal apl_dataready_apl1: STD_LOGIC; +signal apl_read_apl1: STD_LOGIC; +signal apl_run_apl1: STD_LOGIC; +signal apl_seqnr_apl1: STD_LOGIC_VECTOR (7 downto 0); + +signal apl_data_out_apl2: STD_LOGIC_VECTOR (47 downto 0); +signal apl_write_apl2: STD_LOGIC; +signal apl_fifo_full_apl2: STD_LOGIC; +signal apl_short_transfer_apl2: STD_LOGIC; +signal apl_dtype_apl2: STD_LOGIC_VECTOR (3 downto 0); +signal apl_error_pattern_apl2: STD_LOGIC_VECTOR (31 downto 0); +signal apl_send_apl2: STD_LOGIC; +signal apl_target_adress_apl2: STD_LOGIC_VECTOR (15 downto 0); +signal apl_data_in_apl2: STD_LOGIC_VECTOR (47 downto 0); +signal apl_typ_apl2: STD_LOGIC_VECTOR (2 downto 0); +signal apl_dataready_apl2: STD_LOGIC; +signal apl_read_apl2: STD_LOGIC; +signal apl_run_apl2: STD_LOGIC; +signal apl_seqnr_apl2: STD_LOGIC_VECTOR (7 downto 0); + +signal INT_INIT_DATAREADY_1_to_2: STD_LOGIC; +signal INT_INIT_DATA_1_to_2: STD_LOGIC_VECTOR (50 downto 0); +signal INT_INIT_READ_1_to_2: STD_LOGIC; +signal INT_INIT_DATAREADY_2_to_1: STD_LOGIC; +signal INT_INIT_DATA_2_to_1: STD_LOGIC_VECTOR (50 downto 0); +signal INT_INIT_READ_2_to_1: STD_LOGIC; +signal INT_REPLY_DATAREADY_1_to_2: STD_LOGIC; +signal INT_REPLY_DATA_1_to_2: STD_LOGIC_VECTOR (50 downto 0); +signal INT_REPLY_READ_1_to_2: STD_LOGIC; +signal INT_REPLY_DATAREADY_2_to_1: STD_LOGIC; +signal INT_REPLY_DATA_2_to_1: STD_LOGIC_VECTOR (50 downto 0); +signal INT_REPLY_READ_2_to_1: STD_LOGIC; + + +begin + + + + +------------------------------------------------------------------------------- +-- the 2 APLs +------------------------------------------------------------------------------- + +APL1: trb_net_dummy_apl + generic map ( +-- TARGET_ADDRESS => x"0002", + TARGET_ADDRESS => x"000f", + PREFILL_LENGTH => 0, + TRANSFER_LENGTH => 2) + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- APL Transmitter port + APL_DATA_OUT => apl_data_out_apl1, + APL_WRITE_OUT => apl_write_apl1, + APL_FIFO_FULL_IN => apl_fifo_full_apl1, + APL_SHORT_TRANSFER_OUT => apl_short_transfer_apl1, + APL_DTYPE_OUT => apl_dtype_apl1, + APL_ERROR_PATTERN_OUT => apl_error_pattern_apl1, + APL_SEND_OUT => apl_send_apl1, + APL_TARGET_ADDRESS_OUT => apl_target_adress_apl1, + + -- Receiver port + APL_DATA_IN => apl_data_in_apl1, + APL_TYP_IN => apl_typ_apl1, + APL_DATAREADY_IN => apl_dataready_apl1, + APL_READ_OUT => apl_read_apl1, + + -- APL Control port + APL_RUN_IN => apl_run_apl1, + APL_SEQNR_IN => apl_seqnr_apl1 + ); + +APL2: trb_net_dummy_apl + generic map ( + TARGET_ADDRESS => x"0001", + PREFILL_LENGTH => 0, + TRANSFER_LENGTH => 2) + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- APL Transmitter port + APL_DATA_OUT => apl_data_out_apl2, + APL_WRITE_OUT => apl_write_apl2, + APL_FIFO_FULL_IN => apl_fifo_full_apl2, + APL_SHORT_TRANSFER_OUT => apl_short_transfer_apl2, + APL_DTYPE_OUT => apl_dtype_apl2, + APL_ERROR_PATTERN_OUT => apl_error_pattern_apl2, + APL_SEND_OUT => apl_send_apl2, + APL_TARGET_ADDRESS_OUT => apl_target_adress_apl2, + + -- Receiver port + APL_DATA_IN => apl_data_in_apl2, + APL_TYP_IN => apl_typ_apl2, + APL_DATAREADY_IN => apl_dataready_apl2, + APL_READ_OUT => apl_read_apl2, + + -- APL Control port + APL_RUN_IN => apl_run_apl2, + APL_SEQNR_IN => apl_seqnr_apl2 + ); + +------------------------------------------------------------------------------- +-- the 2 APIs +------------------------------------------------------------------------------- + +API1: trb_net_active_api + generic map ( + FIFO_TERM_BUFFER_DEPTH => 3) + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- APL Transmitter port + APL_DATA_IN => apl_data_out_apl1, + APL_WRITE_IN => apl_write_apl1, + APL_FIFO_FULL_OUT => apl_fifo_full_apl1, + APL_SHORT_TRANSFER_IN => apl_short_transfer_apl1, + APL_DTYPE_IN => apl_dtype_apl1, + APL_ERROR_PATTERN_IN => apl_error_pattern_apl1, + APL_SEND_IN => apl_send_apl1, + APL_TARGET_ADDRESS_IN => apl_target_adress_apl1, + + -- Receiver port + APL_DATA_OUT => apl_data_in_apl1, + APL_TYP_OUT => apl_typ_apl1, + APL_DATAREADY_OUT => apl_dataready_apl1, + APL_READ_IN => apl_read_apl1, + + -- APL Control port + APL_RUN_OUT => apl_run_apl1, + APL_SEQNR_OUT => apl_seqnr_apl1, + APL_MY_ADDRESS_IN => x"0001", + + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_1_to_2, + INT_INIT_DATA_OUT => INT_INIT_DATA_1_to_2, + INT_INIT_READ_IN => INT_INIT_READ_1_to_2, + INT_INIT_DATAREADY_IN => INT_INIT_DATAREADY_2_to_1, + INT_INIT_DATA_IN => INT_INIT_DATA_2_to_1, + INT_INIT_READ_OUT => INT_INIT_READ_2_to_1, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => INT_REPLY_DATAREADY_1_to_2, + INT_REPLY_DATA_OUT => INT_REPLY_DATA_1_to_2, + INT_REPLY_READ_IN => INT_REPLY_READ_1_to_2, + INT_REPLY_DATAREADY_IN => INT_REPLY_DATAREADY_2_to_1, + INT_REPLY_DATA_IN => INT_REPLY_DATA_2_to_1, + INT_REPLY_READ_OUT => INT_REPLY_READ_2_to_1 + ); + +API2: trb_net_active_api + generic map ( + FIFO_TERM_BUFFER_DEPTH => 3) + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- APL Transmitter port + APL_DATA_IN => apl_data_out_apl2, + APL_WRITE_IN => apl_write_apl2, + APL_FIFO_FULL_OUT => apl_fifo_full_apl2, + APL_SHORT_TRANSFER_IN => apl_short_transfer_apl2, + APL_DTYPE_IN => apl_dtype_apl2, + APL_ERROR_PATTERN_IN => apl_error_pattern_apl2, + APL_SEND_IN => apl_send_apl2, + APL_TARGET_ADDRESS_IN => apl_target_adress_apl2, + + -- Receiver port + APL_DATA_OUT => apl_data_in_apl2, + APL_TYP_OUT => apl_typ_apl2, + APL_DATAREADY_OUT => apl_dataready_apl2, + APL_READ_IN => apl_read_apl2, + + -- APL Control port + APL_RUN_OUT => apl_run_apl2, + APL_SEQNR_OUT => apl_seqnr_apl2, + APL_MY_ADDRESS_IN => x"0002", + + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_2_to_1, + INT_INIT_DATA_OUT => INT_INIT_DATA_2_to_1, + INT_INIT_READ_IN => INT_INIT_READ_2_to_1, + INT_INIT_DATAREADY_IN => INT_INIT_DATAREADY_1_to_2, + INT_INIT_DATA_IN => INT_INIT_DATA_1_to_2, + INT_INIT_READ_OUT => INT_INIT_READ_1_to_2, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => INT_REPLY_DATAREADY_2_to_1, + INT_REPLY_DATA_OUT => INT_REPLY_DATA_2_to_1, + INT_REPLY_READ_IN => INT_REPLY_READ_2_to_1, + INT_REPLY_DATAREADY_IN => INT_REPLY_DATAREADY_1_to_2, + INT_REPLY_DATA_IN => INT_REPLY_DATA_1_to_2, + INT_REPLY_READ_OUT => INT_REPLY_READ_1_to_2 + ); + + APL_RUN_OUT <= apl_run_apl1; + +end trb_net_dummy_apl_api_chain_testbench_arch; + + + diff --git a/testbench/trb_net_dummy_apl_api_chain_testbench.vhd b/testbench/trb_net_dummy_apl_api_chain_testbench.vhd index 0b6c265..c77e336 100644 --- a/testbench/trb_net_dummy_apl_api_chain_testbench.vhd +++ b/testbench/trb_net_dummy_apl_api_chain_testbench.vhd @@ -41,7 +41,7 @@ component trb_net_active_api APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr APL_SEND_IN: in STD_LOGIC; -- Release sending of the data APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of -- the target (only for active APIs) @@ -74,7 +74,7 @@ component trb_net_active_api INT_REPLY_READ_IN: in STD_LOGIC; INT_REPLY_DATAREADY_IN: in STD_LOGIC; INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; + INT_REPLY_READ_OUT: out STD_LOGIC -- Status and control port -- not needed now, but later @@ -83,7 +83,7 @@ component trb_net_active_api END component; component trb_net_dummy_apl - generic (TARGET_ADDRESS : integer := x"ffff"; + generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"ffff"; PREFILL_LENGTH : integer := 3; TRANSFER_LENGTH : integer := 6); -- length of dummy data @@ -94,25 +94,25 @@ component trb_net_dummy_apl CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_OUT: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_OUT: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_IN: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_OUT: in STD_LOGIC; -- - APL_DTYPE_OUT: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_OUT: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_OUT: in STD_LOGIC_VECTOR (15 downto 0); -- Address of + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_OUT: out STD_LOGIC; -- + APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of -- the target (only for active APIs) -- Receiver port - APL_DATA_IN: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_IN: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_IN: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_OUT: in STD_LOGIC; -- Read data word + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out + APL_READ_OUT: out STD_LOGIC; -- Read data word -- APL Control port - APL_RUN_IN: out STD_LOGIC; -- Data transfer is running - APL_SEQNR_IN: out STD_LOGIC_VECTOR (7 downto 0); + APL_RUN_IN: in STD_LOGIC; -- Data transfer is running + APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0) ); END component; @@ -146,6 +146,20 @@ signal apl_read_apl2: STD_LOGIC; signal apl_run_apl2: STD_LOGIC; signal apl_seqnr_apl2: STD_LOGIC_VECTOR (7 downto 0); +signal INT_INIT_DATAREADY_1_to_2: STD_LOGIC; +signal INT_INIT_DATA_1_to_2: STD_LOGIC_VECTOR (50 downto 0); +signal INT_INIT_READ_1_to_2: STD_LOGIC; +signal INT_INIT_DATAREADY_2_to_1: STD_LOGIC; +signal INT_INIT_DATA_2_to_1: STD_LOGIC_VECTOR (50 downto 0); +signal INT_INIT_READ_2_to_1: STD_LOGIC; +signal INT_REPLY_DATAREADY_1_to_2: STD_LOGIC; +signal INT_REPLY_DATA_1_to_2: STD_LOGIC_VECTOR (50 downto 0); +signal INT_REPLY_READ_1_to_2: STD_LOGIC; +signal INT_REPLY_DATAREADY_2_to_1: STD_LOGIC; +signal INT_REPLY_DATA_2_to_1: STD_LOGIC_VECTOR (50 downto 0); +signal INT_REPLY_READ_2_to_1: STD_LOGIC; + + begin @@ -167,7 +181,8 @@ begin APL1: trb_net_dummy_apl generic map ( - TARGET_ADDRESS => 1, +-- TARGET_ADDRESS => x"0002", + TARGET_ADDRESS => x"000f", PREFILL_LENGTH => 0, TRANSFER_LENGTH => 2) port map ( @@ -198,7 +213,7 @@ APL1: trb_net_dummy_apl APL2: trb_net_dummy_apl generic map ( - TARGET_ADDRESS => 1, + TARGET_ADDRESS => x"0001", PREFILL_LENGTH => 0, TRANSFER_LENGTH => 2) port map ( @@ -233,8 +248,12 @@ APL2: trb_net_dummy_apl API1: trb_net_active_api generic map ( - TRANSFER_LENGTH => 2) + FIFO_TERM_BUFFER_DEPTH => 3) port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + -- APL Transmitter port APL_DATA_IN => apl_data_out_apl1, APL_WRITE_IN => apl_write_apl1, @@ -254,7 +273,8 @@ API1: trb_net_active_api -- APL Control port APL_RUN_OUT => apl_run_apl1, APL_SEQNR_OUT => apl_seqnr_apl1, - + APL_MY_ADDRESS_IN => x"0001", + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_1_to_2, INT_INIT_DATA_OUT => INT_INIT_DATA_1_to_2, INT_INIT_READ_IN => INT_INIT_READ_1_to_2, @@ -273,8 +293,12 @@ API1: trb_net_active_api API2: trb_net_active_api generic map ( - TRANSFER_LENGTH => 2) + FIFO_TERM_BUFFER_DEPTH => 3) port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + -- APL Transmitter port APL_DATA_IN => apl_data_out_apl2, APL_WRITE_IN => apl_write_apl2, @@ -294,7 +318,8 @@ API2: trb_net_active_api -- APL Control port APL_RUN_OUT => apl_run_apl2, APL_SEQNR_OUT => apl_seqnr_apl2, - + APL_MY_ADDRESS_IN => x"0002", + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_2_to_1, INT_INIT_DATA_OUT => INT_INIT_DATA_2_to_1, INT_INIT_READ_IN => INT_INIT_READ_2_to_1, @@ -314,9 +339,9 @@ API2: trb_net_active_api end trb_net_dummy_apl_api_chain_testbench_arch; --- fuse -prj trb_net_active_api_testbench_beh.prj -top trb_net_active_api_testbench -o trb_net_active_api_testbench +-- fuse -prj trb_net_dummy_apl_api_chain_testbench_beh.prj -top trb_net_dummy_apl_api_chain_testbench -o trb_net_dummy_apl_api_chain_testbench --- trb_net_active_api_testbench -tclbatch testsim.tcl +-- trb_net_dummy_apl_api_chain_testbench -tclbatch testsim.tcl -- ntrace select -o on -m / -l this -- ntrace start diff --git a/testbench/trb_net_dummy_apl_api_chain_testbench_beh.prj b/testbench/trb_net_dummy_apl_api_chain_testbench_beh.prj new file mode 100644 index 0000000..c6d3e8f --- /dev/null +++ b/testbench/trb_net_dummy_apl_api_chain_testbench_beh.prj @@ -0,0 +1,7 @@ +vhdl work "../trb_net_std.vhd" +vhdl work "../trb_net_fifo.vhd" +vhdl work "../xilinx/trb_net_fifo_arch.vhd" +vhdl work "../xilinx/shift_lut_x16.vhd" +vhdl work "../trb_net_active_api.vhd" +vhdl work "trb_net_dummy_apl.vhd" +vhdl work "trb_net_dummy_apl_api_chain_testbench.vhd" diff --git a/trb_net_active_api.vhd b/trb_net_active_api.vhd index 239a80b..44a0861 100644 --- a/trb_net_active_api.vhd +++ b/trb_net_active_api.vhd @@ -55,22 +55,22 @@ entity trb_net_active_api is INT_INIT_DATAREADY_OUT: out STD_LOGIC; INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word INT_INIT_READ_IN: in STD_LOGIC; - INT_INIT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits + INT_INIT_DATAREADY_IN: in STD_LOGIC; INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word INT_INIT_READ_OUT: out STD_LOGIC; - INT_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits + INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_REPLY_DATAREADY_OUT: out STD_LOGIC; INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word INT_REPLY_READ_IN: in STD_LOGIC; - INT_REPLY_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits + INT_REPLY_DATAREADY_IN: in STD_LOGIC; INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - INT_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0) -- Status bits + INT_REPLY_READ_OUT: out STD_LOGIC + -- Status and control port -- not needed now, but later @@ -136,6 +136,10 @@ signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 down signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); signal next_INT_INIT_DATA_OUT, reg_INT_INIT_DATA_OUT: std_logic_vector(50 downto 0); signal next_INT_INIT_DATAREADY_OUT, reg_INT_INIT_DATAREADY_OUT: std_logic; +signal next_INT_REPLY_READ_OUT, reg_INT_REPLY_READ_OUT: std_logic; +signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; +signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0); +signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); begin @@ -207,7 +211,10 @@ end generate CHECK_BUFFER; fifo_term_buffer_read<= '0'; INT_REPLY_DATAREADY_OUT <= '0'; INT_REPLY_DATA_OUT(DWORD_POSITION) <= (others => '0'); - INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; + INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; +----------------------------------------------------------------------- +-- IDLE +----------------------------------------------------------------------- if tb_current_state = IDLE then INT_INIT_READ_OUT <= '1'; -- I always can read tb_next_state <= IDLE; @@ -218,23 +225,28 @@ end generate CHECK_BUFFER; fifo_term_buffer_data_in(F3_POSITION) <= INT_INIT_DATA_IN(F3_POSITION); fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_HDR; tb_next_registered_target <= INT_INIT_DATA_IN(TARGET_POSITION); - if fifo_term_buffer_empty = '1' and (tb_next_registered_target = APL_MY_ADDRESS_IN - or tb_next_registered_target = BROADCAST_ADRESS) then + if fifo_term_buffer_full = '0' and (INT_INIT_DATA_IN(TARGET_POSITION) = APL_MY_ADDRESS_IN + or INT_INIT_DATA_IN(TARGET_POSITION) = BROADCAST_ADRESS) then fifo_term_buffer_write <= '1'; else fifo_term_buffer_write <= '0'; + end if; elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_DAT and INT_INIT_DATAREADY_IN = '1' then fifo_term_buffer_data_in <= INT_INIT_DATA_IN; - if fifo_term_buffer_empty = '1' and (tb_registered_target = APL_MY_ADDRESS_IN + if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN or tb_registered_target = BROADCAST_ADRESS) then fifo_term_buffer_write <= '1'; else fifo_term_buffer_write <= '0'; + end if; elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_TRM and INT_INIT_DATAREADY_IN = '1' then tb_next_registered_trailer <= INT_INIT_DATA_IN(DWORD_POSITION); --keep trailer for later use tb_next_state <= RUNNING; end if; +----------------------------------------------------------------------- +-- RUNNING +----------------------------------------------------------------------- elsif tb_current_state = RUNNING then tb_next_state <= RUNNING; if fifo_term_buffer_empty = '0' then -- Have buffered stuff @@ -348,6 +360,7 @@ end generate CHECK_BUFFER; else fifo_to_int_read <= '0'; end if; + end if; -- fifo_to_int_empty = '0' end if; else -- APL_SEND_IN: still running next_state <= RUNNING; @@ -360,7 +373,8 @@ end generate CHECK_BUFFER; fifo_to_int_read <= '1'; else fifo_to_int_read <= '0'; - end if; + end if; + end if; -- fifo_to_int_empty = '0' end if; ------------------------------------------------------------------------------- -- SHUTDOWN: Empty the pipe @@ -375,6 +389,7 @@ end generate CHECK_BUFFER; fifo_to_int_read <= '1'; else fifo_to_int_read <= '0'; + end if; else -- we are done next_state <= SEND_TRAILER; @@ -402,27 +417,28 @@ end generate CHECK_BUFFER; next_state <= WAITING; -- here we have to supply the receiver port -- part 1: connection to network - if fifo_to_apl_empty = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then + if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then next_INT_REPLY_READ_OUT <= '1'; end if; if reg_INT_REPLY_READ_OUT = '1' and INT_REPLY_DATAREADY_IN = '1' then - fifo_to_apl_write <= '1'; + fifo_to_apl_write <= '1'; -- use fifo as the pipe end if; -- part 2: connection to apl - if fifo_to_apl_empty = '0' then - -- data words have to be prepared - next_APL_DATAREADY_OUT <= '1'; + if (fifo_to_apl_empty = '0') then + next_APL_DATAREADY_OUT <= '1'; next_APL_DATA_OUT <= fifo_to_apl_data_out(DWORD_POSITION); - next_APL_TYP_OUT <= fifo_to_apl_data_out(TYP_POSITION); - end if; + next_APL_TYP_OUT <= fifo_to_apl_data_out(TYPE_POSITION); + end if; -- read/no read + if reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1' then + -- valid read fifo_to_apl_read <= '1'; - if reg_APL_TYP_OUT = TYPE_TRM and fifo_to_apl_empty = '1' then -- transfer completely finished + if reg_APL_TYP_OUT = TYPE_TRM and (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then -- transfer completely finished next_state <= IDLE; - elsif reg_APL_TYP_OUT = TYPE_TRM and fifo_to_apl_empty = '0' then +-- elsif reg_APL_TYP_OUT = TYPE_TRM and fifo_to_apl_empty = '0' then -- something wrong - next_state <= MY_ERROR; +-- next_state <= MY_ERROR; end if; end if; -- MISSING: SEQNR check @@ -439,8 +455,8 @@ end generate CHECK_BUFFER; combined_header(13 downto 12) <= (others => '0'); -- VERS combined_header(11 downto 4) <= sequence_counter; -- SEQNR combined_header(3 downto 0) <= APL_DTYPE_IN; - combined_trailer(F1_POSITION) <= APL_ERROR_PATTERN(31 downto 16); - combined_trailer(F2_POSITION) <= APL_ERROR_PATTERN(15 downto 0); + combined_trailer(F1_POSITION) <= APL_ERROR_PATTERN_IN(31 downto 16); + combined_trailer(F2_POSITION) <= APL_ERROR_PATTERN_IN(15 downto 0); combined_trailer(15 downto 14) <= (others => '0'); -- res. combined_trailer(13 downto 12) <= (others => '0'); -- VERS combined_trailer(11 downto 4) <= sequence_counter; -- SEQNR @@ -454,18 +470,29 @@ end generate CHECK_BUFFER; current_state = SEND_HEADER or current_state = RUNNING) else '0'; - + APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing + INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT; -- registered output for -- internal port INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT; + INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT; + -- connect receiver fifo_to_apl_data_in <= INT_REPLY_DATA_IN; - + reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; + reg_APL_DATA_OUT <= next_APL_DATA_OUT; + reg_APL_TYP_OUT <= next_APL_TYP_OUT; + APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; + APL_DATA_OUT <= reg_APL_DATA_OUT; + APL_TYP_OUT <= reg_APL_TYP_OUT; + APL_RUN_OUT <= '0' when (current_state = IDLE) + else '1'; + APL_SEQNR_OUT <= sequence_counter; -- generate the sequence counter -- combinatorial part - SEQNR_COMB : process(sequence_counter) + SEQNR_COMB : process(sequence_counter, current_state, next_state) begin if current_state = WAITING and next_state = IDLE then next_sequence_counter <= sequence_counter+1; @@ -481,6 +508,10 @@ CLK_REG: process(CLK) sequence_counter <= (others => '0'); reg_INT_INIT_DATA_OUT <= (others => '0'); reg_INT_INIT_DATAREADY_OUT <= '0'; + reg_INT_REPLY_READ_OUT <= '0'; +-- reg_APL_DATAREADY_OUT <= '0'; +-- reg_APL_DATA_OUT <= (others => '0'); +-- reg_APL_TYP_OUT <= (others => '0'); current_state <= IDLE; tb_current_state <= IDLE; registered_header <= (others => '0'); @@ -491,16 +522,25 @@ CLK_REG: process(CLK) sequence_counter <= next_sequence_counter; reg_INT_INIT_DATA_OUT <= next_INT_INIT_DATA_OUT; reg_INT_INIT_DATAREADY_OUT <= next_INT_INIT_DATAREADY_OUT; + reg_INT_REPLY_READ_OUT <= next_INT_REPLY_READ_OUT; +-- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; +-- reg_APL_DATA_OUT <= next_APL_DATA_OUT; +-- reg_APL_TYP_OUT <= next_APL_TYP_OUT; current_state <= next_state; tb_current_state <= tb_next_state; registered_header <= next_registered_header; registered_trailer <= next_registered_trailer; tb_registered_trailer <= tb_next_registered_trailer; tb_registered_target <= tb_next_registered_target; + else sequence_counter <= sequence_counter; reg_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT; reg_INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT; + reg_INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT; +-- reg_APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; +-- reg_APL_DATA_OUT <= reg_APL_DATA_OUT; +-- reg_APL_TYP_OUT <= reg_APL_TYP_OUT; current_state <= current_state; tb_current_state <= tb_current_state; registered_header <= registered_header; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 1b088b8..1bdc263 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -27,7 +27,7 @@ package trb_net_std is subtype F3_POSITION is integer range 15 downto 0; subtype DWORD_POSITION is integer range 47 downto 0; - subtype SOURCE_POSITION is integer range 15 downto 0; + subtype SOURCE_POSITION is integer range 47 downto 32; subtype TARGET_POSITION is integer range 31 downto 16; constant ILLEGAL_ADRESS : std_logic_vector(15 downto 0) := x"0000";