From: Michael Boehmer Date: Tue, 5 Jul 2022 10:46:05 +0000 (+0200) Subject: PSCB / PSCD in raw mode, correct LED assignment X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e50626d9402440cbec9bc6ec86b851019000d4be;p=trb3sc.git PSCB / PSCD in raw mode, correct LED assignment --- diff --git a/gbe_hub/trb3sc_gbe_hub.lpf b/gbe_hub/trb3sc_gbe_hub.lpf index 36c1877..e820fc0 100644 --- a/gbe_hub/trb3sc_gbe_hub.lpf +++ b/gbe_hub/trb3sc_gbe_hub.lpf @@ -1,13 +1,19 @@ # locate the PCS blocks -LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; -#LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSC"; +LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSD"; + +LOCATE COMP "THE_GBE_MED_RAW_PCSC/gbe_serdes/PCSD_INST" SITE "PCSC"; +LOCATE COMP "THE_GBE_MED_RAW_PCSB/gbe_serdes/PCSD_INST" SITE "PCSB"; + +# main frequencies FREQUENCY NET "CLK_CORE_PCLK_c" 200.0 MHz; FREQUENCY NET "CLK_SUPPL_PCLK_c" 125.0 MHz; FREQUENCY NET "clk_sys" 100.0 MHz; FREQUENCY NET "GBE/clk_125_rx_from_pcs[0]" 125.0 MHz; +################################################################################################## + # primary nets #USE PRIMARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[0]"; diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index cd3897e..5993454 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -118,7 +118,18 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal gsc_busy : std_logic; signal status : std_logic_vector(15 downto 0); - + + ---------------------------------------------------------------- + signal tx_pll_lol_i : std_logic; + signal tx_pll_lol_c_i : std_logic; + signal tx_pll_lol_d_i : std_logic; + signal tx_clk_avail_i : std_logic; + signal tx_pcs_rst_i : std_logic; +-- signal sync_tx_quad_i : std_logic; + signal link_tx_ready_i : std_logic; +-- signal link_rx_ready_i : std_logic_vector(3 downto 0); + signal status_raw : std_logic_vector(4 * 32 - 1 downto 0); + begin --------------------------------------------------------------------------- @@ -149,13 +160,11 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- B0, B1, B2, B3 downlink on hub addon -- C0, C1, C2, C3 downlink on hub addon -- D0, D1 downlink on TRB3sc, (D2, D3 unused) --- needs PCSSW = 11100100 -- -- SFP: D0 uplink, (D1, D2, D3 unused) -- A0, A1, A2, A3 downlink on backplane --- B3 downlink on TRB3sc, (B0, B1, B2 unused) +-- B0, B1, B2, B3 unused -- C0, C1, C2, C3 unused --- needs PCSS" = 01001110 --------------------------------------------------------------------------- -- Serdes Select @@ -163,8 +172,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler PCSSW_ENSMB <= '0'; PCSSW_EQ <= x"0"; PCSSW_PE <= x"F"; --- PCSSW <= "11100100"; -- SFP2 on D1, Addon on B3 - PCSSW <= "01001110"; -- SFP2 on B3, AddOn on D1 + PCSSW <= "11100100"; -- SFP2 on D1, Addon on B3 +-- PCSSW <= "01001110"; -- SFP2 on B3, AddOn on D1 --------------------------------------------------------------------------- -- PCSD as test point (SFP2) @@ -360,22 +369,190 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_RED <= not status(2); --'0'; LED_YELLOW <= not status(5); --'0'; -GEN_HUB_LEDS : for i in 0 to 6 generate - LED_HUB_LINKOK(i+1) <= not '0'; - LED_HUB_TX(i+1) <= not '0'; - LED_HUB_RX(i+1) <= not '0'; -end generate; +--GEN_HUB_LEDS : for i in 0 to 6 generate +-- LED_HUB_LINKOK(i+1) <= not '0'; +-- LED_HUB_TX(i+1) <= not '0'; +-- LED_HUB_RX(i+1) <= not '0'; +--end generate; + + + LED_HUB_LINKOK(1) <= not status_raw(10 * 8 + 2); --'0'; -- C2 + LED_HUB_TX(1) <= not status_raw(10 * 8 + 5); --'0'; + LED_HUB_RX(1) <= not '0'; + + LED_HUB_LINKOK(2) <= not status_raw(11 * 8 + 2); --'0'; -- C3 + LED_HUB_TX(2) <= not status_raw(11 * 8 + 5); --'0'; + LED_HUB_RX(2) <= not '0'; + + LED_HUB_LINKOK(3) <= not status_raw(8 * 8 + 2); --'0'; -- C0 + LED_HUB_TX(3) <= not status_raw(8 * 8 + 5); --'0'; + LED_HUB_RX(3) <= not '0'; - LED_HUB_LINKOK(8) <= not '0'; + LED_HUB_LINKOK(4) <= not status_raw(9 * 8 + 2); --'0'; -- C1 + LED_HUB_TX(4) <= not status_raw(9 * 8 + 5); --'0'; + LED_HUB_RX(4) <= not '0'; + + LED_HUB_LINKOK(5) <= not status_raw(4 * 8 + 2); --'0'; -- B0 + LED_HUB_TX(5) <= not status_raw(4 * 8 + 5); --'0'; + LED_HUB_RX(5) <= not '0'; + + LED_HUB_LINKOK(6) <= not status_raw(5 * 8 + 2); --'0'; -- B1 + LED_HUB_TX(6) <= not status_raw(5 * 8 + 5); --'0'; + LED_HUB_RX(6) <= not '0'; + + LED_HUB_LINKOK(7) <= not '0'; -- B2 + LED_HUB_TX(7) <= not '0'; + LED_HUB_RX(7) <= not '0'; + + LED_HUB_LINKOK(8) <= not '0'; -- B3 LED_HUB_TX(8) <= not '0'; LED_HUB_RX(8) <= not '0'; - LED_SFP_GREEN(0) <= not '0'; + + LED_SFP_GREEN(0) <= not '0'; -- D0 LED_SFP_RED(0) <= not '0'; - LED_SFP_GREEN(1) <= not '0'; + LED_SFP_GREEN(1) <= not '0'; -- D1 LED_SFP_RED(1) <= not '0'; LED_WHITE(1) <= not additional_reg(31); --'0'; LED_WHITE(0) <= not status(8); --'0'; + +--------------------------------------------------------------------------- +-- PCSC is four ports downlink +--------------------------------------------------------------------------- + THE_GBE_MED_RAW_PCSC: entity gbe_med_raw + generic map( + LINKS_ACTIVE => "1111" + ) + port map( + RESET => reset_i, + GSR_N => GSR_N, + CLK_SYS => clk_sys, + CLK_125 => CLK_SUPPL_PCLK, + CLK_125_RX => open, + -- MAC status and config + MAC_READY_CONF_OUT => open, + MAC_RECONF_IN => (others => '0'), + MAC_AN_READY_OUT => open, + -- MAC data interface + MAC_FIFOAVAIL_IN => (others => '0'), + MAC_FIFOEOF_IN => (others => '0'), + MAC_FIFOEMPTY_IN => (others => '0'), + MAC_RX_FIFOFULL_IN => (others => '0'), + -- MAC TX interface + MAC_TX_DATA_IN => (others => '0'), + MAC_TX_READ_OUT => open, + MAC_TX_DISCRFRM_OUT => open, + MAC_TX_STAT_EN_OUT => open, + MAC_TX_STATS_OUT => open, + MAC_TX_DONE_OUT => open, + -- MAC RX interface + MAC_RX_FIFO_ERR_OUT => open, + MAC_RX_STATS_OUT => open, + MAC_RX_DATA_OUT => open, + MAC_RX_WRITE_OUT => open, + MAC_RX_STAT_EN_OUT => open, + MAC_RX_EOF_OUT => open, + MAC_RX_ERROR_OUT => open, + -- SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(3), + SD_PRSNT_N_IN(1) => HUB_MOD0(4), + SD_PRSNT_N_IN(2) => HUB_MOD0(1), + SD_PRSNT_N_IN(3) => HUB_MOD0(2), + SD_LOS_IN(0) => HUB_LOS(3), + SD_LOS_IN(1) => HUB_LOS(4), + SD_LOS_IN(2) => HUB_LOS(1), + SD_LOS_IN(3) => HUB_LOS(2), + SD_TXDIS_OUT(0) => HUB_TXDIS(3), + SD_TXDIS_OUT(1) => HUB_TXDIS(4), + SD_TXDIS_OUT(2) => HUB_TXDIS(1), + SD_TXDIS_OUT(3) => HUB_TXDIS(2), + -- SerDes control + TX_PLOL_LOL_OUT => tx_pll_lol_c_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + RX_LINK_READY_OUT => open, + TX_LINK_READY_IN => open, + -- Debug + STATUS_OUT => status_raw(3 * 32 - 1 downto 2 * 32), + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- PCSB is two ports downlink (6port hub addon) or four ports downlink (8port hub addon) +--------------------------------------------------------------------------- + THE_GBE_MED_RAW_PCSB: entity gbe_med_raw + generic map( + LINKS_ACTIVE => "0011" + ) + port map( + RESET => reset_i, + GSR_N => GSR_N, + CLK_SYS => clk_sys, + CLK_125 => CLK_SUPPL_PCLK, + CLK_125_RX => open, + -- MAC status and config + MAC_READY_CONF_OUT => open, + MAC_RECONF_IN => (others => '0'), + MAC_AN_READY_OUT => open, + -- MAC data interface + MAC_FIFOAVAIL_IN => (others => '0'), + MAC_FIFOEOF_IN => (others => '0'), + MAC_FIFOEMPTY_IN => (others => '0'), + MAC_RX_FIFOFULL_IN => (others => '0'), + -- MAC TX interface + MAC_TX_DATA_IN => (others => '0'), + MAC_TX_READ_OUT => open, + MAC_TX_DISCRFRM_OUT => open, + MAC_TX_STAT_EN_OUT => open, + MAC_TX_STATS_OUT => open, + MAC_TX_DONE_OUT => open, + -- MAC RX interface + MAC_RX_FIFO_ERR_OUT => open, + MAC_RX_STATS_OUT => open, + MAC_RX_DATA_OUT => open, + MAC_RX_WRITE_OUT => open, + MAC_RX_STAT_EN_OUT => open, + MAC_RX_EOF_OUT => open, + MAC_RX_ERROR_OUT => open, + -- SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => '1', --HUB_MOD0(7), + SD_PRSNT_N_IN(3) => '1', --HUB_MOD0(8), + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => '1', --HUB_LOS(7), + SD_LOS_IN(3) => '1', --HUB_LOS(8), + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => open, --HUB_TXDIS(7), + SD_TXDIS_OUT(3) => open, --HUB_TXDIS(8), + -- SerDes control + TX_PLOL_LOL_OUT => tx_pll_lol_d_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + RX_LINK_READY_OUT => open, + TX_LINK_READY_IN => open, + -- Debug + STATUS_OUT => status_raw(2 * 32 - 1 downto 1 * 32), + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- RSL for TX of SerDes, based on extRSL logic +--------------------------------------------------------------------------- + THE_MAIN_TX_RST: main_tx_reset_RS + port map ( + CLEAR => clear, + CLK_REF => CLK_SUPPL_PCLK, + TX_PLL_LOL_IN => tx_pll_lol_i, + TX_CLOCK_AVAIL_IN => '1', -- not needed here + TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, + SYNC_TX_QUAD_OUT => open, --not needed here + LINK_TX_READY_OUT => link_tx_ready_i, + STATE_OUT => open + ); + + tx_pll_lol_i <= tx_pll_lol_c_i or tx_pll_lol_d_i; + end architecture;