From: Jan Michel Date: Fri, 30 Jan 2015 17:34:12 +0000 (+0100) Subject: my current status - source not working properly X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e67231aaab2da2df40a4205c6592dda28136d1d9;p=soda.git my current status - source not working properly --- diff --git a/.gitignore b/.gitignore index 4274ccc..1a5ec1a 100644 --- a/.gitignore +++ b/.gitignore @@ -46,4 +46,12 @@ syntmp synwork dm backup - +soda_hub +soda_client +soda_source +.kateproject.d +.floorplanner.ini +.setting.ini +.run_manager.ini +._Real_._Math_.vhd +.kateproject diff --git a/code/ip/serdes_4_sync_downstream.ipx b/code/ip/serdes_4_sync_downstream.ipx index bb723b0..2b7f836 100644 --- a/code/ip/serdes_4_sync_downstream.ipx +++ b/code/ip/serdes_4_sync_downstream.ipx @@ -1,11 +1,8 @@ - + - - - - - - + + + diff --git a/code/ip/serdes_sync_source_downstream.ipx b/code/ip/serdes_sync_source_downstream.ipx index 13ca784..02ac8ed 100644 --- a/code/ip/serdes_sync_source_downstream.ipx +++ b/code/ip/serdes_sync_source_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_sync_source_downstream.lpc b/code/ip/serdes_sync_source_downstream.lpc index 6a53c07..d013d9e 100644 --- a/code/ip/serdes_sync_source_downstream.lpc +++ b/code/ip/serdes_sync_source_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_source_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=05/13/2014 -Time=08:58:11 +Date=01/30/2015 +Time=17:46:06 [Parameters] Verilog=0 @@ -190,7 +190,7 @@ _cc_match_mode0=1 _cc_match_mode1=1 _cc_match_mode2=1 _cc_match_mode3=1 -_k00=00 +_k00=01 _k01=00 _k02=00 _k03=00 diff --git a/code/ip/serdes_sync_source_downstream.txt b/code/ip/serdes_sync_source_downstream.txt new file mode 100644 index 0000000..cf095d4 --- /dev/null +++ b/code/ip/serdes_sync_source_downstream.txt @@ -0,0 +1,58 @@ +# This file is used by the simulation model as well as the ispLEVER bitstream +# generation process to automatically initialize the PCSD quad to the mode +# selected in the IPexpress. This file is expected to be modified by the +# end user to adjust the PCSD quad to the final design requirements. + +DEVICE_NAME "LFE3-150EA" +CH0_PROTOCOL "G8B10B" +CH0_MODE "RXTX" +CH1_MODE "DISABLED" +CH2_MODE "DISABLED" +CH3_MODE "DISABLED" +CH0_CDR_SRC "REFCLK_CORE" +PLL_SRC "REFCLK_CORE" +TX_DATARATE_RANGE "MEDHIGH" +CH0_RX_DATARATE_RANGE "MEDHIGH" +REFCK_MULT "10X" +#REFCLK_RATE 200 +CH0_RX_DATA_RATE "FULL" +CH0_TX_DATA_RATE "FULL" +CH0_TX_DATA_WIDTH "8" +CH0_RX_DATA_WIDTH "8" +CH0_TX_FIFO "DISABLED" +CH0_RX_FIFO "ENABLED" +CH0_TDRV "0" +#CH0_TX_FICLK_RATE 200 +#CH0_RXREFCLK_RATE "200" +#CH0_RX_FICLK_RATE 200 +CH0_TX_PRE "DISABLED" +CH0_RTERM_TX "50" +CH0_RX_EQ "DISABLED" +CH0_RTERM_RX "50" +CH0_RX_DCC "DC" +CH0_LOS_THRESHOLD_LO "2" +PLL_TERM "50" +PLL_DCC "AC" +PLL_LOL_SET "0" +CH0_TX_SB "DISABLED" +CH0_RX_SB "DISABLED" +CH0_TX_8B10B "ENABLED" +CH0_RX_8B10B "ENABLED" +CH0_COMMA_A "1100000101" +CH0_COMMA_B "0011111010" +CH0_COMMA_M "1111111100" +CH0_RXWA "ENABLED" +CH0_ILSM "ENABLED" +CH0_CTC "DISABLED" +CH0_CC_MATCH4 "0100011100" +CH0_CC_MATCH_MODE "1" +CH0_CC_MIN_IPG "3" +CCHMARK "9" +CCLMARK "7" +CH0_SSLB "DISABLED" +CH0_SPLBPORTS "DISABLED" +CH0_PCSLBPORTS "DISABLED" +INT_ALL "DISABLED" +QD_REFCK2CORE "ENABLED" + + diff --git a/code/ip/serdes_sync_source_downstream.vhd b/code/ip/serdes_sync_source_downstream.vhd index e0c6a6c..0c3024f 100644 --- a/code/ip/serdes_sync_source_downstream.vhd +++ b/code/ip/serdes_sync_source_downstream.vhd @@ -1534,6 +1534,7 @@ entity serdes_sync_source_downstream is GENERIC (USER_CONFIG_FILE : String := "serdes_sync_source_downstream.txt"); port ( ------------------ +-- CH0 -- hdinp_ch0, hdinn_ch0 : in std_logic; hdoutp_ch0, hdoutn_ch0 : out std_logic; sci_sel_ch0 : in std_logic; @@ -1564,6 +1565,9 @@ entity serdes_sync_source_downstream is rx_cdr_lol_ch0_s : out std_logic; tx_div2_mode_ch0_c : in std_logic; rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- ---- Miscillaneous ports sci_wrdata : in std_logic_vector (7 downto 0); sci_addr : in std_logic_vector (5 downto 0); diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index e11814a..9e508ba 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -1,543 +1,543 @@ ---Media interface for Lattice ECP3 using PCS at 2GHz - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.med_sync_define.all; -use work.soda_components.all; - -entity med_ecp3_sfp_sync_down is - generic( SERDES_NUM : integer range 0 to 3 := 0; - IS_SYNC_SLAVE : integer := c_NO); --select slave mode - port( - OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - --Internal Connection TX - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic := '0'; - --Internal Connection RX - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); - MED_DATAREADY_OUT : out std_logic := '0'; - MED_READ_IN : in std_logic; - RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz - RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz - TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz - TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz - - --Sync operation - RX_DLM : out std_logic := '0'; - RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; - TX_DLM : in std_logic := '0'; - TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; - TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! - LINK_PHASE_OUT : out std_logic := '0'; --PL! - - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; --not used - SD_REFCLK_N_IN : in std_logic; --not used - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable - --Control Interface - SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); - SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); - SCI_READ : in std_logic := '0'; - SCI_WRITE : in std_logic := '0'; - SCI_ACK : out std_logic := '0'; - SCI_NACK : out std_logic := '0'; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') - ); -end entity; - - -architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is - - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture is "media_downlink_group"; - attribute syn_sharing : string; - attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off"; - - -component DCS --- synthesis translate_off -generic - ( -DCSMODE : string :=“POS” -); --- synthesis translate_on -port ( - CLK0 :in std_logic ; - CLK1 :in std_logic ; - SEL :in std_logic ; - DCSOUT :out std_logic) ; -end component; - - ---signal clk_200_i : std_logic; ---signal clk_200_internal : std_logic; -signal clk_200_osc : std_logic; -signal clk_100_osc : std_logic; -signal rx_full_clk_ch0 : std_logic; -signal rx_half_clk_ch0 : std_logic; -signal tx_full_clk_ch0 : std_logic; -signal tx_half_clk_ch0 : std_logic; - -signal tx_data : std_logic_vector(7 downto 0); -signal tx_k : std_logic; -signal rx_data : std_logic_vector(7 downto 0); -signal rx_k : std_logic; -signal rx_error : std_logic; - -signal rst_n : std_logic; -signal rst : std_logic; -- PL! -signal rx_serdes_rst : std_logic; -signal tx_serdes_rst : std_logic; -signal tx_pcs_rst : std_logic; -signal rx_pcs_rst : std_logic; -signal rst_qd : std_logic; -signal serdes_rst_qd : std_logic; -signal sd_los_i : std_logic; --PL! - -signal rx_los_low : std_logic; -signal lsm_status : std_logic; -signal rx_cdr_lol : std_logic; -signal tx_pll_lol : std_logic; - -signal sci_ch_i : std_logic_vector(3 downto 0); -signal sci_qd_i : std_logic; -signal sci_reg_i : std_logic; -signal sci_addr_i : std_logic_vector(8 downto 0); -signal sci_data_in_i : std_logic_vector(7 downto 0); -signal sci_data_out_i : std_logic_vector(7 downto 0); -signal sci_read_i : std_logic; -signal sci_write_i : std_logic; -signal sci_write_shift_i : std_logic_vector(2 downto 0); -signal sci_read_shift_i : std_logic_vector(2 downto 0); - --- fix signal names for constraining -attribute syn_preserve : boolean;-- -attribute syn_keep : boolean;-- -attribute syn_preserve of sci_ch_i : signal is true;-- -attribute syn_keep of sci_ch_i : signal is true;-- -attribute syn_preserve of sci_qd_i : signal is true;-- -attribute syn_keep of sci_qd_i : signal is true;-- -attribute syn_preserve of sci_reg_i : signal is true;-- -attribute syn_keep of sci_reg_i : signal is true;-- -attribute syn_preserve of sci_addr_i : signal is true;-- -attribute syn_keep of sci_addr_i : signal is true;-- -attribute syn_preserve of sci_data_in_i : signal is true;-- -attribute syn_keep of sci_data_in_i : signal is true;-- -attribute syn_preserve of sci_data_out_i : signal is true;-- -attribute syn_keep of sci_data_out_i : signal is true;-- -attribute syn_preserve of sci_read_i : signal is true;-- -attribute syn_keep of sci_read_i : signal is true;-- -attribute syn_preserve of sci_write_i : signal is true;-- -attribute syn_keep of sci_write_i : signal is true;-- -attribute syn_preserve of sci_write_shift_i : signal is true;-- -attribute syn_keep of sci_write_shift_i : signal is true;-- -attribute syn_preserve of sci_read_shift_i : signal is true;-- -attribute syn_keep of sci_read_shift_i : signal is true;-- - -signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; -signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; -signal tx_allow : std_logic; -signal rx_allow : std_logic; -signal tx_allow_q : std_logic; -signal rx_allow_q : std_logic; -signal link_phase_S : std_logic; --PL! -signal request_retr_i : std_logic; -signal start_retr_i : std_logic; -signal request_retr_position_i : std_logic_vector(7 downto 0); -signal start_retr_position_i : std_logic_vector(7 downto 0); -signal send_link_reset_i : std_logic; -signal make_link_reset_i : std_logic; -signal got_link_ready_i : std_logic; -signal internal_make_link_reset_out : std_logic; - -attribute syn_preserve of wa_position : signal is true;-- -attribute syn_keep of wa_position : signal is true;-- -attribute syn_preserve of wa_position_rx : signal is true;-- -attribute syn_keep of wa_position_rx : signal is true;-- - -signal stat_rx_control_i : std_logic_vector(31 downto 0); -signal stat_tx_control_i : std_logic_vector(31 downto 0); -signal debug_rx_control_i : std_logic_vector(31 downto 0); -signal debug_tx_control_i : std_logic_vector(31 downto 0); -signal rx_fsm_state : std_logic_vector(3 downto 0); -signal tx_fsm_state : std_logic_vector(3 downto 0); -signal debug_reg : std_logic_vector(63 downto 0); - -type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); -signal sci_state : sci_ctrl; -signal sci_timer : unsigned(12 downto 0) := (others => '0'); -signal start_timer : unsigned(18 downto 0) := (others => '0'); ---signal watchdog_timer : unsigned(20 downto 0) := (others => '0'); ---signal watchdog_trigger : std_logic :='0'; - -begin - -clk_200_osc <= OSCCLK; -clk_100_osc <= SYSCLK; - -RX_HALF_CLK_OUT <= rx_half_clk_ch0; -RX_FULL_CLK_OUT <= rx_full_clk_ch0; -TX_HALF_CLK_OUT <= tx_half_clk_ch0; -TX_FULL_CLK_OUT <= tx_full_clk_ch0; - -SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready - - ---rst_n <= not CLEAR; PL! ---rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); ---rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); -rst_n <= not(CLEAR or internal_make_link_reset_out); -rst <= (CLEAR or internal_make_link_reset_out); - -------------------------------------------------- --- Serdes -------------------------------------------------- -THE_SERDES : entity work.serdes_sync_source_downstream - port map( - hdinp_ch0 => SD_RXD_P_IN, - hdinn_ch0 => SD_RXD_N_IN, - hdoutp_ch0 => SD_TXD_P_OUT, - hdoutn_ch0 => SD_TXD_N_OUT, - rxiclk_ch0 => tx_full_clk_ch0, -- read fifo is no longer present! PL! - txiclk_ch0 => tx_full_clk_ch0, - rx_full_clk_ch0 => rx_full_clk_ch0, - rx_half_clk_ch0 => rx_half_clk_ch0, - tx_full_clk_ch0 => tx_full_clk_ch0, - tx_half_clk_ch0 => tx_half_clk_ch0, - fpga_rxrefclk_ch0 => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT - txdata_ch0 => tx_data, - tx_k_ch0 => tx_k, - tx_force_disp_ch0 => '0', - tx_disp_sel_ch0 => '0', - rxdata_ch0 => rx_data, - rx_k_ch0 => rx_k, - rx_disp_err_ch0 => open, - rx_cv_err_ch0 => rx_error, - rx_serdes_rst_ch0_c => rx_serdes_rst, - sb_felb_ch0_c => '0', - sb_felb_rst_ch0_c => '0', - tx_pcs_rst_ch0_c => tx_pcs_rst, - tx_pwrup_ch0_c => '1', - rx_pcs_rst_ch0_c => rx_pcs_rst, - rx_pwrup_ch0_c => '1', - rx_los_low_ch0_s => rx_los_low, - lsm_status_ch0_s => lsm_status, - rx_cdr_lol_ch0_s => rx_cdr_lol, - tx_div2_mode_ch0_c => '0', - rx_div2_mode_ch0_c => '0', - refclk2fpga => open, --refclk2core_S, - - SCI_WRDATA => sci_data_in_i, - SCI_RDDATA => sci_data_out_i, - SCI_ADDR => sci_addr_i(5 downto 0), - SCI_SEL_QUAD => sci_qd_i, - SCI_SEL_CH0 => sci_ch_i(0), - SCI_RD => sci_read_i, - SCI_WRN => sci_write_i, - - fpga_txrefclk => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT - tx_serdes_rst_c => tx_serdes_rst, - tx_pll_lol_qd_s => tx_pll_lol, - rst_qd_c => rst_qd, - serdes_rst_qd_c => serdes_rst_qd - - ); - -------------------------------------------------- --- Reset FSM & Link states -------------------------------------------------- -THE_RX_FSM : rx_reset_fsm - port map( - RST_N => rst_n, - RX_REFCLK => clk_200_osc, --rx_full_clk_ch0, - TX_PLL_LOL_QD_S => tx_pll_lol, - RX_SERDES_RST_CH_C => rx_serdes_rst, - RX_CDR_LOL_CH_S => rx_cdr_lol, - RX_LOS_LOW_CH_S => rx_los_low, - RX_PCS_RST_CH_C => rx_pcs_rst, - WA_POSITION => wa_position_rx(3 downto 0), - STATE_OUT => rx_fsm_state - ); - -THE_TX_FSM : tx_reset_fsm - port map( - RST_N => rst_n, - TX_REFCLK => clk_200_osc, - TX_PLL_LOL_QD_S => tx_pll_lol, - RST_QD_C => rst_qd, - TX_PCS_RST_CH_C => tx_pcs_rst, - STATE_OUT => tx_fsm_state - ); - --- Master does not do bit-locking -wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000"; - - ---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable -PROC_ALLOW : process begin - wait until rising_edge(clk_200_osc); --clk_200_i); - if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then - rx_allow <= '1'; - else - rx_allow <= '0'; - end if; - if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then - tx_allow <= '1'; - else - tx_allow <= '0'; - end if; -end process; - -rx_allow_q <= rx_allow when rising_edge(clk_100_osc); -tx_allow_q <= tx_allow when rising_edge(clk_100_osc); - - --- start_timer begins when the rx-link is ready; i.e.: there is a working link. --- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high. --- This gives a slave on the other side time to start-up --- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset -PROC_START_TIMER : process(clk_200_osc) --clk_200_i) -begin - if rising_edge(clk_200_osc) then - if got_link_ready_i = '1' then - if start_timer(start_timer'left) = '0' then - start_timer <= start_timer + 1; - end if; - else - start_timer <= (others => '0'); - end if; - end if; +--Media interface for Lattice ECP3 using PCS at 2GHz + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; +use work.soda_components.all; + +entity med_ecp3_sfp_sync_down is + generic( SERDES_NUM : integer range 0 to 3 := 0; + IS_SYNC_SLAVE : integer := c_NO); --select slave mode + port( + OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --Internal Connection TX + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic := '0'; + --Internal Connection RX + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); + MED_DATAREADY_OUT : out std_logic := '0'; + MED_READ_IN : in std_logic; + RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz + TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz + + --Sync operation + RX_DLM : out std_logic := '0'; + RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; + TX_DLM : in std_logic := '0'; + TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; + TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! + LINK_PHASE_OUT : out std_logic := '0'; --PL! + + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; --not used + SD_REFCLK_N_IN : in std_logic; --not used + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; + + +architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture is "media_downlink_group"; + attribute syn_sharing : string; + attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off"; + + +component DCS +-- synthesis translate_off +generic + ( +DCSMODE : string :=“POS” +); +-- synthesis translate_on +port ( + CLK0 :in std_logic ; + CLK1 :in std_logic ; + SEL :in std_logic ; + DCSOUT :out std_logic) ; +end component; + + +--signal clk_200_i : std_logic; +--signal clk_200_internal : std_logic; +signal clk_200_osc : std_logic; +signal clk_100_osc : std_logic; +signal rx_full_clk_ch0 : std_logic; +signal rx_half_clk_ch0 : std_logic; +signal tx_full_clk_ch0 : std_logic; +signal tx_half_clk_ch0 : std_logic; + +signal tx_data : std_logic_vector(7 downto 0); +signal tx_k : std_logic; +signal rx_data : std_logic_vector(7 downto 0); +signal rx_k : std_logic; +signal rx_error : std_logic; + +signal rst_n : std_logic; +signal rst : std_logic; -- PL! +signal rx_serdes_rst : std_logic; +signal tx_serdes_rst : std_logic; +signal tx_pcs_rst : std_logic; +signal rx_pcs_rst : std_logic; +signal rst_qd : std_logic; +signal serdes_rst_qd : std_logic; +signal sd_los_i : std_logic; --PL! + +signal rx_los_low : std_logic; +signal lsm_status : std_logic; +signal rx_cdr_lol : std_logic; +signal tx_pll_lol : std_logic; + +signal sci_ch_i : std_logic_vector(3 downto 0); +signal sci_qd_i : std_logic; +signal sci_reg_i : std_logic; +signal sci_addr_i : std_logic_vector(8 downto 0); +signal sci_data_in_i : std_logic_vector(7 downto 0); +signal sci_data_out_i : std_logic_vector(7 downto 0); +signal sci_read_i : std_logic; +signal sci_write_i : std_logic; +signal sci_write_shift_i : std_logic_vector(2 downto 0); +signal sci_read_shift_i : std_logic_vector(2 downto 0); + +-- fix signal names for constraining +attribute syn_preserve : boolean;-- +attribute syn_keep : boolean;-- +attribute syn_preserve of sci_ch_i : signal is true;-- +attribute syn_keep of sci_ch_i : signal is true;-- +attribute syn_preserve of sci_qd_i : signal is true;-- +attribute syn_keep of sci_qd_i : signal is true;-- +attribute syn_preserve of sci_reg_i : signal is true;-- +attribute syn_keep of sci_reg_i : signal is true;-- +attribute syn_preserve of sci_addr_i : signal is true;-- +attribute syn_keep of sci_addr_i : signal is true;-- +attribute syn_preserve of sci_data_in_i : signal is true;-- +attribute syn_keep of sci_data_in_i : signal is true;-- +attribute syn_preserve of sci_data_out_i : signal is true;-- +attribute syn_keep of sci_data_out_i : signal is true;-- +attribute syn_preserve of sci_read_i : signal is true;-- +attribute syn_keep of sci_read_i : signal is true;-- +attribute syn_preserve of sci_write_i : signal is true;-- +attribute syn_keep of sci_write_i : signal is true;-- +attribute syn_preserve of sci_write_shift_i : signal is true;-- +attribute syn_keep of sci_write_shift_i : signal is true;-- +attribute syn_preserve of sci_read_shift_i : signal is true;-- +attribute syn_keep of sci_read_shift_i : signal is true;-- + +signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; +signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; +signal tx_allow : std_logic; +signal rx_allow : std_logic; +signal tx_allow_q : std_logic; +signal rx_allow_q : std_logic; +signal link_phase_S : std_logic; --PL! +signal request_retr_i : std_logic; +signal start_retr_i : std_logic; +signal request_retr_position_i : std_logic_vector(7 downto 0); +signal start_retr_position_i : std_logic_vector(7 downto 0); +signal send_link_reset_i : std_logic; +signal make_link_reset_i : std_logic; +signal got_link_ready_i : std_logic; +signal internal_make_link_reset_out : std_logic; + +attribute syn_preserve of wa_position : signal is true;-- +attribute syn_keep of wa_position : signal is true;-- +attribute syn_preserve of wa_position_rx : signal is true;-- +attribute syn_keep of wa_position_rx : signal is true;-- + +signal stat_rx_control_i : std_logic_vector(31 downto 0); +signal stat_tx_control_i : std_logic_vector(31 downto 0); +signal debug_rx_control_i : std_logic_vector(31 downto 0); +signal debug_tx_control_i : std_logic_vector(31 downto 0); +signal rx_fsm_state : std_logic_vector(3 downto 0); +signal tx_fsm_state : std_logic_vector(3 downto 0); +signal debug_reg : std_logic_vector(63 downto 0); + +type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); +signal sci_state : sci_ctrl; +signal sci_timer : unsigned(12 downto 0) := (others => '0'); +signal start_timer : unsigned(18 downto 0) := (others => '0'); +--signal watchdog_timer : unsigned(20 downto 0) := (others => '0'); +--signal watchdog_trigger : std_logic :='0'; + +begin + +clk_200_osc <= OSCCLK; +clk_100_osc <= SYSCLK; + +RX_HALF_CLK_OUT <= rx_half_clk_ch0; +RX_FULL_CLK_OUT <= rx_full_clk_ch0; +TX_HALF_CLK_OUT <= tx_half_clk_ch0; +TX_FULL_CLK_OUT <= tx_full_clk_ch0; + +SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready + + +--rst_n <= not CLEAR; PL! +--rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); +--rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); +rst_n <= not(CLEAR or internal_make_link_reset_out); +rst <= (CLEAR or internal_make_link_reset_out); + +------------------------------------------------- +-- Serdes +------------------------------------------------- +THE_SERDES : entity work.serdes_sync_source_downstream + port map( + hdinp_ch0 => SD_RXD_P_IN, + hdinn_ch0 => SD_RXD_N_IN, + hdoutp_ch0 => SD_TXD_P_OUT, + hdoutn_ch0 => SD_TXD_N_OUT, + rxiclk_ch0 => tx_full_clk_ch0, -- read fifo is no longer present! PL! + txiclk_ch0 => tx_full_clk_ch0, + rx_full_clk_ch0 => rx_full_clk_ch0, + rx_half_clk_ch0 => rx_half_clk_ch0, + tx_full_clk_ch0 => tx_full_clk_ch0, + tx_half_clk_ch0 => tx_half_clk_ch0, + fpga_rxrefclk_ch0 => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT + txdata_ch0 => tx_data, + tx_k_ch0 => tx_k, + tx_force_disp_ch0 => '0', + tx_disp_sel_ch0 => '0', + rxdata_ch0 => rx_data, + rx_k_ch0 => rx_k, + rx_disp_err_ch0 => open, + rx_cv_err_ch0 => rx_error, + rx_serdes_rst_ch0_c => rx_serdes_rst, + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pcs_rst_ch0_c => tx_pcs_rst, + tx_pwrup_ch0_c => '1', + rx_pcs_rst_ch0_c => rx_pcs_rst, + rx_pwrup_ch0_c => '1', + rx_los_low_ch0_s => rx_los_low, + lsm_status_ch0_s => lsm_status, + rx_cdr_lol_ch0_s => rx_cdr_lol, + tx_div2_mode_ch0_c => '0', + rx_div2_mode_ch0_c => '0', + refclk2fpga => open, --refclk2core_S, + + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i(5 downto 0), + SCI_SEL_QUAD => sci_qd_i, + SCI_SEL_CH0 => sci_ch_i(0), + SCI_RD => sci_read_i, + SCI_WRN => sci_write_i, + + fpga_txrefclk => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT + tx_serdes_rst_c => tx_serdes_rst, + tx_pll_lol_qd_s => tx_pll_lol, + rst_qd_c => rst_qd, + serdes_rst_qd_c => serdes_rst_qd + + ); + +------------------------------------------------- +-- Reset FSM & Link states +------------------------------------------------- +THE_RX_FSM : rx_reset_fsm + port map( + RST_N => rst_n, + RX_REFCLK => clk_200_osc, --rx_full_clk_ch0, + TX_PLL_LOL_QD_S => tx_pll_lol, + RX_SERDES_RST_CH_C => rx_serdes_rst, + RX_CDR_LOL_CH_S => rx_cdr_lol, + RX_LOS_LOW_CH_S => rx_los_low, + RX_PCS_RST_CH_C => rx_pcs_rst, + WA_POSITION => wa_position_rx(3 downto 0), + STATE_OUT => rx_fsm_state + ); + +THE_TX_FSM : tx_reset_fsm + port map( + RST_N => rst_n, + TX_REFCLK => clk_200_osc, + TX_PLL_LOL_QD_S => tx_pll_lol, + RST_QD_C => rst_qd, + TX_PCS_RST_CH_C => tx_pcs_rst, + STATE_OUT => tx_fsm_state + ); + +-- Master does not do bit-locking +wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000"; + + +--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable +PROC_ALLOW : process begin + wait until rising_edge(clk_200_osc); --clk_200_i); + if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then + rx_allow <= '1'; + else + rx_allow <= '0'; + end if; + if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then + tx_allow <= '1'; + else + tx_allow <= '0'; + end if; +end process; + +rx_allow_q <= rx_allow when rising_edge(clk_100_osc); +tx_allow_q <= tx_allow when rising_edge(clk_100_osc); + + +-- start_timer begins when the rx-link is ready; i.e.: there is a working link. +-- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high. +-- This gives a slave on the other side time to start-up +-- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset +PROC_START_TIMER : process(clk_200_osc) --clk_200_i) +begin + if rising_edge(clk_200_osc) then + if got_link_ready_i = '1' then + if start_timer(start_timer'left) = '0' then + start_timer <= start_timer + 1; + end if; + else + start_timer <= (others => '0'); + end if; + end if; +end process; + +------------------------------------------------- +-- TX Data +------------------------------------------------- +THE_TX : soda_tx_control + port map( + CLK_200 => clk_200_osc, + CLK_100 => clk_100_osc, + RESET_IN => rst, --CLEAR, PL! + + TX_DATA_IN => MED_DATA_IN, + TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN, + TX_WRITE_IN => MED_DATAREADY_IN, + TX_READ_OUT => MED_READ_OUT, + + TX_DATA_OUT => tx_data, + TX_K_OUT => tx_k, + + REQUEST_RETRANSMIT_IN => request_retr_i, --TODO + REQUEST_POSITION_IN => request_retr_position_i, --TODO + + START_RETRANSMIT_IN => start_retr_i, --TODO + START_POSITION_IN => request_retr_position_i, --TODO + + TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN, + SEND_DLM => TX_DLM, + SEND_DLM_WORD => TX_DLM_WORD, + + SEND_LINK_RESET_IN => CTRL_OP(15), + TX_ALLOW_IN => tx_allow, + RX_ALLOW_IN => rx_allow, + LINK_PHASE_OUT => link_phase_S, --PL! + + DEBUG_OUT => debug_tx_control_i, + STAT_REG_OUT => stat_tx_control_i +); + +LINK_PHASE_OUT <= link_phase_S; --PL! +------------------------------------------------- +-- RX Data +------------------------------------------------- +THE_RX_CONTROL : rx_control + port map( + CLK_200 => clk_200_osc, --rx_full_clk_ch0, PL! 270814 + CLK_100 => clk_100_osc, + RESET_IN => rst, --CLEAR, PL! + + RX_DATA_OUT => MED_DATA_OUT, + RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT, + RX_WRITE_OUT => MED_DATAREADY_OUT, + RX_READ_IN => MED_READ_IN, + + RX_DATA_IN => rx_data, + RX_K_IN => rx_k, + + REQUEST_RETRANSMIT_OUT => request_retr_i, + REQUEST_POSITION_OUT => request_retr_position_i, + + START_RETRANSMIT_OUT => start_retr_i, + START_POSITION_OUT => start_retr_position_i, + + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM + RX_DLM => RX_DLM, + RX_DLM_WORD => RX_DLM_WORD, + + SEND_LINK_RESET_OUT => send_link_reset_i, + MAKE_RESET_OUT => make_link_reset_i, + RX_ALLOW_IN => rx_allow, + GOT_LINK_READY => got_link_ready_i, + + DEBUG_OUT => debug_rx_control_i, + STAT_REG_OUT => stat_rx_control_i + ); + + + +------------------------------------------------- +-- SCI +------------------------------------------------- +--gives access to serdes config port from slow control and reads word alignment every ~ 40 us +PROC_SCI_CTRL: process + variable cnt : integer range 0 to 4 := 0; +begin + wait until rising_edge(clk_100_osc); + SCI_ACK <= '0'; + case sci_state is + when IDLE => + sci_ch_i <= x"0"; + sci_qd_i <= '0'; + sci_reg_i <= '0'; + sci_read_i <= '0'; + sci_write_i <= '0'; + sci_timer <= sci_timer + 1; + if SCI_READ = '1' or SCI_WRITE = '1' then + sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_addr_i <= SCI_ADDR; + sci_data_in_i <= SCI_DATA_IN; + sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_state <= SCTRL; + elsif sci_timer(sci_timer'left) = '1' then + sci_timer <= (others => '0'); + sci_state <= GET_WA; + end if; + when SCTRL => + if sci_reg_i = '1' then + SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + else + sci_state <= SCTRL_WAIT; + end if; + when SCTRL_WAIT => + sci_state <= SCTRL_WAIT2; + when SCTRL_WAIT2 => + sci_state <= SCTRL_FINISH; + when SCTRL_FINISH => + SCI_DATA_OUT <= sci_data_out_i; + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + + when GET_WA => + if cnt = 4 then + cnt := 0; + sci_state <= IDLE; + else + sci_state <= GET_WA_WAIT; + sci_addr_i <= '0' & x"22"; + sci_ch_i <= x"0"; + sci_ch_i(cnt) <= '1'; + sci_read_i <= '1'; + end if; + when GET_WA_WAIT => + sci_state <= GET_WA_WAIT2; + when GET_WA_WAIT2 => + sci_state <= GET_WA_FINISH; + when GET_WA_FINISH => + wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); + sci_state <= GET_WA; + cnt := cnt + 1; + end case; + + if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then + SCI_NACK <= '1'; + else + SCI_NACK <= '0'; + end if; + end process; - -------------------------------------------------- --- TX Data -------------------------------------------------- -THE_TX : soda_tx_control - port map( - CLK_200 => clk_200_osc, - CLK_100 => clk_100_osc, - RESET_IN => rst, --CLEAR, PL! - - TX_DATA_IN => MED_DATA_IN, - TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN, - TX_WRITE_IN => MED_DATAREADY_IN, - TX_READ_OUT => MED_READ_OUT, - - TX_DATA_OUT => tx_data, - TX_K_OUT => tx_k, - - REQUEST_RETRANSMIT_IN => request_retr_i, --TODO - REQUEST_POSITION_IN => request_retr_position_i, --TODO - - START_RETRANSMIT_IN => start_retr_i, --TODO - START_POSITION_IN => request_retr_position_i, --TODO - - TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN, - SEND_DLM => TX_DLM, - SEND_DLM_WORD => TX_DLM_WORD, - - SEND_LINK_RESET_IN => CTRL_OP(15), - TX_ALLOW_IN => tx_allow, - RX_ALLOW_IN => rx_allow, - LINK_PHASE_OUT => link_phase_S, --PL! - - DEBUG_OUT => debug_tx_control_i, - STAT_REG_OUT => stat_tx_control_i -); - -LINK_PHASE_OUT <= link_phase_S; --PL! -------------------------------------------------- --- RX Data -------------------------------------------------- -THE_RX_CONTROL : rx_control - port map( - CLK_200 => clk_200_osc, --rx_full_clk_ch0, PL! 270814 - CLK_100 => clk_100_osc, - RESET_IN => rst, --CLEAR, PL! - - RX_DATA_OUT => MED_DATA_OUT, - RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT, - RX_WRITE_OUT => MED_DATAREADY_OUT, - RX_READ_IN => MED_READ_IN, - - RX_DATA_IN => rx_data, - RX_K_IN => rx_k, - - REQUEST_RETRANSMIT_OUT => request_retr_i, - REQUEST_POSITION_OUT => request_retr_position_i, - - START_RETRANSMIT_OUT => start_retr_i, - START_POSITION_OUT => start_retr_position_i, - - --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM - RX_DLM => RX_DLM, - RX_DLM_WORD => RX_DLM_WORD, - - SEND_LINK_RESET_OUT => send_link_reset_i, - MAKE_RESET_OUT => make_link_reset_i, - RX_ALLOW_IN => rx_allow, - GOT_LINK_READY => got_link_ready_i, - - DEBUG_OUT => debug_rx_control_i, - STAT_REG_OUT => stat_rx_control_i - ); - - - -------------------------------------------------- --- SCI -------------------------------------------------- ---gives access to serdes config port from slow control and reads word alignment every ~ 40 us -PROC_SCI_CTRL: process - variable cnt : integer range 0 to 4 := 0; -begin - wait until rising_edge(clk_100_osc); - SCI_ACK <= '0'; - case sci_state is - when IDLE => - sci_ch_i <= x"0"; - sci_qd_i <= '0'; - sci_reg_i <= '0'; - sci_read_i <= '0'; - sci_write_i <= '0'; - sci_timer <= sci_timer + 1; - if SCI_READ = '1' or SCI_WRITE = '1' then - sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); - sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); - sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); - sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); - sci_addr_i <= SCI_ADDR; - sci_data_in_i <= SCI_DATA_IN; - sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); - sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); - sci_state <= SCTRL; - elsif sci_timer(sci_timer'left) = '1' then - sci_timer <= (others => '0'); - sci_state <= GET_WA; - end if; - when SCTRL => - if sci_reg_i = '1' then - SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); - SCI_ACK <= '1'; - sci_write_i <= '0'; - sci_read_i <= '0'; - sci_state <= IDLE; - else - sci_state <= SCTRL_WAIT; - end if; - when SCTRL_WAIT => - sci_state <= SCTRL_WAIT2; - when SCTRL_WAIT2 => - sci_state <= SCTRL_FINISH; - when SCTRL_FINISH => - SCI_DATA_OUT <= sci_data_out_i; - SCI_ACK <= '1'; - sci_write_i <= '0'; - sci_read_i <= '0'; - sci_state <= IDLE; - - when GET_WA => - if cnt = 4 then - cnt := 0; - sci_state <= IDLE; - else - sci_state <= GET_WA_WAIT; - sci_addr_i <= '0' & x"22"; - sci_ch_i <= x"0"; - sci_ch_i(cnt) <= '1'; - sci_read_i <= '1'; - end if; - when GET_WA_WAIT => - sci_state <= GET_WA_WAIT2; - when GET_WA_WAIT2 => - sci_state <= GET_WA_FINISH; - when GET_WA_FINISH => - wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); - sci_state <= GET_WA; - cnt := cnt + 1; - end case; - - if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then - SCI_NACK <= '1'; - else - SCI_NACK <= '0'; - end if; - -end process; - - -------------------------------------------------- --- Debug Registers -------------------------------------------------- -debug_reg(3 downto 0) <= rx_fsm_state; -debug_reg(4) <= rx_k; -debug_reg(5) <= rx_error; -debug_reg(6) <= rx_los_low; -debug_reg(7) <= rx_cdr_lol; - -debug_reg(8) <= tx_k; -debug_reg(9) <= tx_pll_lol; -debug_reg(10) <= lsm_status; -debug_reg(11) <= make_link_reset_i; -debug_reg(15 downto 12) <= tx_fsm_state; --- debug_reg(31 downto 24) <= tx_data; - -debug_reg(16) <= '0'; -debug_reg(17) <= tx_allow; -debug_reg(18) <= RESET; -debug_reg(19) <= CLEAR; -debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8); - -debug_reg(35 downto 32) <= wa_position(3 downto 0); -debug_reg(36) <= debug_tx_control_i(6); -debug_reg(39 downto 37) <= "000"; -debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); - - -STAT_DEBUG <= debug_reg; - -internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0'; -sd_los_i <= SD_LOS_IN when rising_edge(clk_100_osc); -- PL! - -STAT_OP(15) <= send_link_reset_i when rising_edge(clk_100_osc); -STAT_OP(14) <= '0'; -STAT_OP(13) <= internal_make_link_reset_out when rising_edge(clk_100_osc); --make trbnet reset -STAT_OP(12) <= '0'; -STAT_OP(11) <= '0'; -STAT_OP(10) <= rx_allow; -STAT_OP(9) <= tx_allow; ---STAT_OP(8 downto 4) <= (others => '0'); -STAT_OP(8) <= got_link_ready_i; -STAT_OP(7) <= send_link_reset_i; -STAT_OP(6) <= make_link_reset_i; -STAT_OP(5) <= request_retr_i; -STAT_OP(4) <= start_retr_i; -STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; + + +------------------------------------------------- +-- Debug Registers +------------------------------------------------- +debug_reg(3 downto 0) <= rx_fsm_state; +debug_reg(4) <= rx_k; +debug_reg(5) <= rx_error; +debug_reg(6) <= rx_los_low; +debug_reg(7) <= rx_cdr_lol; + +debug_reg(8) <= tx_k; +debug_reg(9) <= tx_pll_lol; +debug_reg(10) <= lsm_status; +debug_reg(11) <= make_link_reset_i; +debug_reg(15 downto 12) <= tx_fsm_state; +-- debug_reg(31 downto 24) <= tx_data; + +debug_reg(16) <= '0'; +debug_reg(17) <= tx_allow; +debug_reg(18) <= RESET; +debug_reg(19) <= CLEAR; +debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8); + +debug_reg(35 downto 32) <= wa_position(3 downto 0); +debug_reg(36) <= debug_tx_control_i(6); +debug_reg(39 downto 37) <= "000"; +debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); + + +STAT_DEBUG <= debug_reg; + +internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0'; +sd_los_i <= SD_LOS_IN when rising_edge(clk_100_osc); -- PL! + +STAT_OP(15) <= send_link_reset_i when rising_edge(clk_100_osc); +STAT_OP(14) <= '0'; +STAT_OP(13) <= internal_make_link_reset_out when rising_edge(clk_100_osc); --make trbnet reset +STAT_OP(12) <= '0'; +STAT_OP(11) <= '0'; +STAT_OP(10) <= rx_allow; +STAT_OP(9) <= tx_allow; +--STAT_OP(8 downto 4) <= (others => '0'); +STAT_OP(8) <= got_link_ready_i; +STAT_OP(7) <= send_link_reset_i; +STAT_OP(6) <= make_link_reset_i; +STAT_OP(5) <= request_retr_i; +STAT_OP(4) <= start_retr_i; +STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; end med_ecp3_sfp_sync_down_arch; \ No newline at end of file diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index d076d8d..3b4e056 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -17,7 +17,7 @@ use work.version.all; entity trb3_periph_sodahub is generic( - SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests! +-- SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests! USE_125_MHZ : integer := c_NO; CLOCK_FREQUENCY : integer := 100; NUM_INTERFACES : integer := 6 + 1 -- This is the number of SERDES's in use: 1 copper trb-upstream + 6 to ADDONboard @@ -709,7 +709,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up TRB_HUB : trb_net16_hub_base generic map ( - HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES), IBUF_SECURE_MODE => c_YES, MII_NUMBER => 7, MII_IS_UPLINK => (0 => 1, others => 0), @@ -770,8 +770,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= SFP_LOS(1); --med_stat_op(8); - LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10); + LED_ORANGE <= SFP_LOS(3); --med_stat_op(8); + LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10); LED_GREEN <= med_stat_op(12); --tx_pll_lol LED_RED <= med_stat_op(11); --rx_cdr_lol @@ -779,6 +779,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up LED_RX(2) <= med_stat_op(10); LED_RX(3) <= med_stat_op(9); LED_RX(4) <= med_stat_op(6); + LED_RX(5) <= '0'; + LED_RX(6) <= '1'; --------------------------------------------------------------------------- -- DEBUG diff --git a/soda_hub.lpf b/soda_hub.lpf deleted file mode 100644 index 8191b20..0000000 --- a/soda_hub.lpf +++ /dev/null @@ -1,218 +0,0 @@ -rvl_alias "rxup_full_clk" "rxup_full_clk"; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; -BLOCK JTAGPATHS ; -################################################################# -# Basic Settings -################################################################# -SYSCONFIG MCCLK_FREQ = 20; -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; -################################################################# -# Clock I/O -################################################################# -LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; -LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? -LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; -#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; -#LOCATE COMP "PCSA_REFCLKP" SITE "AC17"; -#LOCATE COMP "PCSA_REFCLKN" SITE "AC18"; -#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; -#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL! -DEFINE PORT GROUP "CLK_group" "*CLK*" ; -IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; -################################################################# -# To central FPGA -################################################################# -LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ; -LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ; -LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ; -LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ; -LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ; -LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ; -LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ; -LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ; -LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ; -LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ; -LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ; -LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ; -DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -LOCATE COMP "TEST_LINE[0]" SITE "A5" ; -LOCATE COMP "TEST_LINE[1]" SITE "A6" ; -LOCATE COMP "TEST_LINE[2]" SITE "G8" ; -LOCATE COMP "TEST_LINE[3]" SITE "F9" ; -LOCATE COMP "TEST_LINE[4]" SITE "D9" ; -LOCATE COMP "TEST_LINE[5]" SITE "D10" ; -LOCATE COMP "TEST_LINE[6]" SITE "F10" ; -LOCATE COMP "TEST_LINE[7]" SITE "E10" ; -LOCATE COMP "TEST_LINE[8]" SITE "A8" ; -LOCATE COMP "TEST_LINE[9]" SITE "B8" ; -LOCATE COMP "TEST_LINE[10]" SITE "G10" ; -LOCATE COMP "TEST_LINE[11]" SITE "G9" ; -LOCATE COMP "TEST_LINE[12]" SITE "C9" ; -LOCATE COMP "TEST_LINE[13]" SITE "C10" ; -LOCATE COMP "TEST_LINE[14]" SITE "H10" ; -LOCATE COMP "TEST_LINE[15]" SITE "H11" ; -DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; -################################################################# -# Connection to AddOn -################################################################# -LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 -LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 -LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 -LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 -#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 -#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 -#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 -LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 -LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 -#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 -LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 -LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 -LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 -LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 -#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 -#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 -#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 -LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 -LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 -#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 -LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 -LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 -LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 -LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 -#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 -#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 -#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 -LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 -#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 -LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 -LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 -LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 -LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 -#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 -#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 -#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 -LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 -LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 -#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 -LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 -LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 -LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 -LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 -#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 -#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 -#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 -LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 -LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 -#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 -LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 -LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 -LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 -LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 -#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 -#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 -#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 -LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 -LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 -#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 -DEFINE PORT GROUP "SFP_group" "SFP*" ; -IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -################################################################# -# Additional Lines to AddOn -################################################################# -#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 -#all lines are input only -#line 4/5 go to PLL input -#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 -#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 -#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 -#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 -#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 -################################################################# -# Flash ROM and Reboot -################################################################# -LOCATE COMP "FLASH_CLK" SITE "B12" ; -LOCATE COMP "FLASH_CS" SITE "E11" ; -LOCATE COMP "FLASH_DIN" SITE "E12" ; -LOCATE COMP "FLASH_DOUT" SITE "A12" ; -DEFINE PORT GROUP "FLASH_group" "FLASH*" ; -IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; -LOCATE COMP "PROGRAMN" SITE "B11" ; -IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -################################################################# -# Misc -################################################################# -LOCATE COMP "TEMPSENS" SITE "A13" ; -IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -#coding of FPGA number -LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; -LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; -IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -#terminated differential pair to pads -LOCATE COMP "SUPPL" SITE "C14" ; -#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; -################################################################# -# LED -################################################################# -LOCATE COMP "LED_GREEN" SITE "F12" ; -LOCATE COMP "LED_ORANGE" SITE "G13" ; -LOCATE COMP "LED_RED" SITE "A15" ; -LOCATE COMP "LED_YELLOW" SITE "A16" ; -DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; - - -################################################################# -#GSR_NET NET "GSR_N"; -################################################################# -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; - -MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; -MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; -#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only -MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; -MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; -#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only -#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ; - -BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ; -BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*"; -BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*"; - -#UGROUP "SPIlogic" BBOX 20 20 -# BLKNAME THE_SPI_RELOAD; -#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ; - -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[0]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[1]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[2]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[3]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[0]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[1]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[2]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[3]"; - -## IOBUF ALLPORTS ; -USE PRIMARY NET "clk_200_osc" ; -USE PRIMARY NET "clk_100_osc" ; -USE PRIMARY NET "rxup_full_clk" ; -FREQUENCY NET "clk_200_osc" 200.000000 MHz ; -FREQUENCY NET "clk_100_osc" 100.000000 MHz ; -FREQUENCY NET "rxup_full_clk" 200.000000 MHz ; diff --git a/soda_hub.lpf b/soda_hub.lpf new file mode 120000 index 0000000..35b4571 --- /dev/null +++ b/soda_hub.lpf @@ -0,0 +1 @@ +soda_hub_groningen.lpf \ No newline at end of file diff --git a/soda_hub_frankfurt.lpf b/soda_hub_frankfurt.lpf new file mode 100644 index 0000000..7974e58 --- /dev/null +++ b/soda_hub_frankfurt.lpf @@ -0,0 +1,228 @@ +rvl_alias "rxup_full_clk" "rxup_full_clk"; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; +BLOCK JTAGPATHS ; + +################################################################# +# Basic Settings +################################################################# +SYSCONFIG MCCLK_FREQ = 20; +# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; +#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +#LOCATE COMP "PCSA_REFCLKP" SITE "AC17"; +#LOCATE COMP "PCSA_REFCLKN" SITE "AC18"; +#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL! +DEFINE PORT GROUP "CLK_group" "*CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; + +################################################################# +# To central FPGA +################################################################# +LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ; +LOCATE COMP "FPGA5_COMM_10" SITE "V10" ; +LOCATE COMP "FPGA5_COMM_11" SITE "W10" ; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5" ; +LOCATE COMP "TEST_LINE_1" SITE "A6" ; +LOCATE COMP "TEST_LINE_2" SITE "G8" ; +LOCATE COMP "TEST_LINE_3" SITE "F9" ; +LOCATE COMP "TEST_LINE_4" SITE "D9" ; +LOCATE COMP "TEST_LINE_5" SITE "D10" ; +LOCATE COMP "TEST_LINE_6" SITE "F10" ; +LOCATE COMP "TEST_LINE_7" SITE "E10" ; +LOCATE COMP "TEST_LINE_8" SITE "A8" ; +LOCATE COMP "TEST_LINE_9" SITE "B8" ; +LOCATE COMP "TEST_LINE_10" SITE "G10" ; +LOCATE COMP "TEST_LINE_11" SITE "G9" ; +LOCATE COMP "TEST_LINE_12" SITE "C9" ; +LOCATE COMP "TEST_LINE_13" SITE "C10" ; +LOCATE COMP "TEST_LINE_14" SITE "H10" ; +LOCATE COMP "TEST_LINE_15" SITE "H11" ; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; + +################################################################# +# Connection to AddOn +################################################################# +LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1 +LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3 +LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5 +LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7 +#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 +#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 +#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 +LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15 +LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17 +#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 +LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21 +LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23 +LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25 +LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27 +#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 +#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 +#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 +LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35 +LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 +#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 +LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2 +LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4 +LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6 +LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8 +#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 +#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 +#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 +LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18 +#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 +LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22 +LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24 +LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26 +LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28 +#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 +#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 +#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 +LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36 +LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38 +#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 +LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169 +LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171 +LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173 +LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175 +#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 +#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 +#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 +LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183 +LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185 +#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 +LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170 +LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172 +LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174 +LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176 +#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 +#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 +#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 +LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184 +LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186 +#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +################################################################# +# Additional Lines to AddOn +################################################################# +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "B12" ; +LOCATE COMP "FLASH_CS" SITE "E11" ; +LOCATE COMP "FLASH_DIN" SITE "E12" ; +LOCATE COMP "FLASH_DOUT" SITE "A12" ; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PROGRAMN" SITE "B11" ; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13" ; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20" ; +LOCATE COMP "CODE_LINE_0" SITE "Y21" ; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14" ; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12" ; +LOCATE COMP "LED_ORANGE" SITE "G13" ; +LOCATE COMP "LED_RED" SITE "A15" ; +LOCATE COMP "LED_YELLOW" SITE "A16" ; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; + + +################################################################# +#GSR_NET NET "GSR_N"; +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; +#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only +MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; +#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only +#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ; + +BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ; +BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*"; +BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*"; + +#UGROUP "SPIlogic" BBOX 20 20 +# BLKNAME THE_SPI_RELOAD; +#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ; + +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3"; + +## IOBUF ALLPORTS ; +USE PRIMARY NET "clk_200_osc" ; +USE PRIMARY NET "clk_100_osc" ; +USE PRIMARY NET "rxup_full_clk" ; +FREQUENCY NET "clk_200_osc" 200.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; +FREQUENCY NET "rxup_full_clk" 200.000000 MHz ; diff --git a/soda_hub_groningen.lpf b/soda_hub_groningen.lpf new file mode 100644 index 0000000..8191b20 --- /dev/null +++ b/soda_hub_groningen.lpf @@ -0,0 +1,218 @@ +rvl_alias "rxup_full_clk" "rxup_full_clk"; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; +BLOCK JTAGPATHS ; +################################################################# +# Basic Settings +################################################################# +SYSCONFIG MCCLK_FREQ = 20; +# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; +#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +#LOCATE COMP "PCSA_REFCLKP" SITE "AC17"; +#LOCATE COMP "PCSA_REFCLKN" SITE "AC18"; +#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL! +DEFINE PORT GROUP "CLK_group" "*CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; +################################################################# +# To central FPGA +################################################################# +LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ; +LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ; +LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ; +LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ; +LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ; +LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ; +LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ; +LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ; +LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ; +LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ; +LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ; +LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "TEST_LINE[0]" SITE "A5" ; +LOCATE COMP "TEST_LINE[1]" SITE "A6" ; +LOCATE COMP "TEST_LINE[2]" SITE "G8" ; +LOCATE COMP "TEST_LINE[3]" SITE "F9" ; +LOCATE COMP "TEST_LINE[4]" SITE "D9" ; +LOCATE COMP "TEST_LINE[5]" SITE "D10" ; +LOCATE COMP "TEST_LINE[6]" SITE "F10" ; +LOCATE COMP "TEST_LINE[7]" SITE "E10" ; +LOCATE COMP "TEST_LINE[8]" SITE "A8" ; +LOCATE COMP "TEST_LINE[9]" SITE "B8" ; +LOCATE COMP "TEST_LINE[10]" SITE "G10" ; +LOCATE COMP "TEST_LINE[11]" SITE "G9" ; +LOCATE COMP "TEST_LINE[12]" SITE "C9" ; +LOCATE COMP "TEST_LINE[13]" SITE "C10" ; +LOCATE COMP "TEST_LINE[14]" SITE "H10" ; +LOCATE COMP "TEST_LINE[15]" SITE "H11" ; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; +################################################################# +# Connection to AddOn +################################################################# +LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 +LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 +LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 +LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 +#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 +#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 +#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 +LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 +LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 +#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 +LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 +LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 +LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 +LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 +#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 +#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 +#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 +LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 +LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 +#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 +LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 +LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 +LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 +LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 +#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 +#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 +#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 +LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 +#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 +LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 +LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 +LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 +LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 +#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 +#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 +#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 +LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 +LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 +#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 +LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 +LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 +LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 +LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 +#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 +#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 +#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 +LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 +LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 +#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 +LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 +LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 +LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 +LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 +#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 +#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 +#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 +LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 +LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 +#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +################################################################# +# Additional Lines to AddOn +################################################################# +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "B12" ; +LOCATE COMP "FLASH_CS" SITE "E11" ; +LOCATE COMP "FLASH_DIN" SITE "E12" ; +LOCATE COMP "FLASH_DOUT" SITE "A12" ; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PROGRAMN" SITE "B11" ; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13" ; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +#coding of FPGA number +LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; +LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; +IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14" ; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12" ; +LOCATE COMP "LED_ORANGE" SITE "G13" ; +LOCATE COMP "LED_RED" SITE "A15" ; +LOCATE COMP "LED_YELLOW" SITE "A16" ; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; + + +################################################################# +#GSR_NET NET "GSR_N"; +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; +#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only +MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; +#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only +#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ; + +BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ; +BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*"; +BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*"; + +#UGROUP "SPIlogic" BBOX 20 20 +# BLKNAME THE_SPI_RELOAD; +#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ; + +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[0]"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[1]"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[2]"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[3]"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[0]"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[1]"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[2]"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[3]"; + +## IOBUF ALLPORTS ; +USE PRIMARY NET "clk_200_osc" ; +USE PRIMARY NET "clk_100_osc" ; +USE PRIMARY NET "rxup_full_clk" ; +FREQUENCY NET "clk_200_osc" 200.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; +FREQUENCY NET "rxup_full_clk" 200.000000 MHz ; diff --git a/soda_source/serdes_sync_source_downstream.txt b/soda_source/serdes_sync_source_downstream.txt index 400122b..cf095d4 100644 --- a/soda_source/serdes_sync_source_downstream.txt +++ b/soda_source/serdes_sync_source_downstream.txt @@ -44,7 +44,7 @@ CH0_COMMA_M "1111111100" CH0_RXWA "ENABLED" CH0_ILSM "ENABLED" CH0_CTC "DISABLED" -CH0_CC_MATCH4 "0000011100" +CH0_CC_MATCH4 "0100011100" CH0_CC_MATCH_MODE "1" CH0_CC_MIN_IPG "3" CCHMARK "9"