From: Jan Michel <j.michel@gsi.de>
Date: Mon, 20 May 2019 14:36:14 +0000 (+0200)
Subject: update Padiwa TDC top-level
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e82d9ad66368425ba17b1e5b0bc9642360ec1f63;p=tdc.git

update Padiwa TDC top-level
---

diff --git a/releases/tdc_v2.3/trb3_periph_padiwa.vhd b/releases/tdc_v2.3/trb3_periph_padiwa.vhd
index 441ee29..090036a 100644
--- a/releases/tdc_v2.3/trb3_periph_padiwa.vhd
+++ b/releases/tdc_v2.3/trb3_periph_padiwa.vhd
@@ -32,8 +32,6 @@ entity trb3_periph_padiwa is
 
     --Serdes
     CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 0, not used
---     SERDES_TX            : out std_logic_vector(3 downto 2);
---     SERDES_RX            : in  std_logic_vector(3 downto 2);
 
     FPGA5_COMM : inout std_logic_vector(11 downto 0);
                                         --Bit 0/1 input, serial link RX active
@@ -140,6 +138,7 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
   attribute nopad of  serdes_i : signal is "true";  
   
   signal triggerlogic_out : std_logic_vector(7 downto 0);
+  signal triggerlogic_in  : std_logic_vector(28 downto 1);
 
   --TDC
   signal hit_in_i         : std_logic_vector(64 downto 1);
@@ -350,9 +349,9 @@ begin
       DEBUG_TX_OUT  => debug_tx,
 
       --Trigger & Monitor 
-      MONITOR_INPUTS(47 downto 0) => hit_in_i(48 downto 1),
-      MONITOR_INPUTS(51 downto 48) => trig_gen_out_i,
-      TRIG_GEN_INPUTS  => hit_in_i(48 downto 1),
+      MONITOR_INPUTS(51 downto 0) => hit_in_i(52 downto 1),
+      MONITOR_INPUTS(55 downto 52) => trig_gen_out_i,
+      TRIG_GEN_INPUTS  => hit_in_i(52 downto 1),
       TRIG_GEN_OUTPUTS => trig_gen_out_i,
       LCD_OUT => lcd_out,
       --SED
@@ -367,35 +366,31 @@ begin
       DEBUG_OUT => open
       );      
 
---     OUT_CS     <= padiwa_cs(3 downto 0);
---     OUT_SCK    <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
---     OUT_SDO    <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
---     padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
-
-
       
-THE_TRIGGER_LOGIC : entity work.trigger_logic
-  generic map(
-    INPUTS  => 24,
-    OUTPUTS => 8
-    )
-  port map(
-    CLK      => clk_100_i,
-    RESET    => reset_i,
-    
-    --Slowcontrol
-    BUS_RX     => bustrigger_rx,
-    BUS_TX     => bustrigger_tx,
-    
-    --Inputs and Outputs
-    INPUT  => hit_in_i(24 downto 1),
-    OUTPUT => triggerlogic_out(7 downto 0)
-    );
-  FPGA5_COMM(10 downto 7) <= trig_gen_out_i or triggerlogic_out(3 downto 0);
-
-  
+-- THE_TRIGGER_LOGIC : entity work.trigger_logic
+--   generic map(
+--     INPUTS  => 28,
+--     OUTPUTS => 8
+--     )
+--   port map(
+--     CLK      => clk_100_i,
+--     RESET    => reset_i,
+--     
+--     --Slowcontrol
+--     BUS_RX     => bustrigger_rx,
+--     BUS_TX     => bustrigger_tx,
+--     
+--     --Inputs and Outputs
+--     INPUT  => triggerlogic_in,
+--     OUTPUT => triggerlogic_out(7 downto 0)
+--     );
+  FPGA5_COMM(10 downto 7) <= trig_gen_out_i;-- or triggerlogic_out(3 downto 0);
+
+--   triggerlogic_in <= hit_in_i(28 downto 1) when rising_edge(clk_100_i);
   --FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
-
+bustrigger_tx.ack <= '0';
+bustrigger_tx.unknown <= '1';
+bustrigger_tx.nack <= '0';
     
     
 ---------------------------------------------------------------------------
@@ -490,7 +485,7 @@ THE_TRIGGER_LOGIC : entity work.trigger_logic
     end generate Gen_Hit_In_Signals;
   end generate;
 
-  gen_double_padiwa_fast : if USE_PADIWA_FAST_ONLY = 1 generate
+  gen_double_padiwa_fast : if DOUBLE_EDGE_TYPE = 2 and USE_PADIWA_FAST_ONLY = 1 generate
     Gen_Hit_Fast_Signals : for i in 1 to 32 generate
       hit_in_i(i*2-1) <= INP(i*2-2);
       hit_in_i(i*2)   <= not INP(i*2-2);