From: Michael Boehmer Date: Mon, 6 Dec 2021 12:35:05 +0000 (+0100) Subject: fixed reset issue on rx_rsl.vhd X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=e83a16dae1f3e27eb9af7ac7fd4423962ce05e15;p=trbnet.git fixed reset issue on rx_rsl.vhd --- diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 03de147..2520265 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -163,17 +163,21 @@ begin ------------------------------------------------- -- BUG: link_tx_ready(i) for master ports to be included -- BUG: slave ports need also disable with link_tx_ready(i) - SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) when IS_MODE(3) = c_IS_MASTER else - '1' when IS_MODE(3) = c_IS_UNUSED else + SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) when IS_MODE(3) = c_IS_MASTER else + not link_rx_ready_i(3) when IS_MODE(3) = c_IS_SLAVE else + '1' when IS_MODE(3) = c_IS_UNUSED else '0'; - SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2) when IS_MODE(2) = c_IS_MASTER else - '1' when IS_MODE(2) = c_IS_UNUSED else + SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2) when IS_MODE(2) = c_IS_MASTER else + not link_rx_ready_i(2) when IS_MODE(2) = c_IS_SLAVE else + '1' when IS_MODE(2) = c_IS_UNUSED else '0'; - SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1) when IS_MODE(1) = c_IS_MASTER else - '1' when IS_MODE(1) = c_IS_UNUSED else + SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1) when IS_MODE(1) = c_IS_MASTER else + not link_rx_ready_i(1) when IS_MODE(1) = c_IS_SLAVE else + '1' when IS_MODE(1) = c_IS_UNUSED else '0'; - SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0) when IS_MODE(0) = c_IS_MASTER else - '1' when IS_MODE(0) = c_IS_UNUSED else + SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0) when IS_MODE(0) = c_IS_MASTER else + not link_rx_ready_i(0) when IS_MODE(0) = c_IS_SLAVE else + '1' when IS_MODE(0) = c_IS_UNUSED else '0'; ------------------------------------------------- diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 61bf273..8f6eda7 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -124,13 +124,14 @@ begin ------------------------------------------------- THE_RX_RST_FSM: rx_rsl port map( - CLEAR => GLOBAL_RESET_IN, + CLEAR => '0', --GLOBAL_RESET_IN, CLK_REF => CLK_REF, PLL_LOL_IN => TX_PLL_LOL_IN, CDR_LOL_IN => RX_CDR_LOL_IN, CV_IN => RX_CV_IN, LSM_IN => RX_LSM_IN, LOS_IN => RX_LOS_IN, + SD_LOS_IN => SFP_LOS_IN, WAP_ZERO_IN => is_wap_zero_i, -- outputs RX_SERDES_RST_OUT => rx_serdes_rst_i, diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index b52e551..49c8052 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -34,6 +34,7 @@ component rx_rsl is CV_IN : in std_logic; LSM_IN : in std_logic; LOS_IN : in std_logic; + SD_LOS_IN : in std_logic; WAP_ZERO_IN : in std_logic; -- outputs RX_SERDES_RST_OUT : out std_logic; diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd index 91cfdca..a6b725a 100644 --- a/media_interfaces/sync/rx_rsl.vhd +++ b/media_interfaces/sync/rx_rsl.vhd @@ -11,6 +11,7 @@ entity rx_rsl is CV_IN : in std_logic; LSM_IN : in std_logic; LOS_IN : in std_logic; + SD_LOS_IN : in std_logic; WAP_ZERO_IN : in std_logic; -- outputs RX_SERDES_RST_OUT : out std_logic; @@ -38,6 +39,7 @@ architecture rx_rsl_arc of rx_rsl is signal cv_s : std_logic; signal lsm_s : std_logic; signal los_s : std_logic; + signal sd_los_s : std_logic; signal cnt : unsigned(31 downto 0); @@ -64,6 +66,7 @@ begin cv_s <= '1'; lsm_s <= '0'; los_s <= '1'; + sd_los_s <= '1'; RX_SERDES_RST_OUT <= '1'; RX_PCS_RST_OUT <= '1'; @@ -77,7 +80,8 @@ begin cdr_lol_s <= CDR_LOL_IN; cv_s <= CV_IN; lsm_s <= LSM_IN; - los_s <= LOS_IN; + los_s <= LOS_IN; + sd_los_s <= SD_LOS_IN; case rx_sm is when POWERUP => @@ -85,7 +89,7 @@ begin RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - if( (pll_lol_s = '1') or (los_s = '1') ) then + if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then cnt <= (others => '0'); else if( cnt = Tplol ) then @@ -213,7 +217,8 @@ begin ------------------------------------------------ -- if (pll_lol_s = '1') or (los_s = '1') then - if( pll_lol_s = '1' ) then +-- if( pll_lol_s = '1' ) then + if( (pll_lol_s = '1') or (sd_los_s = '1') ) then rx_sm <= POWERUP; cnt <= (others => '0'); end if;