From: Ludwig Maier Date: Tue, 10 Jun 2014 18:51:45 +0000 (+0200) Subject: nxyter update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=eadf172068ddd1735ddf26796e4b6f8e0e164d01;p=trb3.git nxyter update --- diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 0878262..b944e3c 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -16,6 +16,7 @@ entity nx_data_receiver is RESET_IN : in std_logic; TRIGGER_IN : in std_logic; NX_ONLINE_IN : in std_logic; + NX_CLOCK_ON_IN : in std_logic; -- nXyter Ports NX_TIMESTAMP_CLK_IN : in std_logic; @@ -1460,18 +1461,35 @@ begin case R_STATE is when R_IDLE => - if (reset_for_offline = '1' or - (disable_adc_r = '0' and - (pll_adc_not_lock = '1' or - adc_reset_sync = '1')) or - startup_reset = '1' - ) then - R_STATE <= R_RESET_TIMESTAMP; - else - reset_timeout_flag <= '0'; - rs_timeout_timer_reset <= '1'; - reset_handler_busy <= '0'; - R_STATE <= R_IDLE; + if (NX_CLOCK_ON_IN = '1') then + if ((disable_adc_r = '0' and + (pll_adc_not_lock = '1' or + adc_reset_sync = '1' or + adc_frame_rate_error = '1' or + adc_error = '1' or + pll_adc_not_lock = '1' or + adc_dt_error = '1' or + adc_sclk_ok_c100 = '0' or + adc_locked_c100 = '0' + ) + ) or + nx_frame_rate_error = '1' or + startup_reset = '1' or + timestamp_dt_error = '1' or + parity_rate_error = '1' or + nx_frame_rate_error = '1' + ) then + R_STATE <= R_RESET_TIMESTAMP; + else + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; + reset_handler_busy <= '0'; + R_STATE <= R_IDLE; + end if; + else + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; + R_STATE <= R_IDLE; end if; debug_state <= x"1"; @@ -1578,7 +1596,8 @@ begin debug_state <= x"9"; when R_PLL_WAIT_LOCK => - if (pll_adc_not_lock = '0') then + if (adc_sclk_ok_c100 = '1' and + pll_adc_not_lock = '0') then -- Next: Release ADC Reset output_handler_reset <= '1'; fifo_reset_handler <= '1'; @@ -1592,7 +1611,7 @@ begin debug_state <= x"6"; when R_WAIT_ADC_OK => - if (adc_locked_c100 = '1' and + if (adc_locked_c100 = '1' and adc_frame_rate_error = '0') then -- Next: Release Output Handler and Clock Domain transfer Fifo -- Resets @@ -1605,7 +1624,7 @@ begin debug_state <= x"a"; when R_WAIT_DATA_HANDLER_OK => - if (frame_rate_error = '0') then + if (frame_rate_error = '0') then startup_reset <= '0'; reset_timeout_flag <= '0'; rs_timeout_timer_reset <= '1'; diff --git a/nxyter/source/nx_register_setup.vhd b/nxyter/source/nx_register_setup.vhd index 3bd0891..71821ba 100644 --- a/nxyter/source/nx_register_setup.vhd +++ b/nxyter/source/nx_register_setup.vhd @@ -30,6 +30,7 @@ entity nx_register_setup is INT_ADDR_IN : in std_logic_vector(15 downto 0); INT_ACK_OUT : out std_logic; INT_DATA_OUT : out std_logic_vector(31 downto 0); + NX_CLOCK_ON_OUT : out std_logic; -- Slave bus SLV_READ_IN : in std_logic; @@ -209,6 +210,9 @@ architecture Behavioral of nx_register_setup is -- Internal Register Read signal int_data_o : std_logic_vector(31 downto 0); signal int_ack_o : std_logic; + + -- Status + signal nx_clock_on_o : std_logic; -- TRBNet Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -1271,7 +1275,7 @@ begin else case SLV_ADDR_IN is when x"0050" => - -- Nxyter Clock + -- Nxyter Clock ON if (i2c_disable_memory = '0') then slv_data_out_o(0) <= i2c_ram(33)(3); slv_data_out_o(31 downto 1) <= (others => '0'); @@ -1378,6 +1382,7 @@ begin -- ReadToken slv_data_out_o <= i2c_read_token(31 downto 0); slv_ack_o <= '1'; + when x"0073" => -- ReadToken slv_data_out_o(13 downto 0) <= i2c_read_token(45 downto 32); @@ -1445,6 +1450,7 @@ begin ----------------------------------------------------------------------------- -- Output Signals ----------------------------------------------------------------------------- + nx_clock_on_o <= i2c_ram(33)(3) when rising_edge(CLK_IN); I2C_COMMAND_OUT <= i2c_command_o; I2C_LOCK_OUT <= i2c_command_busy_o; @@ -1456,6 +1462,8 @@ begin INT_ACK_OUT <= int_ack_o; INT_DATA_OUT <= int_data_o; + NX_CLOCK_ON_OUT <= nx_clock_on_o; + -- Slave Bus SLV_DATA_OUT <= slv_data_out_o; SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 234ddb0..a16af71 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -327,6 +327,7 @@ component nx_register_setup INT_ADDR_IN : in std_logic_vector(15 downto 0); INT_ACK_OUT : out std_logic; INT_DATA_OUT : out std_logic_vector(31 downto 0); + NX_CLOCK_ON_OUT : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -452,6 +453,7 @@ component nx_data_receiver RESET_IN : in std_logic; TRIGGER_IN : in std_logic; NX_ONLINE_IN : in std_logic; + NX_CLOCK_ON_IN : in std_logic; NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_TIMESTAMP_RESET_OUT : out std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 0d79588..e71a09f 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -130,6 +130,7 @@ architecture Behavioral of nXyter_FEE_board is signal spi_command : std_logic_vector(31 downto 0); signal spi_command_busy : std_logic; signal spi_data : std_logic_vector(31 downto 0); + signal nxyter_clock_on : std_logic; -- SPI Interface ADC signal spi_sdi : std_logic; @@ -358,6 +359,7 @@ begin INT_ADDR_IN => int_addr, INT_ACK_OUT => int_ack, INT_DATA_OUT => int_data, + NX_CLOCK_ON_OUT => nxyter_clock_on, SLV_READ_IN => slv_read(9), SLV_WRITE_IN => slv_write(9), SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32), @@ -555,7 +557,8 @@ begin RESET_IN => RESET_IN, TRIGGER_IN => trigger_timing, NX_ONLINE_IN => nxyter_online, - + NX_CLOCK_ON_IN => nxyter_clock_on, + NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset, diff --git a/nxyter/source/portmap.txt b/nxyter/source/portmap.txt new file mode 100644 index 0000000..6c2a9b0 --- /dev/null +++ b/nxyter/source/portmap.txt @@ -0,0 +1,22 @@ +x"0000" "0001" 1 -- Data Delay +x"0020" "0000" 0 -- Debug Handler +x"0040" "0001" 1 -- I2C Master +x"0060" "0000" 0 -- SPI Master +x"0080" "0007" 3 -- Event Buffer +x"0100" "000f" 4 -- NX Status Handler +x"0120" "001f" 5 -- Data Validate +x"0140" "0007" 3 -- Trigger Generator +x"0160" "000f" 4 -- Trigger Handler + +x"0200" "01ff" 9 0x0380 -- NX Register Setup + +x"0400" "001f" 5 -- Trigger Validate + +x"0500" "001f" 5 -- Data Receiver + + + +x"0800" "07ff" 11 -- NX Histograms + + + diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index d55c38c..f4c82ff 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -1,8 +1,8 @@ -w -i 2 -l 5 --n 28 --t 50 +-n 24 +-t 30 -s 1 -c 1 -e 2 diff --git a/nxyter/trb3_periph_nx1.vhd b/nxyter/trb3_periph_nx1.vhd index 91a776d..1bb7be4 100644 --- a/nxyter/trb3_periph_nx1.vhd +++ b/nxyter/trb3_periph_nx1.vhd @@ -375,6 +375,9 @@ begin CLOCK_FREQUENCY => 100, TIMING_TRIGGER_RAW => c_YES, + -- Feature Register, see TRB# Docu page 12 + REGIO_INCLUDED_FEATURES => x"0101_0000_0000_0000", + --Configure data handler DATA_INTERFACE_NUMBER => NUM_NXYTER, DATA_BUFFER_DEPTH => 13, --13