From: palka <palka>
Date: Thu, 21 Feb 2008 15:04:21 +0000 (+0000)
Subject: additional write register for version number
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ebee66df0cd42318d95029dea0f295a222c8d402;p=trbv2.git

additional write register for version number
---

diff --git a/etrax_interface.vhd b/etrax_interface.vhd
index 5df2a94..edb6e36 100755
--- a/etrax_interface.vhd
+++ b/etrax_interface.vhd
@@ -46,6 +46,7 @@ entity etrax_interface is
     FPGA_REGISTER_0B        : in    std_logic_vector(31 downto 0);
     FPGA_REGISTER_0C        : in    std_logic_vector(31 downto 0);
     FPGA_REGISTER_0D        : in    std_logic_vector(31 downto 0);
+    FPGA_REGISTER_0E        : out    std_logic_vector(31 downto 0);
     EXTERNAL_RESET          : out   std_logic;
     LVL2_VALID              : in    std_logic
   --  DEBUG_REGISTER_OO       : out   std_logic_vector(31 downto 0)
@@ -90,6 +91,7 @@ architecture etrax_interface of etrax_interface is
   signal fpga_register_0B_i : std_logic_vector(31 downto 0);
   signal fpga_register_0C_i : std_logic_vector(31 downto 0);
   signal fpga_register_0D_i : std_logic_vector(31 downto 0);
+  signal fpga_register_0E_i : std_logic_vector(31 downto 0);
   signal saved_external_data : std_logic_vector(31 downto 0);
   signal etrax_is_ready_to_read_i : std_logic;
   signal lvl2_not_valid_pulse : std_logic;
@@ -166,6 +168,7 @@ begin
          fpga_register_0B_i <= FPGA_REGISTER_0B;
          fpga_register_0c_i <= FPGA_REGISTER_0C;
          fpga_register_0d_i <= FPGA_REGISTER_0D;
+         FPGA_REGISTER_0E   <= fpga_register_0e_i;
      end if;
    end process REGISTERS;
     --     DEBUG_REGISTER_OO(7 downto 0) <= fpga_register_00_i(7 downto 0);
@@ -363,6 +366,8 @@ begin
     if rising_edge(CLK) then
       if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then
          fpga_register_06_i                          <= x"00000000";
+         fpga_register_07_i                          <= x"00000000";
+         fpga_register_0e_i                          <= x"00000000";
       else
         case saved_rw_mode(7 downto 0) is
           when "00000000"        =>
@@ -381,13 +386,15 @@ begin
                 when x"0000000A" => saved_data_fpga <= fpga_register_0A_i;
                 when x"0000000B" => saved_data_fpga <= fpga_register_0B_i;
                 when x"0000000C" => saved_data_fpga <= fpga_register_0C_i;
-                when x"0000000D" => saved_data_fpga <= fpga_register_0D_i;                                                                        
+                when x"0000000D" => saved_data_fpga <= fpga_register_0D_i;
+                when x"0000000E" => saved_data_fpga <= fpga_register_0E_i;
                 when others      => saved_data_fpga <= x"deadface";
               end case;
             elsif saved_rw_mode(15) = '0' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then
               case saved_address(31 downto 0) is
                 when x"00000006" => fpga_register_06_i <= saved_data;
                 when x"00000007" => fpga_register_07_i <= saved_data;
+                when x"0000000e" => fpga_register_0e_i <= saved_data;                                    
                 when others      => null;
               end case;
             end if;