From: hadeshyp Date: Tue, 2 Jun 2009 09:41:38 +0000 (+0000) Subject: added time ports to endpoint X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ec2de04808774561fa08a6495136954b4c289d8e;p=mdcoep.git added time ports to endpoint --- diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd index c66aa23..699c8ee 100644 --- a/design/mdc_oepb_pack.vhd +++ b/design/mdc_oepb_pack.vhd @@ -194,16 +194,16 @@ component mdc_addon_daq_bus_0 component trb_net16_endpoint_hades_full is generic ( USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); - IBUF_DEPTH : channel_config_t := (6,6,6,6); + IBUF_DEPTH : channel_config_t := (1,6,6,6); FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); - FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; - INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_NO); + INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_yES,c_yeS,c_NO); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; @@ -216,14 +216,15 @@ component mdc_addon_daq_bus_0 --set to 0 for each unused bit in a register REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F100"; + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE: integer := c_YES + REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR + CLOCK_FREQUENCY : itneger range 1 to 200 := 100; ); port( @@ -270,6 +271,8 @@ component mdc_addon_daq_bus_0 IPU_READ_OUT : out std_logic; IPU_LENGTH_IN : in std_logic_vector (15 downto 0); IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + -- Slow Control Data Port REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -295,6 +298,13 @@ component mdc_addon_daq_bus_0 REGIO_ONEWIRE_MONITOR_IN : in std_logic; REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + TRIGGER_MONITOR_IN : in std_logic; --strobe when timing trigger received + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond + + --Debugging & Status information STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); STAT_DEBUG_1 : out std_logic_vector (31 downto 0); STAT_DEBUG_2 : out std_logic_vector (31 downto 0); diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 3fe2449..ce90923 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -118,6 +118,12 @@ architecture mdc_oepb_arch of mdc_oepb is signal adc_timeout : std_logic; signal adc_stat : std_logic_vector(31 downto 0); + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_microsecond_tick : std_logic; + signal trigger_monitor : std_logic; + signal reg_REGIO_ADDR : std_logic_vector(15 downto 0); signal reg_REGIO_READ : std_logic; signal last_reg_REGIO_READ : std_logic; @@ -259,6 +265,12 @@ begin REGIO_ONEWIRE_INOUT => ONEWIRE, REGIO_ONEWIRE_MONITOR_IN => '0', + TRIGGER_MONITOR_IN => trigger_monitor, + GLOBAL_TIME_OUT => global_time, + LOCAL_TIME_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIMER_US_TICK_OUT => timer_microsecond_tick, + STAT_DEBUG_IPU => open, STAT_DEBUG_1 => open, STAT_DEBUG_2 => open, @@ -485,7 +497,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) -- pseudo_timing_trigger <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT; cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(7 downto 4); motherboard_type_in_i <= REGIO_REGISTERS_OUT(11 downto 8); - + end if; end process;