From: Jan Michel Date: Thu, 12 Jul 2018 09:51:42 +0000 (+0200) Subject: add Mimosis readout logic X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ec40def786e4cb2753e45e8380ca046f22d5f497;p=trb3sc.git add Mimosis readout logic --- diff --git a/mimosis/settings.sh b/mimosis/settings.sh old mode 100644 new mode 100755 index cc1bc85..9c9f3c5 --- a/mimosis/settings.sh +++ b/mimosis/settings.sh @@ -1,7 +1,20 @@ #!/bin/bash -trbcmd w 0xf3cb 0xa000 0x6700a8c0 #reversed bytes! + +export DAQOPSERVER=jspc29:82 + +trbcmd reset trbcmd w 0xf3cb 0xa001 0x409c #40000 -trbcmd w 0xf3cb 0xa002 0xC8F45FBC -trbcmd w 0xf3cb 0xa003 0x0000535D -trbcmd w 0xf3cb 0xa004 30 +### jspc57 +#trbcmd w 0xf3cb 0xa000 0x6700a8c0 #IP address reversed bytes! 192.168.0.103 +#trbcmd w 0xf3cb 0xa002 0xC8F45FBC #jspc57 MAC BC:5F:F4:C8:5D:53 +#trbcmd w 0xf3cb 0xa003 0x0000535D +### end of jspc57 +### jspc62 +trbcmd w 0xf3cb 0xa000 0x1200a8c0 #reversed bytes! 192.168.0.18 +trbcmd w 0xf3cb 0xa002 0xcaeb1734 #jspc62 MAC 34:17:eb:ca:bc:b9 +trbcmd w 0xf3cb 0xa003 0x0000b9bc +### end of jspc57 + +trbcmd w 0xf3cb 0xa004 1000 +trbcmd w 0xf3cb 0xa005 1 diff --git a/mimosis/trb3sc_mimosis.vhd b/mimosis/trb3sc_mimosis.vhd index 62eca09..82ff1ff 100644 --- a/mimosis/trb3sc_mimosis.vhd +++ b/mimosis/trb3sc_mimosis.vhd @@ -149,9 +149,18 @@ architecture trb3sc_arch of trb3sc_mimosis is signal fwd_length : std_logic_vector(15 downto 0); signal fwd_do_send : std_logic; signal word_counter : unsigned(15 downto 0); - type tx_state_t is (IDLE,SEND); + type tx_state_t is (IDLE,START,START2,SEND,SEND_1,SEND_2,SEND_3,EOB); signal tx_state : tx_state_t; + + signal fifo_data_in, fifo_data_out : std_logic_vector(35 downto 0); + signal fifo_write, fifo_read : std_logic; + signal fifo_empty, fifo_full : std_logic; + signal fifo_count : std_logic_vector(11 downto 0); + signal input_data : std_logic_vector(18 downto 0); + signal sclk_r, sclk_rr : std_logic; + signal last_valid : std_logic; + attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; attribute syn_keep of bussci_rx : signal is true; @@ -483,7 +492,6 @@ THE_REGS : process begin busrdo_tx.ack <= '0'; busrdo_tx.nack <= '0'; busrdo_tx.unknown <= '0'; - fwd_do_send <= '0'; if busrdo_rx.write = '1' then busrdo_tx.ack <= '1'; @@ -493,7 +501,7 @@ THE_REGS : process begin when x"02" => fwd_dst_mac(31 downto 0) <= busrdo_rx.data; when x"03" => fwd_dst_mac(47 downto 32) <= busrdo_rx.data(15 downto 0); when x"04" => fwd_length <= busrdo_rx.data(15 downto 0); - when x"05" => fwd_do_send <= '1'; + when x"05" => fwd_do_send <= busrdo_rx.data(0); when others => busrdo_tx.ack <= '0'; busrdo_tx.unknown <= '1'; end case; elsif busrdo_rx.read = '1' then @@ -504,43 +512,118 @@ THE_REGS : process begin when x"02" => busrdo_tx.data <= fwd_dst_mac(31 downto 0); when x"03" => busrdo_tx.data <= x"0000" & fwd_dst_mac(47 downto 32); when x"04" => busrdo_tx.data <= x"0000" & fwd_length; - when x"05" => busrdo_tx.data <= x"0000000" & fwd_full & fwd_ready & "00"; + when x"05" => busrdo_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; when others => busrdo_tx.ack <= '0'; busrdo_tx.unknown <= '1'; end case; end if; + if reset_i = '1' then + fwd_do_send <= '0'; + end if; end process; --------------------------------------------------------------------------- --- Test sender +-- Input stage +--------------------------------------------------------------------------- +sclk_r <= CLK_IN when rising_edge(clk_sys); +sclk_rr <= sclk_r when rising_edge(clk_sys); +input_data <= VALID_IN & CMD_IN & ADDRPIX_IN when rising_edge(clk_sys); + + THE_READER : process begin + wait until rising_edge(clk_sys); + fifo_write <= '0'; + + if sclk_r = '1' and sclk_rr = '0' then + last_valid <= input_data(18); + if fwd_do_send = '1' and fifo_full = '0' then + if input_data(18) = '1' then + fifo_data_in <= x"0" & x"000" & input_data(17 downto 14) & "00" & input_data(13 downto 0); + fifo_write <= '1'; + elsif last_valid = '1' then + fifo_data_in <= x"0FFFFFFFF"; + fifo_write <= '1'; + end if; + end if; + end if; + + end process; + +--------------------------------------------------------------------------- +-- Data Buffer +--------------------------------------------------------------------------- + THE_BUFFER : entity work.fifo_36x2k_oreg + port map( + Data => fifo_data_in, + Clock => clk_sys, + WrEn => fifo_write, + RdEn => fifo_read, + Reset => reset_i, + AmFullThresh => (3 => '0', others => '1'), + Q => fifo_data_out, + WCNT => fifo_count, + Empty => fifo_empty, + Full => open, + AlmostFull => fifo_full + ); + +--------------------------------------------------------------------------- +-- Sender --------------------------------------------------------------------------- THE_SENDER : process begin wait until rising_edge(clk_sys); fwd_sop <= '0'; fwd_eop <= '0'; fwd_datavalid <= '0'; + fifo_read <= '0'; case tx_state is when IDLE => - if fwd_do_send = '1' then - word_counter <= unsigned(fwd_length); + if fwd_ready = '1' and fwd_do_send = '1' and fifo_count(10) = '1' then -- + tx_state <= START; fwd_sop <= '1'; - tx_state <= SEND; + fifo_read <= '1'; end if; + when START => + word_counter <= unsigned(fwd_length); + fwd_datavalid <= '1'; + fwd_data <= x"00"; + tx_state <= START2; + when START2 => + tx_state <= SEND; when SEND => + word_counter <= word_counter - 1; + fwd_data <= fifo_data_out(31 downto 24); + --fwd_data <= std_logic_vector(word_counter(7 downto 0)); + fwd_datavalid <= '1'; + tx_state <= SEND_1; + when SEND_1 => + fwd_data <= fifo_data_out(23 downto 16); + fwd_datavalid <= '1'; + if word_counter > 0 then + fifo_read <= '1'; + end if; + tx_state <= SEND_2; + when SEND_2 => + fwd_data <= fifo_data_out(15 downto 8); + fwd_datavalid <= '1'; + tx_state <= SEND_3; + when SEND_3 => + fwd_data <= fifo_data_out(7 downto 0); fwd_datavalid <= '1'; - fwd_data <= std_logic_vector(word_counter(7 downto 0)); if word_counter = 0 then fwd_eop <= '1'; - tx_state <= IDLE; - else - word_counter <= word_counter - 1; + tx_state <= EOB; + else + tx_state <= SEND; end if; + when EOB => + tx_state <= IDLE; end case; if reset_i = '1' then tx_state <= IDLE; end if; end process; - + + --------------------------------------------------------------------------- -- Switches ---------------------------------------------------------------------------