From: Adrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Date: Tue, 2 Mar 2021 15:30:09 +0000 (+0100)
Subject: small custom agwb handler for simulation purpose
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ed1861e2cb7d7438f437ddf7bee2630ef0bb3a1c;p=cri.git

small custom agwb handler for simulation purpose
---

diff --git a/src/agwb_handler_dca_sim.vhd b/src/agwb_handler_dca_sim.vhd
new file mode 100644
index 0000000..1059fb9
--- /dev/null
+++ b/src/agwb_handler_dca_sim.vhd
@@ -0,0 +1,79 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+
+-- just for simulation purpose
+use work.wishbone_pkg.all;
+
+entity agwb_handler_dca_sim is
+  port (
+    CLK_DCA          : in  std_logic;  -- 40 MHz clock of DCA
+    
+    -- DCA INTERFACE
+    WB_SLAVE_IN      : in  t_wishbone_slave_in;
+    WB_SLAVE_OUT     : out t_wishbone_slave_out;
+
+    -- protocol specific ports
+    RX_DATA_MAIN_OUT : out std_logic_vector(31 downto 0);
+    RX_DATA_MAIN_STB : out std_logic;
+
+    RX_DATA_END_OUT  : out std_logic_vector(31 downto 0);
+    RX_DATA_END_STB  : out std_logic;
+    
+    TX_DATA_IN       : in  std_logic_vector(31 downto 0);
+    TX_READ_ACK      : out std_logic;
+    
+    TX_SIZE_DATA     : in  std_logic_vector(31 downto 0); -- in byte
+    TX_SIZE_ACK      : out std_logic
+    
+  );
+end entity agwb_handler_dca_sim;
+
+architecture RTL of agwb_handler_dca_sim is
+
+
+begin
+
+
+THE_AGWBHANDLER_FSM : process
+begin
+  wait until rising_edge(CLK_DCA);
+  
+  RX_DATA_MAIN_STB <= '0';
+  RX_DATA_END_STB  <= '0';
+  TX_READ_ACK      <= '0';
+  TX_SIZE_ACK      <= '0';
+  WB_SLAVE_OUT.ack <= '0';
+  
+  if WB_SLAVE_IN.cyc = '1' and WB_SLAVE_IN.stb = '1' then
+  
+    if    WB_SLAVE_IN.adr = x"00000000" then
+      -- normal Write reg
+      if WB_SLAVE_IN.we = '1' then
+        RX_DATA_MAIN_OUT <= WB_SLAVE_IN.dat;
+        RX_DATA_MAIN_STB <= '1';
+      end if;
+    elsif WB_SLAVE_IN.adr = x"00000001" then
+      -- normal Write reg
+      if WB_SLAVE_IN.we = '1' then
+        RX_DATA_END_OUT <= WB_SLAVE_IN.dat;
+        RX_DATA_END_STB <= '1';
+      end if;
+    elsif WB_SLAVE_IN.adr = x"00000002" then
+      if WB_SLAVE_IN.we = '0' then
+        WB_SLAVE_OUT.dat <= TX_DATA_IN;
+        WB_SLAVE_OUT.ack <= '1';
+      end if;    
+    elsif WB_SLAVE_IN.adr = x"00000003" then  
+      if WB_SLAVE_IN.we = '0' then
+        WB_SLAVE_OUT.dat <= TX_DATA_IN;
+        WB_SLAVE_OUT.ack <= '1';
+      end if;
+    end if;
+  end if;  
+end process;
+
+end architecture RTL;