From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Mon, 20 Dec 2021 11:36:30 +0000 (+0100)
Subject: TABs removed
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=edf42af2694e8a39cd7df07c59de6f42ba22d950;p=trbnet.git

TABs removed
---

diff --git a/special/trb_net_reset_handler.vhd b/special/trb_net_reset_handler.vhd
index fcb8524..694a102 100644
--- a/special/trb_net_reset_handler.vhd
+++ b/special/trb_net_reset_handler.vhd
@@ -5,22 +5,21 @@ use ieee.std_logic_unsigned.all;
 
 library work;
 
-
 entity trb_net_reset_handler is
-generic(
-	RESET_DELAY     : std_logic_vector(15 downto 0) := x"1fff"
-);
+  generic(
+    RESET_DELAY     : std_logic_vector(15 downto 0) := x"1fff"
+  );
 port(
-	CLEAR_IN        : in    std_logic; -- reset input (high active, async)
-	CLEAR_N_IN      : in    std_logic; -- reset input (low active, async)
-	CLK_IN          : in    std_logic; -- raw master clock, NOT from PLL/DLL!
-	SYSCLK_IN       : in    std_logic; -- PLL/DLL remastered clock
-	PLL_LOCKED_IN   : in    std_logic; -- master PLL lock signal (async)
-	RESET_IN        : in    std_logic; -- general reset signal (SYSCLK)
-	TRB_RESET_IN    : in    std_logic; -- TRBnet reset signal (SYSCLK)
-	CLEAR_OUT       : out   std_logic; -- async reset out, USE WITH CARE!
-	RESET_OUT       : out   std_logic; -- synchronous reset out (SYSCLK)
-	DEBUG_OUT       : out   std_logic_vector(15 downto 0)
+  CLEAR_IN        : in    std_logic; -- reset input (high active, async)
+  CLEAR_N_IN      : in    std_logic; -- reset input (low active, async)
+  CLK_IN          : in    std_logic; -- raw master clock, NOT from PLL/DLL!
+  SYSCLK_IN       : in    std_logic; -- PLL/DLL remastered clock
+  PLL_LOCKED_IN   : in    std_logic; -- master PLL lock signal (async)
+  RESET_IN        : in    std_logic; -- general reset signal (SYSCLK)
+  TRB_RESET_IN    : in    std_logic; -- TRBnet reset signal (SYSCLK)
+  CLEAR_OUT       : out   std_logic; -- async reset out, USE WITH CARE!
+  RESET_OUT       : out   std_logic; -- synchronous reset out (SYSCLK)
+  DEBUG_OUT       : out   std_logic_vector(15 downto 0)
 );
 end;
 
@@ -70,10 +69,10 @@ comb_async_rst_n <= not clear_in and clear_n_in and pll_locked_in;
 ----------------------------------------------------------------
 THE_ASYNC_SAMPLER_PROC: process( clk_in )
 begin
-	if( rising_edge(clk_in) ) then
-		async_sampler(7 downto 0) <= async_sampler(6 downto 0) & comb_async_rst_n;
-		async_pulse               <= comb_async_pulse;
-	end if;
+  if( rising_edge(clk_in) ) then
+    async_sampler(7 downto 0) <= async_sampler(6 downto 0) & comb_async_rst_n;
+    async_pulse               <= comb_async_pulse;
+  end if;
 end process THE_ASYNC_SAMPLER_PROC;
 
 -- first two registers are clock domain transfer registers!
@@ -84,19 +83,19 @@ comb_async_pulse <= '1' when ( async_sampler(7 downto 2) = b"0000_00" ) else '0'
 ----------------------------------------------------------------
 THE_SYNC_PROC: process( sysclk_in )
 begin
-	if( rising_edge(sysclk_in) ) then
-		reset_buffer     <= RESET_IN;      -- not really needed, but relaxes timing
-		trb_reset_buffer <= TRB_RESET_IN;  -- not really needed, but relaxes timing
-		final_reset      <= final_reset(0) & reset;
-	end if;
+  if( rising_edge(sysclk_in) ) then
+    reset_buffer     <= RESET_IN;      -- not really needed, but relaxes timing
+    trb_reset_buffer <= TRB_RESET_IN;  -- not really needed, but relaxes timing
+    final_reset      <= final_reset(0) & reset;
+  end if;
 end process THE_SYNC_PROC;
 
 THE_CROSSING_PROC: process( clk_in )
 begin
-	if( rising_edge(clk_in) ) then
-		reset_pulse      <= reset_pulse(0)     & reset_buffer;
-		trb_reset_pulse  <= trb_reset_pulse(0) & trb_reset_buffer;
-	end if;
+  if( rising_edge(clk_in) ) then
+    reset_pulse      <= reset_pulse(0)     & reset_buffer;
+    trb_reset_pulse  <= trb_reset_pulse(0) & trb_reset_buffer;
+  end if;
 end process THE_CROSSING_PROC;
 
 ----------------------------------------------------------------
@@ -104,19 +103,19 @@ end process THE_CROSSING_PROC;
 ----------------------------------------------------------------
 THE_GLOBAL_RESET_PROC: process( clk_in )
 begin
-	if( rising_edge(clk_in) ) then
-		if( (async_pulse = '1') or (reset_pulse(1) = '1') or (trb_reset_pulse(1) = '1') ) then
-			reset_cnt <= (others => '0');
-			reset     <= '1';
-		else
-			reset_cnt <= reset_cnt + 1;
-			reset     <= '1';
-			if( reset_cnt = RESET_DELAY ) then
-				reset     <= '0';
-				reset_cnt <= RESET_DELAY;
-			end if;
-		end if;
-	end if;
+  if( rising_edge(clk_in) ) then
+    if( (async_pulse = '1') or (reset_pulse(1) = '1') or (trb_reset_pulse(1) = '1') ) then
+      reset_cnt <= (others => '0');
+      reset     <= '1';
+    else
+      reset_cnt <= reset_cnt + 1;
+      reset     <= '1';
+      if( reset_cnt = RESET_DELAY ) then
+        reset     <= '0';
+        reset_cnt <= RESET_DELAY;
+      end if;
+    end if;
+  end if;
 end process THE_GLOBAL_RESET_PROC;
 
 ----------------------------------------------------------------