From: Jan Michel Date: Mon, 22 Jul 2019 09:22:09 +0000 (+0200) Subject: add 16 clock TDC test X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ee836b80af321f2e57e98fea8e479fbc57e9e328;p=trb5sc.git add 16 clock TDC test --- diff --git a/tdc16clk/code/ffarray.vhd b/tdc16clk/code/ffarray.vhd new file mode 100644 index 0000000..6ada58d --- /dev/null +++ b/tdc16clk/code/ffarray.vhd @@ -0,0 +1,256 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity ffarray is + generic( + CHANNELS : integer := 1 + ); + port( + CLK : in std_logic; + SYSCLK : in std_logic; + RESET_IN : in std_logic; + SIGNAL_IN : in std_logic_vector(CHANNELS-1 downto 0); + SPIKE_REJECT: in std_logic; +-- DATA_OUT : out std_logic_vector(31 downto 0); +-- READ_IN : in std_logic := '0'; + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + EMPTY_OUT : out std_logic := '0' + ); +end entity; + +architecture ffarray_arch of ffarray is + +attribute syn_hier : string; +attribute syn_hier of ffarray_arch : architecture is "hard"; + +signal CLKt : std_logic_vector(3 downto 0); +signal CLKa : std_logic_vector(15 downto 0); +signal clk_tdc_i : std_logic_vector(1 downto 0); +signal clk_tdc : std_logic; + +type vector_arr_5 is array (0 to CHANNELS-1) of std_logic_vector(6 downto 0); +type vector_arr_8 is array (0 to CHANNELS-1) of std_logic_vector(15 downto 0); +type vector_arr_9 is array (0 to CHANNELS-1) of std_logic_vector(17 downto 0); + +signal final1, final2 : vector_arr_8; +signal final_t : vector_arr_8; +signal final : vector_arr_9; +type ffarr_t is array(0 to 2) of vector_arr_8; +signal ffarr : ffarr_t; +signal finalval : vector_arr_5; + +signal inpgate : std_logic_vector(CHANNELS-1 downto 0); +signal buffer_read : std_logic_vector(CHANNELS-1 downto 0); +type buffer_t is array(0 to 1) of std_logic_vector(30 downto 0); +type buffers_t is array(CHANNELS-1 downto 0) of buffer_t; +signal buffer_data : buffers_t; +signal buffer_empty_0, buffer_empty_1 : std_logic_vector(CHANNELS-1 downto 0); +signal spike_reject_f : std_logic; + +type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0); +signal ram : ram_t; + +signal fifo_write, last, fifo_write_val : std_logic_vector(CHANNELS-1 downto 0); + +signal fifo_real_write, fifo_empty, valid_read : std_logic; +signal fifo_data : std_logic_vector(35 downto 0); +signal fifo_data_out : std_logic_vector(35 downto 0); + + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + + attribute syn_preserve of CLKa : signal is true; + attribute syn_keep of CLKa : signal is true; + attribute syn_preserve of CLKt : signal is true; + attribute syn_keep of CLKt : signal is true; + +signal timer : unsigned(20 downto 0) := (others => '0'); +signal read_q, read_qq : std_logic; + +begin + +timer <= timer + 1 when rising_edge(clk_tdc); +spike_reject_f <= SPIKE_REJECT when rising_edge(clk_tdc); + +THE_PLL_FIRST : entity work.pll_125_375 + port map( + CLKI => CLK, + CLKOP => open, + CLKOS => clk_tdc_i(0), + CLKOS2 => clk_tdc_i(1), + CLKOS3 => clk_tdc + ); +THE_PLL_SECOND_1 : entity work.pll_375_1 + port map( + CLKI => clk_tdc_i(0), + CLKOP => CLKa(0), + CLKOS => CLKa(1), + CLKOS2 => CLKa(2), + CLKOS3 => CLKa(3) + ); +THE_PLL_SECOND_2 : entity work.pll_375_1 + port map( + CLKI => clk_tdc_i(1), + CLKOP => CLKa(4), + CLKOS => CLKa(5), + CLKOS2 => CLKa(6), + CLKOS3 => CLKa(7) + ); + +-- CLKa(3 downto 0) <= CLKt(3 downto 0); +CLKa(15 downto 8) <= not CLKa(7 downto 0); + + +gen_channels : for c in 0 to CHANNELS-1 generate + inpgate(c) <= SIGNAL_IN(c); + gen_ffarr_first : for i in 0 to 15 generate + ffarr(0)(c)(i) <= inpgate(c) when rising_edge(CLKa(i)); + ffarr(1)(c)(i) <= ffarr(0)(c)(i) when rising_edge(CLKa((i/8)*8)); + ffarr(2)(c)(i) <= ffarr(1)(c)(i) when rising_edge(CLKa(0)); + end generate; + +process begin + wait until rising_edge(CLKa(0)); + final_t(c) <= ffarr(2)(c); +end process; + + + +process begin + wait until rising_edge(clk_tdc); + final1(c) <= final_t(c); + final2(c) <= ffarr(2)(c); + last(c) <= final2(c)(15); + if (final1(c)(15) xor last(c)) = '1' then + fifo_write(c) <= '1'; + final(c) <= '0' & final1(c) & last(c); + elsif (final2(c)(15) xor final1(c)(15)) = '1' then + fifo_write(c) <= '1'; + final(c) <= '1' & final2(c) & final1(c)(15); + else + fifo_write(c) <= '0'; + end if; +end process; + + +process begin + wait until rising_edge(clk_tdc); + if fifo_write(c) = '1' then + finalval(c) <= (others => '0'); + case final(c)(15 downto 0) is + when x"0001" | x"fffe" => finalval(c)(3 downto 0) <= "0000"; + when x"0003" | x"fffc" => finalval(c)(3 downto 0) <= "0001"; + when x"0007" | x"fff8" => finalval(c)(3 downto 0) <= "0010"; + when x"000f" | x"fff0" => finalval(c)(3 downto 0) <= "0011"; + when x"001f" | x"ffe0" => finalval(c)(3 downto 0) <= "0100"; + when x"003f" | x"ffc0" => finalval(c)(3 downto 0) <= "0101"; + when x"007f" | x"ff80" => finalval(c)(3 downto 0) <= "0110"; + when x"00ff" | x"ff00" => finalval(c)(3 downto 0) <= "0111"; + when x"01ff" | x"fe00" => finalval(c)(3 downto 0) <= "1000"; + when x"03ff" | x"fc00" => finalval(c)(3 downto 0) <= "1001"; + when x"07ff" | x"f800" => finalval(c)(3 downto 0) <= "1010"; + when x"0fff" | x"f000" => finalval(c)(3 downto 0) <= "1011"; + when x"1fff" | x"e000" => finalval(c)(3 downto 0) <= "1100"; + when x"3fff" | x"c000" => finalval(c)(3 downto 0) <= "1101"; + when x"7fff" | x"8000" => finalval(c)(3 downto 0) <= "1110"; + when x"ffff" | x"0000" => finalval(c)(3 downto 0) <= "1111"; + when others => finalval(c)(6) <= '1'; + end case; + finalval(c)(5) <= final(c)(17); + finalval(c)(4) <= final(c)(16); + if(final(c)(0) = final1(c)(0) or spike_reject = '0') then + fifo_write_val(c) <= '1'; + end if; + else + fifo_write_val(c) <= '0'; + end if; +end process; + +PROC_BUFFER : process begin + wait until rising_edge(clk_tdc); + if fifo_write_val(c) = '1' then + if buffer_empty_0(c) = '1' then + buffer_data(c)(0)(3 downto 0) <= finalval(c)(3 downto 0); + buffer_data(c)(0)(4) <= finalval(c)(6); + buffer_data(c)(0)(5) <= finalval(c)(5); + buffer_data(c)(0)(25 downto 6) <= std_logic_vector(timer(19 downto 0)); + buffer_data(c)(0)(29 downto 26) <= (others => '0'); + buffer_data(c)(0)(30) <= finalval(c)(4); + buffer_empty_0(c) <= '0'; + end if; + end if; + if buffer_read(c) = '1' then + buffer_empty_1(c) <= '1'; + end if; + if buffer_empty_0(c) = '0' and buffer_empty_1(c) = '1' then + buffer_data(c)(1) <= buffer_data(c)(0); + buffer_empty_0(c) <= '1'; + buffer_empty_1(c) <= '0'; + end if; + +end process; + + +end generate; + +process + variable chan : integer range 0 to 16 := 0; +begin + wait until rising_edge(clk_tdc); + fifo_real_write <= '0'; + buffer_read <= (others => '0'); + if buffer_empty_1(chan) = '0' then + fifo_data(30 downto 0) <= buffer_data(chan)(1); + fifo_data(29 downto 26)<= std_logic_vector(to_unsigned(chan,4)); + if(chan = 0) then --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + fifo_real_write <= '1'; + end if; --!!!!!!!!!!! + buffer_read(chan) <= '1'; + end if; + chan := chan + 1; + if chan = 9 then chan := 0; end if; +end process; + + +THE_FIFO : entity work.fifo_36x1k + port map( +-- Data => fifo_data, + Data(17 downto 0) => final(0), + WrClock => clk_tdc, + RdClock => SYSCLK, + WrEn => fifo_write(0), +-- WrEn => fifo_real_write, + RdEn => BUS_RX.read, + Reset => RESET_IN, + RPReset => RESET_IN, + Q => fifo_data_out, + Empty => fifo_empty, + Full => open, + AlmostEmpty => open, + AlmostFull => open + ); + +process begin + wait until rising_edge(SYSCLK); + if BUS_RX.read = '1' then + valid_read <= not fifo_empty; + end if; + read_q <= BUS_RX.read; + read_qq <= read_q; +end process; + +EMPTY_OUT <= fifo_empty; +BUS_TX.data <= valid_read & fifo_data_out(30 downto 0); +BUS_TX.ack <= read_qq; +BUS_TX.nack <= '0'; +BUS_TX.unknown <= '0'; + + +end architecture; diff --git a/tdc16clk/compile.pl b/tdc16clk/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/tdc16clk/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/tdc16clk/config.vhd b/tdc16clk/config.vhd new file mode 100644 index 0000000..998bd65 --- /dev/null +++ b/tdc16clk/config.vhd @@ -0,0 +1,121 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F570"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"81"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/tdc16clk/config_compile_frankfurt.pl b/tdc16clk/config_compile_frankfurt.pl new file mode 100644 index 0000000..151c5fa --- /dev/null +++ b/tdc16clk/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_mdctdc", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_tdc', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/tdc16clk/par.p2t b/tdc16clk/par.p2t new file mode 100644 index 0000000..9e4ef4d --- /dev/null +++ b/tdc16clk/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 2 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/tdc16clk/readdata2.pl b/tdc16clk/readdata2.pl new file mode 100755 index 0000000..83f3154 --- /dev/null +++ b/tdc16clk/readdata2.pl @@ -0,0 +1,203 @@ +#!/usr/bin/perl + +use strict; +use warnings; +use feature 'state'; +use URI::Escape; +use Data::Dumper; +use HADES::TrbNet; +use Time::HiRes qw( usleep); +use Getopt::Long; +use Fcntl; + +use HADES::TrbNet; + +if (!defined $ENV{'DAQOPSERVER'}) { + die "DAQOPSERVER not set in environment"; +} + +if (!defined &trb_init_ports()) { + die("can not connect to trbnet-daemon on the $ENV{'DAQOPSERVER'}"); +} + +my @counters; +my $port; +my $help; +my $ser_dev; +my $isTrbNet = 0; +my $poll = 0; +my $cmd = ""; +my $verbose = 0; +my $invert_trigger = 0; + +my $fh; + +Getopt::Long::Configure(qw(gnu_getopt)); +GetOptions( + 'help|h' => \$help, + 'device|d=s' => \$ser_dev, +# 'poll|p' => \$poll, + 'verbose|v' => \$verbose, + 'invert_trigger|i' => \$invert_trigger, + ) ; + +if ($help || (defined $ARGV[0] && $ARGV[0] =~ /help/)) { + exit; + } + +# +# $ser_dev = "/dev/ttyUSB1" unless defined $ser_dev; +# $cmd = "RD0" if $poll; +my $last = 0; +# +# +# my $c = "stty -F $ser_dev 921600 raw"; +# #my $c = "stty -F $ser_dev -isig -icanon -iexten speed 921600 time 100"; +# my $r = qx($c); +# print $r; +# +# $r = open ($fh, "+<", $ser_dev); +# unless ($fh) { +# print "can't open serial interface $ser_dev\n"; +# exit; +# } +# +# $|=1; + + + +sub Stream { + my $v = 0; + while(1) { + my $d = trb_register_read_mem(0xf570,0xc000,1,1000); + foreach my $v (@{$d->{0xf570}}) { + +# if ($_ =~ /([A-Fa-f0-9]{8})/) {$v = hex($1);} +# next if ($v>>16 & 0xffff) == 0xdead; + unless ($v & 0x80000000) {next;} + next if $last == $v; + $counters[($v&0x1f) + (($v>>30 & 1) << 16)]++; + my $diff = ($v>>5 & 0x1fffff)*16+($v & 0xf) - ($last>>5 & 0x1fffff)*16-($last & 0xf); + $diff += 2**24 if $diff < 0; + printf("%i\t%i\t%03x\t%i\t%i\n",$v>>30 & 1, $v>>26 & 0xf, ($v & 0x1f), $v>>5 & 0x1fffff, $diff) if $verbose; + $last = $v if (($v>>30 & 1)==$invert_trigger) && (($v>>26&0xf) == 8) ; + } + } + } + + +# sub Cmd { +# my ($c) = @_; +# #print "send command '$c'\n"; +# if ($c ne "") { +# my $s = $c . "T"x0 . "\n"; +# #print "send string '$s'\n"; +# print $fh $s; +# } +# #usleep(10); +# #sleep 1; +# #sleep 1; +# my $timeout = 1; +# #return; +# #print "try to read \n"; +# my ($rec) = eval { +# local $SIG{ALRM} = sub { die "alarm\n" }; # NB: \n required +# alarm $timeout; +# #my $rec2 = <$fh>; +# my $rec2 =""; +# my $nread = sysread $fh, $rec2, 100; +# #print "received (n words: $nread) in eval: $rec2\n"; +# alarm 0; +# $rec2; +# }; +# if ($@) { +# die unless $@ eq "alarm\n"; # propagate unexpected errors +# print "timed out\n"; +# # timed out +# } +# else { +# #print "received: $rec\n"; +# } +# +# # return $rec; +# +# if ($rec =~ /R([A-Fa-f0-9]{8})/) {return hex($1);} +# +# return 0xdeadde99 if $poll; +# +# #print "%\n"; +# #return 0xdeaddead; +# } + +# sub decode { +# my $v = shift @_; +# return 0 if($v == 0x001 || $v == 0x1fe); +# return 1 if($v == 0x003 || $v == 0x1fc); +# return 2 if($v == 0x007 || $v == 0x1f8); +# return 3 if($v == 0x00f || $v == 0x1f0); +# return 4 if($v == 0x01f || $v == 0x1e0); +# return 5 if($v == 0x03f || $v == 0x1c0); +# return 6 if($v == 0x07f || $v == 0x180); +# return 7 if($v == 0x0ff || $v == 0x100); +# return $v; +# } + + +$SIG{"INT"} = \&finish; +$SIG{"QUIT"} = \&stats; + +sub finish{ +# my $v = Cmd("W0000000000"); + stats(); + exit; +} + +sub stats{ + print "----------------------\n"; + print "Bin\tCnt1\tSize1\tCnt2\tSize2\n"; + my @sum ; + for(my $i=0; $i < 512; $i++){ + if ($counters[$i]) { + $sum[$i/256] += $counters[$i]; + } + } + + for(my $i=0; $i < 256; $i++){ + if ($counters[$i]) { + printf("%01x\t%i\t%i\t%i\t%i\n",$i,$counters[$i], $counters[$i]/$sum[0]*1000000/375, +# $counters[$i+256], $counters[$i]/$sum[1]*1000000/375 +) + } + } + print ("Sum:\t$sum[0]\t\t$sum[1]\n"); + print "----------------------\n"; + } + +# main + + + +# my $v; + + +# Cmd("W0000000001") unless $poll; + +print "Edge\tChan\tFine\tCoarse\tDiff to last leading edge in 500ps bins\n"; +# if(!$poll) { +Stream(); +# } +# else { +# while(1) { +# $v = Cmd("$cmd"); +# next if ($v>>16 & 0xffff) == 0xdead; +# unless ($v & 0x80000000) {next;} +# next if $last == $v; +# $counters[($v&0xf) + (($v>>30 & 1) << 8)]++; +# my $diff = ($v>>4 & 0x3fffff)*8+($v & 0x7) - ($last>>4 & 0x3fffff)*8-($last & 0x7); +# $diff += 2**25 if $diff < 0; +# printf("%i\t%i\t%03x\t%i\t%i\n",$v>>30 & 1, $v>>26 & 0xf, ($v & 0x0f), $v>>4 & 0x3fffff, $diff) if $verbose; +# $last = $v if $v>>30 & 1; +# } +# } + + diff --git a/tdc16clk/trb5sc_mdctdc.lpf b/tdc16clk/trb5sc_mdctdc.lpf new file mode 100644 index 0000000..8670db5 --- /dev/null +++ b/tdc16clk/trb5sc_mdctdc.lpf @@ -0,0 +1,180 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +# UGROUP "INPGATE0" BBOX 1 1 +# BLKNAME THE_TDC/gen_channels.0.inpgate[0] +# ; +# LOCATE UGROUP "INPGATE0" SITE "R14C4D"; + +UGROUP "ffarr0groupA" BBOX 3 3 + BLKNAME THE_TDC/ffarr_0_0 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[8] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[9] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[10] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[11] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[12] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[13] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[14] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[15] + ; +LOCATE UGROUP "ffarr0groupA" SITE "R13C2D"; +# UGROUP "ffarr0groupA1" BBOX 1 1 +# BLKNAME THE_TDC/ffarr_0_0 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] +# ; +# LOCATE UGROUP "ffarr0groupA1" SITE "R13C2D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[8] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[9] +# +# +# +# UGROUP "ffarr0groupA2" BBOX 1 1 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] +# ; +# LOCATE UGROUP "ffarr0groupA2" SITE "R13C3D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[10] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[11] +# +# +# UGROUP "ffarr0groupA3" BBOX 1 1 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] +# ; +# LOCATE UGROUP "ffarr0groupA3" SITE "R14C2D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[12] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[13] +# +# +# UGROUP "ffarr0groupA4" BBOX 1 1 +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] +# ; +# LOCATE UGROUP "ffarr0groupA4" SITE "R14C3D"; +# +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[14] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[15] + + +UGROUP "ffarr0groupB" BBOX 3 2 + BLKNAME THE_TDC/ffarr_1_0 + BLKNAME THE_TDC/ffarr_2_0 + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[1] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[2] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[3] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[4] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[5] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[6] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[7] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[8] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[8] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[9] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[9] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[10] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[10] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[11] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[11] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[12] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[12] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[13] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[13] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[14] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[14] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[15] + BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[15] + ; + + +LOCATE UGROUP "ffarr0groupB" SITE "R14C5D"; + +# +# UGROUP "ffarr0groupAD" BBOX 2 2 +# BLKNAME THE_TDC/ffarr_0_0[0] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] +# ; +# +# UGROUP "ffarr0groupBD" BBOX 2 2 +# BLKNAME THE_TDC/ffarr_1_0[0] +# BLKNAME THE_TDC/ffarr_2_0[0] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[1] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[2] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[3] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[4] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[5] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[6] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[7] +# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[7] +# ; +# +# LOCATE UGROUP "ffarr0groupAD" SITE "R13C2D"; +# LOCATE UGROUP "ffarr0groupBD" SITE "R13C4D"; diff --git a/tdc16clk/trb5sc_mdctdc.prj b/tdc16clk/trb5sc_mdctdc.prj new file mode 100644 index 0000000..5a5094b --- /dev/null +++ b/tdc16clk/trb5sc_mdctdc.prj @@ -0,0 +1,203 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_mdctdc" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_mdctdc.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + +add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "./project/plltdc/fifo_36x1k/fifo_36x1k.vhd" +add_file -vhdl -lib work "./project/plltdc/pll_125_375/pll_125_375.vhd" +add_file -vhdl -lib work "./project/plltdc/pll_375_1/pll_375_1.vhd" +add_file -vhdl -lib work "./code/ffarray.vhd" + +add_file -vhdl -lib work "./trb5sc_mdctdc.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/tdc16clk/trb5sc_mdctdc.vhd b/tdc16clk/trb5sc_mdctdc.vhd new file mode 100644 index 0000000..78797b2 --- /dev/null +++ b/tdc16clk/trb5sc_mdctdc.vhd @@ -0,0 +1,428 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_mdctdc is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn +-- FE_GPIO : inout std_logic_vector(11 downto 0); +-- FE_CLK : out std_logic_vector( 2 downto 1); +-- FE_DIFF : inout std_logic_vector(63 downto 0); + INP : in std_logic_vector(63 downto 0); + + CS : out std_logic_vector(4 downto 1); + MISO : in std_logic_vector(4 downto 1); + MOSI : out std_logic; + SCK : out std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); + HDR_IO : inout std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of trb5sc_mdctdc is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1); + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0); + + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal link_stat_in_reg : std_logic; + + signal tdc_data : std_logic_vector(31 downto 0); + signal tdc_read, tdc_empty : std_logic; + +begin + +trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => bustdc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => bustdc_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO(9 downto 0), + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => monitor_inputs_i, + TRIG_GEN_INPUTS => trigger_inputs_i, + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + CS <= spi_cs(3 downto 0); + spi_miso(3 downto 0) <= MISO; + + MOSI <= spi_mosi(0) when spi_cs(0) = '0' + else spi_mosi(1) when spi_cs(1) = '0' + else spi_mosi(2) when spi_cs(2) = '0' + else spi_mosi(3) when spi_cs(3) = '0' + else '0'; + + SCK <= spi_clk(0) when spi_cs(0) = '0' + else spi_clk(1) when spi_cs(1) = '0' + else spi_clk(2) when spi_cs(2) = '0' + else spi_clk(3) when spi_cs(3) = '0' + else '1'; + + + monitor_inputs_i <= INP(MONITOR_INPUT_NUM-1 downto 0); + trigger_inputs_i <= INP(TRIG_GEN_INPUT_NUM-1 downto 0); + hit_in_i <= INP(NUM_TDC_CHANNELS-2 downto 0); + + assert DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error; + + HDR_IO(15 downto 10) <= (others => '0'); +-- TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; + FLASH_NCS <= flash_ncs_i; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off; + LED <= x"F0"; + LED_RJ_GREEN <= "00"; + LED_RJ_RED <= "11"; + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- +THE_TDC : entity work.ffarray + generic map( + CHANNELS => 1 + ) + port map( + CLK => CLK_125, + SYSCLK => clk_sys, + RESET_IN => reset_i, + SIGNAL_IN => INP(0 downto 0), + SPIKE_REJECT=> '0', +-- DATA_OUT => tdc_data, +-- READ_IN => tdc_read, + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + EMPTY_OUT => tdc_empty + ); + + +-- TEST(8 downto 1) <= clk_tdc; + + + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +readout_tx(0).data_finished <= '1'; +readout_tx(0).data_write <= '0'; +readout_tx(0).busy_release <= '1'; + +end architecture; + + +