From: hadeshyp Date: Thu, 28 Feb 2013 14:54:05 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ef7cde3c9c48ee0e39451e77985ad121d61b0aee;p=trb3.git *** empty log message *** --- diff --git a/syncmode/sim/sim.mpf b/syncmode/sim/sim.mpf index e00d7af..3f08029 100644 --- a/syncmode/sim/sim.mpf +++ b/syncmode/sim/sim.mpf @@ -1656,7 +1656,7 @@ Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v Project_File_3 = /d/jspc22/trb/cvs/trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1359136923 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_4 = /d/jspc22/trb/cvs/trbnet/media_interfaces/med_ecp3_sfp_sync.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1361370779 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1361370779 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_5 = /d/jspc22/trb/cvs/trbnet/media_interfaces/sync/rx_reset_fsm.vhd Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1359640087 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_6 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd @@ -1670,11 +1670,11 @@ Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v Project_File_10 = /d/jspc22/trb/cvs/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1359555184 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_11 = /d/jspc22/trb/cvs/trbnet/media_interfaces/sync/rx_control.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1361376401 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1361376401 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_12 = /d/jspc22/trb/cvs/trbnet/media_interfaces/sync/tx_control.vhd Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1359730708 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_13 = /d/jspc22/trb/cvs/trbnet/media_interfaces/sync/med_sync_define.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1360842735 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1360842735 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/syncmode/sim/wave.do b/syncmode/sim/wave.do index a7d71dc..0c2806a 100644 --- a/syncmode/sim/wave.do +++ b/syncmode/sim/wave.do @@ -267,8 +267,8 @@ add wave -noupdate -radix hexadecimal /med_ecp3_sfp_sync_tb/THE_MASTER/THE_RX_FS add wave -noupdate -radix hexadecimal /med_ecp3_sfp_sync_tb/THE_MASTER/THE_RX_FSM/timer2 add wave -noupdate -radix hexadecimal /med_ecp3_sfp_sync_tb/THE_MASTER/THE_RX_FSM/tx_pll_lol_qd_s_int TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -configure wave -namecolwidth 416 +WaveRestoreCursors {{Cursor 1} {3980337070 ps} 0} +configure wave -namecolwidth 218 configure wave -valuecolwidth 40 configure wave -justifyvalue left configure wave -signalnamewidth 1 @@ -282,4 +282,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ps} {13780 ps} +WaveRestoreZoom {3980233620 ps} {3980498420 ps} diff --git a/syncmode/trb3_central.vhd b/syncmode/trb3_central.vhd index 90ce502..ea6cf3f 100644 --- a/syncmode/trb3_central.vhd +++ b/syncmode/trb3_central.vhd @@ -296,7 +296,20 @@ signal tx_dlm_i : std_logic; attribute syn_preserve of spictrl_addr : signal is true; attribute syn_keep of spimem_addr : signal is true; attribute syn_preserve of spimem_addr : signal is true; - +component DCS +-- synthesis translate_off +generic + ( +DCSMODE : string :=“POS” +); +-- synthesis translate_on + +port ( +CLK0 :in std_logic ; +CLK1 :in std_logic ; +SEL :in std_logic ; +DCSOUT :out std_logic) ; +end component; begin --------------------------------------------------------------------------- @@ -345,17 +358,45 @@ THE_MAIN_PLL : pll_in200_out100 LOCK => pll_lock ); -gen_sync_clocks : if SYNC_MODE = c_YES generate - clk_100_i <= rx_clock_100; - clk_200_i <= rx_clock_200; -end generate; - -gen_local_clocks : if SYNC_MODE = c_NO generate - clk_100_i <= clk_100_internal; - clk_200_i <= clk_200_internal; -end generate; - - +--Temporary clock switch for debugging, should be not used! + DCSInst0: DCS + -- synthesis translate_off + generic map ( + DCSMODE => “POS” + ); + -- synthesis translate_on + port map ( + SEL => TEST_LINE(16), + CLK0 => clk_100_internal, + CLK1 => rx_clock_100, + DCSOUT => clk_100_i + ); + + DCSInst1: DCS + -- synthesis translate_off + generic map ( + DCSMODE => “POS” + ); + -- synthesis translate_on + port map ( + SEL => TEST_LINE(16), + CLK0 => clk_200_internal, + CLK1 => rx_clock_200, + DCSOUT => clk_200_i + ); + +-- +-- gen_sync_clocks : if SYNC_MODE = c_YES generate +-- clk_100_i <= rx_clock_100; +-- clk_200_i <= rx_clock_200; +-- end generate; +-- +-- gen_local_clocks : if SYNC_MODE = c_NO generate +-- clk_100_i <= clk_100_internal; +-- clk_200_i <= clk_200_internal; +-- end generate; +-- +-- --------------------------------------------------------------------------- -- The TrbNet media interface (Uplink) @@ -370,7 +411,6 @@ THE_MEDIA_UPLINK : med_ecp3_sfp_sync SYSCLK => clk_100_i, RESET => reset_i, CLEAR => clear_i, - CLK_EN => '1', --Internal Connection MED_DATA_IN => med_data_out(15 downto 0), MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), @@ -418,7 +458,7 @@ SFP_TXDIS(7 downto 2) <= (others => '1'); --SFP_TXDIS(8 downto 6) <= (others => '1'); - +tx_dlm_i <= common_ctrl_regs(31); -- Be careful when setting the MII_NUMBER and MII_IS_* generics! @@ -872,7 +912,7 @@ LED_YELLOW <= link_ok; --debug(3); TEST_LINE(16) <= 'Z'; TEST_LINE(31 downto 17) <= med_stat_debug(31 downto 17); - CLK_TEST_OUT <= clk_100_internal & clk_200_i & clk_100_i; + CLK_TEST_OUT <= clk_100_internal & tx_dlm_i & rx_dlm_i; -- FPGA1_CONNECTOR(0) <= '0';