From: Michael Boehmer Date: Mon, 16 May 2022 12:42:43 +0000 (+0200) Subject: clean up X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f01307108cc9b1bea94dac93cef13227c0b192da;p=trbnet.git clean up --- diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd index 5a8cdca..7c3c528 100644 --- a/media_interfaces/med_ecp5_sfp_sync.vhd +++ b/media_interfaces/med_ecp5_sfp_sync.vhd @@ -104,11 +104,11 @@ signal hdinp : std_logic; signal hdinn : std_logic; signal hdoutp : std_logic; signal hdoutn : std_logic; +signal stat_med : std_logic_vector(31 downto 0); + attribute nopad : string; attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; -signal stat_med : std_logic_vector(31 downto 0); - begin reset_n <= not RESET; @@ -116,14 +116,6 @@ clk_200_ref <= CLK_REF_FULL; SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready --- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate --- clk_200_i <= clk_rx_full; --- end generate; --- --- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate --- clk_200_i <= clk_200_internal; --- end generate; - ------------------------------------------------- -- Serdes ------------------------------------------------- @@ -156,7 +148,6 @@ gen_pcs0 : if SERDES_NUM = 0 or SERDES_NUM = 1 generate -- same entity in any ca serdes_sync_0_tx_pcs_rst_c => tx_pcs_rst, serdes_sync_0_rx_serdes_rst_c => rx_serdes_rst, - serdes_sync_0_sci_wrdata => sci_data_in_i, serdes_sync_0_sci_rddata => sci_data_out_i, serdes_sync_0_sci_addr => sci_addr_i, @@ -184,63 +175,7 @@ gen_pcs0 : if SERDES_NUM = 0 or SERDES_NUM = 1 generate -- same entity in any ca serdes_sync_0_rsl_tx_rdy => tx_ready ); end generate; --- gen_pcs1 : if SERDES_NUM = 1 generate --- THE_SERDES : entity work.pcs1 --- port map( --- serdes_sync_0_hdinp => hdinp, --- serdes_sync_0_hdinn => hdinn, --- serdes_sync_0_hdoutp => hdoutp, --- serdes_sync_0_hdoutn => hdoutn, --- serdes_sync_0_rxrefclk => CLK_INTERNAL_FULL, --- serdes_sync_0_rx_pclk => clk_rx_full, --- serdes_sync_0_tx_pclk => clk_tx_full, --- --- serdes_sync_0_txdata => tx_data, --- serdes_sync_0_tx_k(0) => tx_k, --- serdes_sync_0_tx_force_disp(0) => '0', --- serdes_sync_0_tx_disp_sel(0) => '0', --- serdes_sync_0_rxdata => rx_data, --- serdes_sync_0_rx_k(0) => rx_k, --- serdes_sync_0_rx_disp_err(0) => open, --- serdes_sync_0_rx_cv_err(0) => rx_error, --- --- serdes_sync_0_tx_idle_c => '0', --- serdes_sync_0_signal_detect_c => '0', --- serdes_sync_0_rx_los_low_s => rx_los_low, --- serdes_sync_0_lsm_status_s => lsm_status, --- serdes_sync_0_rx_cdr_lol_s => rx_cdr_lol, --- serdes_sync_0_rx_pcs_rst_c => rx_pcs_rst, --- serdes_sync_0_tx_pcs_rst_c => tx_pcs_rst, --- serdes_sync_0_rx_serdes_rst_c => rx_serdes_rst, --- --- --- serdes_sync_0_sci_wrdata => sci_data_in_i, --- serdes_sync_0_sci_rddata => sci_data_out_i, --- serdes_sync_0_sci_addr => sci_addr_i, --- serdes_sync_0_sci_en_dual => reset_n, --- serdes_sync_0_sci_sel_dual => sci_ch_i(4), --- serdes_sync_0_sci_en => reset_n, --- serdes_sync_0_sci_sel => sci_ch_i(0), --- serdes_sync_0_sci_rd => sci_read_i, --- serdes_sync_0_sci_wrn => sci_write_i, --- serdes_sync_0_sci_int => open, --- --- serdes_sync_0_cyawstn => '0', --? --- serdes_sync_0_rst_dual_c => rst_qd, --- serdes_sync_0_serdes_rst_dual_c => '0', --- serdes_sync_0_tx_pwrup_c => '1', --- serdes_sync_0_rx_pwrup_c => '1', --- serdes_sync_0_serdes_pdb => '1', --- serdes_sync_0_tx_serdes_rst_c => tx_serdes_rst, --- --- serdes_sync_0_pll_refclki => CLK_REF_FULL, --- serdes_sync_0_pll_lol => tx_pll_lol, --- serdes_sync_0_rsl_disable => '1', --- serdes_sync_0_rsl_rst => '0', --- serdes_sync_0_rsl_rx_rdy => rx_ready, --- serdes_sync_0_rsl_tx_rdy => tx_ready --- ); --- end generate; + gen_pcs2 : if SERDES_NUM = 2 generate THE_SERDES : entity work.pcs2 port map( @@ -270,7 +205,6 @@ gen_pcs2 : if SERDES_NUM = 2 generate serdes_sync_0_tx_pcs_rst_c => tx_pcs_rst, serdes_sync_0_rx_serdes_rst_c => rx_serdes_rst, - serdes_sync_0_sci_wrdata => sci_data_in_i, serdes_sync_0_sci_rddata => sci_data_out_i, serdes_sync_0_sci_addr => sci_addr_i, @@ -378,7 +312,7 @@ THE_SCI_READER : entity work.sci_reader MEDIA_STATUS_REG_IN(127 downto 96) => stat_med, MEDIA_STATUS_REG_IN(255 downto 128) => (others => '0'), DEBUG_OUT => open - ); + ); STAT_DEBUG(11 downto 0) <= debug_med_sync_control_i(11 downto 0); STAT_DEBUG(15 downto 12) <= (others => '0');