From: hadeshyp <hadeshyp>
Date: Thu, 10 Sep 2009 10:10:02 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f07fca7a8fe3811930818e1e768c95d9c3bd6f4c;p=mdcoep.git

*** empty log message ***
---

diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index 36d370f..85339af 100644
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -27,6 +27,7 @@ entity mdc_oepb is
       CLK_FF    : out std_logic;
       DATA_FF   : out std_logic;
       MRES      : out std_logic;
+      CS        : in  std_logic_vector(2 downto 1);
       --ADC
       ADC_SCK       : out std_logic;
       ADC_SDI       : out std_logic;
@@ -191,6 +192,9 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal flash_rom_clk    : std_logic;
   signal next_flash_rom_clk : std_logic;
 
+  signal reg_CS : std_logic_vector(2 downto 1);
+  signal real_flash_rom_select : std_logic_vector(1 downto 0);
+
 
 
 --   signal flash_mem_data : std_logic_vector(31 downto 0);
@@ -308,6 +312,24 @@ begin
   DATA_FF <= flash_rom_select;
 
 
+  THE_CS_SYNC : signal_sync
+    generic map(
+      DEPTH => 2,
+      WIDTH => 2
+      )
+    port map(
+      RESET    => reset_internal,
+      D_IN     => CS,
+      CLK0     => CLK,
+      CLK1     => CLK,
+      D_OUT    => reg_CS
+      );
+
+
+  real_flash_rom_select <= "00" when reg_CS = "10" else
+                           "01" when reg_CS = "01" else
+                           "10";
+
 ---------------------------------------------------------------------
 -- trbnet endpoint
 ---------------------------------------------------------------------
@@ -531,8 +553,8 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_DATA_OUT(4*32+31 downto 4*32+1) => open,
     BUS_ADDR_OUT(4*16+15 downto 4*16)   => open,
     BUS_TIMEOUT_OUT(4)                  => open,
-    BUS_DATA_IN(4*32)                   => flash_rom_select,
-    BUS_DATA_IN(4*32+31 downto 4*32+1)  => (others => '0'),
+    BUS_DATA_IN(4*32+1 downto 4*32)     => real_flash_rom_select,
+    BUS_DATA_IN(4*32+31 downto 4*32+2)  => (others => '0'),
     BUS_DATAREADY_IN(4)                 => flash_rom_read,
     BUS_WRITE_ACK_IN(4)                 => flash_rom_write,
     BUS_NO_MORE_DATA_IN(4)              => '0',