From: Jan Michel Date: Mon, 18 Dec 2017 12:54:18 +0000 (+0100) Subject: Update tdc template design X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f1bc280c1aa792a281879e141a5d21f813bfdb8d;p=trb3sc.git Update tdc template design --- diff --git a/scripts/nodes_frankfurt.txt b/scripts/nodes_frankfurt.txt index 5ac6e94..e62a86e 100644 --- a/scripts/nodes_frankfurt.txt +++ b/scripts/nodes_frankfurt.txt @@ -2,12 +2,12 @@ [jspc29] SYSTEM = linux -CORENUM = 3 -ENV = /d/jspc29/lattice/38_settings.sh +CORENUM = 4 +ENV = /d/jspc29/lattice/310_settings.sh WORKDIR = /d/jspc22/trb/git/trb3sc/tdctemplate/workdir [jspc57] SYSTEM = linux CORENUM = 7 -ENV = /d/jspc29/lattice/38_settings.sh +ENV = /d/jspc29/lattice/310_settings.sh WORKDIR = /d/jspc22/trb/git/trb3sc/tdctemplate/workdir diff --git a/tdctemplate/config.vhd b/tdctemplate/config_32_sfp_kel.vhd similarity index 100% rename from tdctemplate/config.vhd rename to tdctemplate/config_32_sfp_kel.vhd diff --git a/tdctemplate/config_48_crate_4conn.vhd b/tdctemplate/config_48_crate_4conn.vhd new file mode 100644 index 0000000..2cb7441 --- /dev/null +++ b/tdctemplate/config_48_crate_4conn.vhd @@ -0,0 +1,143 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + + --pinout to be used - don't forget to change config_compile.pl as well + -- 0: 32 Pin AddOn + -- 1: 4conn AddOn + -- 2: 2x KEL on board + + constant PINOUT : integer := 1; + +--TDC settings + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 49; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + --ring buffer size: 32,64,96,128,dyn + constant TDC_DATA_FORMAT : integer := 0; + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 4095; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3CF"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"70"; + +--set to 0 for backplane serdes, set to 3 for front SFP serdes + constant SERDES_NUM : integer := 0; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 48; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 52; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"73", x"63", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"85",x"0a", + x"86",x"0a", + x"87",x"0a", + others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/tdctemplate/config_compile_frankfurt.pl b/tdctemplate/config_compile_frankfurt.pl index 1c5bcb3..611f005 100644 --- a/tdctemplate/config_compile_frankfurt.pl +++ b/tdctemplate/config_compile_frankfurt.pl @@ -1,8 +1,8 @@ TOPNAME => "trb3sc_tdctemplate", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', -synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/N-2017.09-1/', nodelist_file => 'nodes_frankfurt.txt', # synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/tdctemplate/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../trb3sc_tdctemplate.prj\" #", #Include only necessary lpf files diff --git a/tdctemplate/par.p2t b/tdctemplate/par.p2t index c35a699..1a65a74 100644 --- a/tdctemplate/par.p2t +++ b/tdctemplate/par.p2t @@ -13,9 +13,8 @@ -w -l 5 -i 6 --n 1 --t 6 --s 1 +-t 26 +# -s 1 #save how many -c 0 -e 0 -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=ON:parHoldLimit=10000 diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index 5b65338..60ff437 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -217,7 +217,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" add_file -vhdl -lib work "./trb3sc_tdctemplate.vhd" -#add_file -fpga_constraint "./synplify.fdc" +add_file -constraint "./trb3sc_tdctemplate.sdc" diff --git a/tdctemplate/trb3sc_tdctemplate.sdc b/tdctemplate/trb3sc_tdctemplate.sdc new file mode 100644 index 0000000..dc4de07 --- /dev/null +++ b/tdctemplate/trb3sc_tdctemplate.sdc @@ -0,0 +1,6 @@ +define_clock {CLK_CORE_PCLK} -name {CLK_CORE_PCLK} -freq 200 +define_clock {pll_in125_out33|CLKOP_inferred_clock} -name {clk_cal} -freq 33 +define_clock {clock_reset_handler|REF_CLK_OUT_inferred_clock} -name {ref_clk} -freq 200 +define_clock {clock_reset_handler|SYS_CLK_OUT_inferred_clock} -name {sys_clk} -freq 100 +define_clock {serdes_sync_0|rx_full_clk_ch0_inferred_clock} -name {full_rx} -freq 200 +define_clock {System} -name{system} -freq 100 \ No newline at end of file