From: hadeshyp Date: Tue, 22 Jun 2010 12:36:25 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=f23b216ea8bb006c5ad66da714daa53a0a04f4ef;p=ctsaddon.git *** empty log message *** --- diff --git a/compile1_frankfurt.pl b/compile1_frankfurt.pl new file mode 100755 index 0000000..83c8ecf --- /dev/null +++ b/compile1_frankfurt.pl @@ -0,0 +1,154 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +# +# Command line for synplify_pro +# + + +use Data::Dumper; + +use warnings; +use strict; + +my $lattice_path = '/d/sugar/lattice/ispLEVER8.0/isptools/'; +#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; +my $synplify_path = '/d/sugar/lattice/synplify/fpga_c200906sp1'; + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; + + +my $TOPNAME="cts_fpga1"; + +my $FAMILYNAME="LatticeSCM"; +my $DEVICENAME="LFSCM3GA40EP1"; +my $PACKAGE="FFBGA1020"; +my $SPEEDGRADE="7"; + + +#create full lpf file +system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +#my $c=$synplify_path."synplify_pro_oem -batch $TOPNAME".".prj"; +#my $c="$synplify_path/bin/synplify_pro -Pro -prj $TOPNAME".".prj"; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +#if ($r) { +#$c="cat $TOPNAME.srr"; +#system($c); +#exit 129; +#} + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "bdabdhsadbhjasdhasldhbas"; + exit 129; + } +} +#if (0){ + +$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + + +system("rm $TOPNAME.ncd"); + +#$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/cts_fpga1.p2t b/cts_fpga1.p2t new file mode 100644 index 0000000..9ce01fc --- /dev/null +++ b/cts_fpga1.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 1 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: + diff --git a/cts_fpga1.prj b/cts_fpga1.prj new file mode 100644 index 0000000..273a977 --- /dev/null +++ b/cts_fpga1.prj @@ -0,0 +1,151 @@ +#-- Synplicity, Inc. +#-- Version 9.0 +#-- Project file ../ctsaddon/cts_fpga1.prj + + + +#add_file options +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" +add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" + + +add_file -vhdl -lib work "../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" + + + +#Lattice SCM files +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in200_out100.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd" +#Wrong filename, but hard to change now... + + +add_file -vhdl -lib work "cts_fpga1.vhd" + +#Some of these files have to be regenerated +# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd" +# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_clock_generator.vhd" +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" + + + + + + + +#implementation: "workdir" +impl -add workdir -type fpga + +#device options +set_option -technology LATTICE-SCM +set_option -part LFSCM3GA40EP1 +set_option -package FF1020C +set_option -speed_grade -5 +set_option -part_companion "" + +#compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +#set_option -resource_sharing 0 +set_option -top_module "cts_fpga1" + +#map options +set_option -frequency auto +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +set_option -force_gsr auto +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 + + + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_format "edif" +project -result_file "workdir/cts_fpga1.edf" + + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd index d468723..43a0682 100644 --- a/cts_fpga1.vhd +++ b/cts_fpga1.vhd @@ -9,9 +9,15 @@ use work.trb_net_components.all; use work.version.all; entity cts_fpga1 is + generic( + NUM_STAT_REGS : integer range 0 to 6 := 2; + NUM_CTRL_REGS : integer range 0 to 6 := 2; + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FF01"; + REGIO_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001" + ); port( --Clocks - CLK200_IN : in std_logic; + CLK_200_IN : in std_logic; ADO_CLKOUT : out std_logic; --Resets RESET_FPGA_1 : in std_logic; @@ -20,7 +26,7 @@ entity cts_fpga1 is ADO_TTL : inout std_logic_vector(46 downto 0); FS_PE : inout std_logic_vector(11 downto 5); --To 2nd FPGA - FFC : inout std_logic_vector(23 downto 0); + FFC : inout std_logic_vector(22 downto 0); --Trigger IO LVDS_IN : in std_logic_vector(63 downto 0); LVDS_OUT : out std_logic_vector(15 downto 0); @@ -54,12 +60,13 @@ entity cts_fpga1 is TRB3_MOD : inout std_logic_vector(2 downto 0); TRB3_TX_DIS : out std_logic; --Other + ONEWIRE_MONITOR_IN : in std_logic; RS1 : out std_logic_vector(3 downto 0); RS2 : out std_logic_vector(3 downto 0); DIS1 : out std_logic_vector(2 downto 0); DIS2 : out std_logic_vector(2 downto 0); --Debug - TEST_LINE : out std_logic_vector(31 downto 0); + TEST_LINE : out std_logic_vector(31 downto 0) ); attribute syn_useioff : boolean; @@ -98,3 +105,391 @@ entity cts_fpga1 is attribute syn_useioff of TRB3_TX_DIS : signal is false; end entity; + +architecture cts_fpga1_arch of cts_fpga1 is + + --Clock & Reset + signal clk_100 : std_logic; + signal clk_200 : std_logic; + signal clk_en : std_logic; + signal make_reset_via_network : std_logic; + signal pll_locked : std_logic; + signal reset_i_100 : std_logic; + signal reset_async : std_logic; + signal delayed_restart_fpga : std_logic; + signal restart_fpga_counter : unsigned(11 downto 0); + + --media interface to endpoint + signal med_data_in : std_logic_vector (16-1 downto 0); + signal med_packet_num_in : std_logic_vector (3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + signal med_data_out : std_logic_vector (16-1 downto 0); + signal med_packet_num_out : std_logic_vector (3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_stat_op : std_logic_vector (16-1 downto 0); + signal med_ctrl_op : std_logic_vector (16-1 downto 0); + signal med_stat_debug : std_logic_vector (64-1 downto 0); + + --endpoint RegIo to bus handler + signal regio_addr_out : std_logic_vector (16-1 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (32-1 downto 0); + signal regio_data_in : std_logic_vector (32-1 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --SPI for flash programming + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector (31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector (31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector (31 downto 0); + signal spimem_addr : std_logic_vector (5 downto 0); + signal spimem_data_out : std_logic_vector (31 downto 0); + signal spimem_ack : std_logic; + signal spi_bram_addr : std_logic_vector (7 downto 0); + signal spi_bram_wr_d : std_logic_vector (7 downto 0); + signal spi_bram_rd_d : std_logic_vector (7 downto 0); + signal spi_bram_we : std_logic; + + --endpoint LVL1 trigger + signal trg_type : std_logic_vector (3 downto 0); + signal trg_valid_timing : std_logic; + signal trg_valid_notiming : std_logic; + signal trg_invalid : std_logic; + signal trg_data_valid : std_logic; + signal trg_number : std_logic_vector (15 downto 0); + signal trg_code : std_logic_vector (7 downto 0); + signal trg_information : std_logic_vector (23 downto 0); + signal trg_error_pattern : std_logic_vector (31 downto 0); + signal trg_release : std_logic; + signal trg_int_trg_number : std_logic_vector (15 downto 0); + + --FEE + signal fee_trg_release : std_logic; + signal fee_trg_statusbits : std_logic_vector (31 downto 0); + signal fee_data : std_logic_vector (31 downto 0); + signal fee_data_local : std_logic_vector (31 downto 0); + signal fee_data_write : std_logic; + signal fee_data_finished : std_logic; + signal fee_data_almost_full : std_logic; + + --endpoint RegIo registers + signal regio_common_stat_reg : std_logic_vector (std_COMSTATREG*32-1 downto 0); + signal regio_common_ctrl_reg : std_logic_vector (std_COMCTRLREG*32-1 downto 0); + signal regio_stat_registers : std_logic_vector (32*2**(NUM_STAT_REGS)-1 downto 0); + signal regio_ctrl_registers : std_logic_vector (32*2**(NUM_CTRL_REGS)-1 downto 0); + signal regio_common_stat_strobe : std_logic_vector ((std_COMSTATREG)-1 downto 0); + signal regio_common_ctrl_strobe : std_logic_vector ((std_COMCTRLREG)-1 downto 0); + signal regio_stat_strobe : std_logic_vector (2**(NUM_STAT_REGS)-1 downto 0); + signal regio_ctrl_strobe : std_logic_vector (2**(NUM_CTRL_REGS)-1 downto 0); + signal my_address : std_logic_vector (15 downto 0); + + --Timers + signal timing_trigger_feedback : std_logic; + signal global_time : std_logic_vector (31 downto 0); + signal local_time : std_logic_vector (7 downto 0); + signal time_since_last_trg : std_logic_vector (31 downto 0); + signal timer_ticks : std_logic_vector (1 downto 0); + + + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset state machine +--------------------------------------------------------------------------- + clk_en <= '1'; + make_reset_via_network <= MED_STAT_OP(0*16 + 13); + + THE_PLL : pll_in200_out100 + port map( + CLK => CLK_200_IN, + CLKOP => clk_100, + CLKOS => open, + LOCK => pll_locked + ); + + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"0EEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => CLK_200_IN, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_locked, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => make_reset_via_network, -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => reset_async, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i_100, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Media Interface +--------------------------------------------------------------------------- + + +--------------------------------------------------------------------------- +-- TrbNet Endpoint +--------------------------------------------------------------------------- + + THE_ENDPOINT: trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => NUM_STAT_REGS, + REGIO_NUM_CTRL_REGS => NUM_CTRL_REGS, + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ADDRESS => REGIO_INIT_ADDRESS, + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + REGIO_INIT_ENDPOINT_ID => REGIO_ENDPOINT_ID, + REGIO_COMPILE_VERSION => x"0000", + REGIO_HARDWARE_VERSION => x"51000000", + REGIO_USE_1WIRE_INTERFACE => c_MONITOR, + CLOCK_FREQUENCY => 100, + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 11, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**11-520, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-10 + ) + port map( + CLK => clk_100, + RESET => reset_i_100, + CLK_EN => clk_en, + + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + -- LVL1 trigger APL + TRG_TIMING_TRG_RECEIVED_IN => timing_trigger_feedback, + LVL1_TRG_DATA_VALID_OUT => trg_data_valid, + LVL1_VALID_TIMING_TRG_OUT => trg_valid_timing, + LVL1_VALID_NOTIMING_TRG_OUT=> trg_valid_notiming, + LVL1_INVALID_TRG_OUT => trg_invalid, + LVL1_TRG_TYPE_OUT => trg_type, + LVL1_TRG_NUMBER_OUT => trg_number, + LVL1_TRG_CODE_OUT => trg_code, + LVL1_TRG_INFORMATION_OUT => trg_information, + LVL1_INT_TRG_NUMBER_OUT => trg_int_trg_number, + + -- FEE Port + FEE_TRG_RELEASE_IN(0) => fee_trg_release, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits, + FEE_DATA_IN => fee_data, + FEE_DATA_WRITE_IN(0) => fee_data_write, + FEE_DATA_FINISHED_IN(0) => fee_data_finished, + FEE_DATA_ALMOST_FULL_OUT(0)=> fee_data_almost_full, + + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => regio_common_stat_reg, + REGIO_COMMON_CTRL_REG_OUT => regio_common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => regio_common_stat_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => regio_common_ctrl_strobe, + + REGIO_STAT_REG_IN => regio_stat_registers, --start 0x80 + REGIO_CTRL_REG_OUT => regio_ctrl_registers, --start 0xc0 + REGIO_STAT_STROBE_OUT => regio_stat_strobe, + REGIO_CTRL_STROBE_OUT => regio_ctrl_strobe, + + --following ports only used when using internal data port + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => open, + ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks + ); + + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- +-- D000 spi status register +-- D001 spi ctrl register +-- D100 - D13F spi memory + + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) + ) + port map( + CLK => clk_100, + RESET => reset_i_100, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + STAT_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER: spi_master + port map( + CLK_IN => clk_100, + RESET_IN => reset_i_100, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => SPI_CS_OUT, + SPI_SDI_IN => SPI_SO_IN, + SPI_SDO_OUT => SPI_SI_OUT, + SPI_SCK_OUT => SPI_CLK_OUT, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + + -- data memory for SPI accesses + THE_SPI_MEMORY: spi_databus_memory + port map( + CLK_IN => clk_100, + RESET_IN => reset_i_100, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + PROC_REBOOT : process (clk_100) + begin + if reset_i_100 = '1' then + PROGRAMN_OUT <= '1'; + delayed_restart_fpga <= '0'; + restart_fpga_counter <= x"FFF"; + elsif rising_edge(clk_100) then + PROGRAMN_OUT <= not delayed_restart_fpga; + delayed_restart_fpga <= '0'; + if regio_common_ctrl_reg(15) = '1' then + restart_fpga_counter <= x"000"; + elsif restart_fpga_counter /= x"FFF" then + restart_fpga_counter <= restart_fpga_counter + 1; + if restart_fpga_counter >= x"F00" then + delayed_restart_fpga <= '1'; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- Unused Ports +--------------------------------------------------------------------------- + FFC <= (others => 'Z'); + DIS1 <= (others => 'Z'); + DIS2 <= (others => 'Z'); + RS1 <= (others => 'Z'); + RS2 <= (others => 'Z'); + + +--------------------------------------------------------------------------- +-- Debug +--------------------------------------------------------------------------- + proc_testline : process(clk_100) + begin + if rising_edge(clk_100) then + TEST_LINE(30 downto 0) <= (others => '0'); + end if; + end process; + + TEST_LINE(31) <= clk_100; + + +end architecture;